Laboratorium Sistem Digital

Program Studi Teknik Elektro

Institut Teknologi Del

Nama Kuliah (Kode

Praktikum Arsitektur Sistem Komputer (NWS3103)
MK)
Tahun Ajaran/ Semester 2018-2019/5 (Ganjil)
Modul 1 2 3 4 5
Nama Praktikan - NIM Basry A Sihotang – 14S16040
Tanggal Praktikum 15 November 2018

Tugas Pendahuluan
1. 32 bit 2 to 1 Multiplexer
VHDL CODE :
library ieee;
use ieee.std_logic_1164.all;

entity twomultiplexer is
port(
D1 : IN std_logic_vector (31 DOWNTO 0);
D2 : IN std_logic_vector (31 DOWNTO 0);
Y : OUT std_logic_vector (31 DOWNTO 0);
S : IN std_logic
);
end twomultiplexer;
architecture behavioral of twomultiplexer is
BEGIN
Y <= D1 when (S = '1') else D2;
END behavioral;
FUNCTIONAL SIMULATIONAL

TIMING SIMULATIONAL

2. 32 bit 4 to 1 Multiplexer
VHDL CODE :
library ieee;
use ieee.std_logic_1164.all;

entity formulti is
port (
D1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
D2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
D3 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

Laboratorium Sistem Digital 2018

 Laboratorium Sistem Digital
Program Studi Teknik Elektro
Institut Teknologi Del

D4 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

Y : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
S : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END formulti;
architecture behavioral of formulti is
BEGIN
Y <= D1 when (S = "00") else
D2 when (S = "01") else
D3 when (S = "10") else D4;
END behavioral;
FUNCTIONAL SIMULATIONAL

TIMING SIMULATIONAL

3. 5 bit 4 to 1 Multiplexer
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;

entity formulti5bit is
port (
D1 : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
D2 : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
D3 : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
D4 : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
Y : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
S : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END formulti5bit;
architecture behavioral of formulti5bit is
BEGIN
Y <= D1 when (S = "00") else
D2 when (S = "01") else
D3 when (S = "10") else
D4;
END behavioral;
FUNCTIONAL SIMULATIONAL

Laboratorium Sistem Digital 2018

 Laboratorium Sistem Digital
Program Studi Teknik Elektro
Institut Teknologi Del

TIMING SIMULATIONAL

4. KOMPARATOR
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;

entity komparator is
port (
D1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
D2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
EQ : OUT STD_LOGIC
);
end komparator;

architecture behavioral of komparator is

BEGIN
EQ <= '1' when D1=D2 else '0';
end behavioral;
FUNCTIONAL SIMULATION

TIMING SIMULATION

5. BUS MERGING
VHDL CODE :
library ieee;
use ieee.std_logic_1164.all;

entity bus_merger is
port (

Laboratorium Sistem Digital 2018

 Laboratorium Sistem Digital
Program Studi Teknik Elektro
Institut Teknologi Del

DATA_IN1 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

DATA_IN2 : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
DATA_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end bus_merger;

architecture behavioral of bus_merger is

begin
DATA_OUT(31 DOWNTO 28) <= DATA_IN1 (3 DOWNTO 0);
DATA_OUT(27 DOWNTO 0) <= DATA_IN2 (27 DOWNTO 0);
end behavioral;
FUNCTIONAL SIMULATION

TIMING SIMULATION

Laboratorium Sistem Digital 2018

 Laboratorium Sistem Digital
Program Studi Teknik Elektro
Institut Teknologi Del

Laboratorium Sistem Digital 2018