USART

The USART is a full-duplex synchronous/asynchronous receiver-transmitter proven in high-volume devices

from National Semiconductor and available exclusively from IPextreme as synthesizable IP.

The USART supports a wide range of software programmable baud rates and data formats and operates in
either Synchronous or Asynchronous (UART) mode. It implements automatic parity generation and several
error detection schemes. The USART is capable of detecting a wakeup pattern to selectively enable the
receiver and implements flow control logic for hardware handshaking.

The host interface of the USART complies with the AMBA 2.0 APB protocol. Control registers within the
USART provide CPU control of baud rate, frame format, wakeup pattern detection, operating mode, and
enabling/disabling interrupts. Status registers provide interrupt and error status. In addition, there are
registers that hold the transmit/receive data.

In Asynchronous (UART) mode, the USART communicates with other devices using two signals: transmit
(TDX) and receive (RDX). In Synchronous mode, the USART communicates with other devices using three
signals: transmit (TDX), receive (RDX), and clock (CKX); data bits are transferred synchronously with the
CKX signal. Flow control is available in both Asynchronous and Synchronous modes through RTS/CTS
signaling.

To reduce chip-level pin count, the USART interface signals can be shared with other on-chip functions
through a General Purpose I/O (GPIO) Controller.

FEATURES

• Full-duplex double-buffered receiver/transmitter

• Synchronous operation using the CKX clock pin
• CKX can be generated internally or externally
• Asynchronous (UART) operation
• Programmable baud rate between CLK/2 and CLK/32768 baud
• Programmable frame formats
o 7, 8, or 9 data bits
o 1 or 2 stop bits
o Odd, even, mark, space, or no parity
• Hardware support of parity-bit generation during transmission and parity-bit check during reception
 • Software-controlled break transmission and detection
• Interrupt on transmit buffer empty, receive buffer full, receive error, and delta clear-to-send (flow
control mode) conditions, each with a separate interrupt enable
• Internal diagnostic capability
• Automatic error detection
o Parity error
o Framing error
o Data overrun error
• 9-bit Attention mode
• DMA support for transmit and receive with separate enables
• Hardware flow control functions
o Clear-to-send (CTS)
o Request-to-send (RTS)
• Wakeup pattern detection according to ISO14230/KWP2000
• Debug support: Freeze/suspend USART activity

INTERFACES

• AMBA 2.0 APB host interface

o 8-bit read/write data buses
o 10-bit address bus
• USART pins (CKX, TXD, RXD, CTS, RTS) through chip I/O pads (optionally through a GPIO
Controller )
• DMA interface
o One transmit DMA channel
o One receive DMA channel
• Clock interface
o APB clock for registers, DMA, interrupt functions, and for baud rate generation in
Asynchronous mode
o Baud rate clock input for Synchronous mode with external baud rate generation
o Baud rate clock output for Synchronous mode with internal baud rate generation
• Interrupt interface (four interrupts)
• One asynchronous reset input
• Freeze/suspend interface
• DFT signals

HARDWARE CONFIGURATION OPTIONS

GATE COUNT AND PERFORMANCE
Gate count and maximum frequency depend on synthesis tool and target technology. Example values for a
typical 130-nm technology are:

• 2300 (NAND2 equivalent) gates

• 100 MHz (APB clock)

DELIVERABLES
The USART is available in Source and Encrypted products. The Source product is fully configurable and is
delivered in plain text Verilog source code. The Encrypted product, which is available in the Core Store,
offers limited configurability (default parameter values) and is delivered in encrypted source code. Both
products include:

• Synthesizable Verilog source code (encrypted in the Encrypted product)

• Integration testbench and tests
• Documentation
• Automatic configuration through the IPextreme IP distribution and support portal
• Scripts for simulation and synthesis with support for common EDA tools

USART-processor
A universal asynchronous receiver/transmitter is a type of "asynchronous receiver/transmitter", a piece
of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in
conjunction with other communication standards such as EIA RS-232.

A UART is usually an individual (or part of an) integrated circuit used for serial communications over a
computer or peripheral device serial port. UARTs are now commonly included in microcontrollers. A dual
UART or DUART combines two UARTs into a single chip. Many modern ICs now come with a UART that
can also communicate synchronously; these devices are called USARTs (universal
synchronous/asynchronous receiver/transmitter).
Definition

• The 8251A is a programmable serial communication interface chip designed for

synchronous and asynchronous serial data communication.
• It supports the serial transmission of data.
• It is packed in a 28 pin DIP.

The functional block diagram of 825 1A consists five sections. They are:

o Read/Write control logic

o Transmitter
o Receiver
o Data bus buffer
o Modem control.

Read/Write control logic:

• The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the
8251A according to the control word written into its control register.
• It monitors the data flow.
• This section has three registers and they are control register, status register and data
buffer.
• The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with
these three registers.
• When C/D(low) is high, the control register is selected for writing control word or reading
status word.
• When C/D(low) is low, the data buffer is selected for read/write operation.
• When the reset is high, it forces 8251A into the idle mode.
• The clock input is necessary for 8251A for communication with CPU and this clock does not
control either the serial transmission or the reception rate.
Transmitter section:

• The transmitter section accepts parallel data from CPU and converts them into serial data.
• The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit
parallel data and another register called output register to convert the parallel data into
serial bits.
• When output register is empty, the data is transferred from buffer to output register. Now
the processor can again load another data in buffer register.
• If buffer register is empty, then TxRDY is goes to high.
• If output register is empty then TxEMPTY goes to high.
• The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART.
• The clock frequency can be 1,16 or 64 times the baud rate.

Receiver Section:

• The receiver section accepts serial data and convert them into parallel data
• The receiver section is double buffered, i.e., it has an input register to receive serial data
and convert to parallel, and a buffer register to hold the parallel data.
• When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit
time and samples the line again.
• If the line is still low, then the input register accepts the following bits, forms a character
and loads it into the buffer register.
• The CPU reads the parallel data from the buffer register.
• When the input register loads a parallel data to buffer register, the RxRDY line goes high.
• The clock signal RxC (low) controls the rate at which bits are received by the USART.
• During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data
transmission.
• During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of
synchronous character.
MODEM Control:

• The MODEM control unit allows to interface a MODEM to 8251A and to establish data
communication through MODEM over telephone lines.

• This unit takes care of handshake signals for MODEM interface.

Transmitting and receiving serial data

The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the serial
communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in
a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. Serial
transmission of digital information (bits) through a single wire or other medium is much more cost effective
than parallel transmission through multiple wires. A UART is used to convert the transmitted information
between its sequential and parallel form at each end of the link. Each UART contains a shift register which is
the fundamental method of conversion between serial and parallel forms.

The UART usually does not directly generate or receive the external signals used between different items of
equipment. Typically, separate interface devices are used to convert the logic level signals of the UART to
and from the external signaling levels.

Asynchronous receiving and transmitting

In asynchronous transmitting, teletype-style UARTs send a "start" bit, five to eight data bits, least-significant-
bit first, an optional "parity" bit, and then one, one and a half, or two "stop" bits. The start bit is the opposite
polarity of the data-line's idle state. The stop bit is the data-line's idle state, and provides a delay before the
next character can start. (This is called asynchronous start-stop transmission). In mechanical teletypes, the
"stop" bit was often stretched to two bit times to give the mechanism more time to finish printing a character.
A stretched "stop" bit also helps resynchronization.

The parity bit can either make the number of "one" bits between any start/stop pair odd, or even, or it can be
omitted. Odd parity is more reliable because it assures that there will always be at least one data transition,
and this permits many UARTs to resynchronize.

In synchronous transmission, the clock data is recovered separately from the data stream and no
start/stop bits are used. This improves the efficiency of transmission on suitable channels since more of the
bits sent are usable data and not character framing. An asynchronous transmission sends no characters
over the interconnection when the transmitting device has nothing to send—only idle stop bits; but a
synchronous interface must send "pad" characters to maintain synchronism between the receiver and
transmitter. The usual filler is the ASCII "SYN" character. This may be done automatically by the transmitting
device.

USART chips have both synchronous and asynchronous modes.

Asynchronous transmission allows data to be transmitted without the sender having to send a clock signal to
the receiver. Instead, the sender and receiver must agree on timing parameters in advance and special bits
are added to each word which are used to synchronize the sending and receiving units.
The start bit is always a 0 (logic low), which is also called a space. The start bit signals the receiving DTE
that a character code is coming. The next five to eight bits, depending on the code set employed, represent
the character. In the ASCII code set the eighth data bit may be a parity bit. The next one or two bits are
always in the mark (logic high, i.e., '1') condition and called the stop bit(s). They provide a "rest" interval for
the receiving DTE so that it may prepare for the next character which may be after the stop bit(s).