INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR Mid-Spring Semester 2019-20 Date of Examination : 20/02/2020 __ Session (FN/AN) FN _ Duration 2hrs ____ Full Marks 60 Subject No. : EE60004 Subject : ADVANCED POWER ELECTRONIC CONVERTE! Department/Center/School: ELECTRICAL ENGINEERING Specific charts, graph paper, log book etc., required NONE Special Instructions (if any) : This question paper has four questions. Answer all of them. Make relevant assumptions and approximations. Question 1 A three level inverter based 3.3KV induction motor drive is shown in Fig. 1. The rated loading capacity of the inverter at rated motor terminal voltage is 4MVA. Ata specific switching interval, when the inverter is at an operating condition with half the rated voltage and half the rated current, the A-phase voltage is found to be in its positive zero crossing. Assume A-B-C sequence. At this operating condition, the motor current lags the motor terminal voltage by 30° {a) For the specific switching interval described above, identify the switching states that will be used to realize the voltage vector in that interval. 15) (b) Calculate the duty cycles of operations of all the switches such that ) Average value of midpoint current Io in that switching interval is zero. 15) i) Average value of common mode voltage applied at the motor terminals in that switching interval is zero. 15] Fig. 1 Question 2 ‘The cascaded bridge inverter shown in Fig. 2 is used to drive a 3.3kV induction motor. Hybrid modulation strategy is used to modulate the inverter switches where the devices connected to V, sources are switched at fundamental frequency and the devices connected to V2 sources undergo PWM at switching frequency. Ata given operating condition, inverter applies rated voltage at the motor terminals. (@) If sine triangle comparison based PWM is used then calculate the minimum values of V; and V2 to ensure hybrid modulation and maximum possible pole voltage levels with equal voltage steps. 2] (b) With the calculated values of Vi and V2, find the duty cycles of operation of inverter switches when the ‘Acphase voltage is at its positive peak (4) Page 1 of 2(©) Plot the three phase pole voltage waveforms in one switching interval for the operating condition of (b). B) (@ If the inverter supplies 1 MW active power to the motor terminals at 0.8 pf lag, then calculate the average powers (averaged over one fundamental period) supplied by the voltage sources Vi and V2. {6] | & ea Spal PF (sag ai] [s 7 ese ode olf we Question 3 The DC bus voltage of the two level three phase voltage source inverter as shown in Fig. 3 is 600V. The inverter is feeding an induction motor at a line voltage of 200V rms and the motor current is 10A rms. The motor current fags the fundamental motor terminal voltage by 60°. The motor current can be assumed to be sinusoidal. It can be assumed that the inverter switching frequency is very high compared to the fundamental frequency. Assume one switching period to be 200us. At a specific instant, when the B-phase voltage reference is at its positive peak, draw the pole voltages Vao, Vso, Veo, line to fine voltage Vas, phase voltage Vaw and de link current Inc for one complete inverter switching period for (a) Space phasor based Pulse Width Modulation and (b) Sinusoidal Pulse Width Modulation. Dimension both the x-axis and y-axis of all the waveforms, [+7] be ® ie = 3.phase IM io 4 a Val2: Va=600V Fig. 3 Question 4 (@) Draw the circuit diagrams of 3 phase S-level DC-AC converters using (i) Capacitor clamped topology and (ii) Diode clamped topology. Clearly write down the voltages across different capacitors used in the circuits. Also, clearly write down the voltage blocking capability of different controlled and uncontrolled switches used in the circuits. (61 (b) For the S-level capacitor clamped topology the overall DC link voltage is Vue and at a specific switching interval, A-phase voltage reference is 0.45Vdc. If phase shifted carrier based sinusoidal PWM is used for this capacitor clamped multilevel converter, then calculate the duty cycles of operation of the A-phase switches and plot the resultant pole voltage waveform in that switching interval. (4) (©) Repeat (b) for the 5-level diode clamped topology. Only difference is, ievel shifted in-phase carriers are used for the diode clamped topology in place of the phase shifted carriers for modulation, 5] ~-END— Page 2 of 2