Designing

circuits for
performance

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 Designing circuits for performance

 Some techniques for improving CMOS circuit

performance
• Input Ordering Delay Effect
• Transistor Sizing
• Reducing Fan-in
• Buffer Insertion for Large CL

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 Input Ordering Delay Effect:
Input Order
 Our parasitic delay model was too simple
– Calculate parasitic delay of NAND-2 for Y falling
for two cases
• If the input A switches last.
• If the input B switches last.

2 2 Y
A 2 6C

B 2x 2C

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Input Ordering Delay Effect (Case 1)

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Input Ordering Delay Effect (Case 2)

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 Input Ordering Delay Effect:
Inner & Outer Inputs
 Inner input (A) is closest to output
2 2 Y

 Outer input (B) is closest to rail A 2

B 2

 If input arrival time is known

– Connect latest input to inner terminal
– Parasitic delay is smaller if inner input switches
last

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Transistor Sizing

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Transistor Sizing

 MN discharges only CL

 But M1 discharges all

capacitance

 So M1 may have the

greatest size
 M1>M2>….>MN

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 Reducing Fan-in

 Using deeper logic depth

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Buffer Insertion for Large CL

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Designing circuits for performance

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