2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
Approximate Multipliers for Optimal Utilization of
2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) | 978-1-6654-3595-6/20/$31.00 ©2021 IEEE | DOI: 10.1109/DDECS52668.2021.9417027
FPGA Resources
Christoph Niemann, Michael Rethfeldt, Dirk Timmermann
Institute of Applied Microelectronics and Computer Engineering
University of Rostock, Germany
Email: christoph.niemann@uni-rostock.de
Abstract—Approximate or inexact arithmetic is a promising
approach towards lower power consumption for applications that
can tolerate a certain amount of imprecision. As human percep-
tion is limited in its precision, this applies to image and audio
processing. Beyond, other applications like neuronal networks or
AI processing can benefit from such arithmetic as well, as they are
inherently tolerant to a certain amount of inaccuracy. One of the
most critical components of arithmetic circuits regarding power,
delay, and area are multipliers. Various sophisticated approaches
towards approximate multipliers are already published for
ASICs. However, such ASIC approaches are under-performing in
conjunction with the specific Lookup-Table (LUT)-based design
of FPGAs. As FPGAs gain in importance for applications like
signal processing, there is a substantial lack of approximate
design methodology for FPGAs. We propose an approach towards
approximate signal processing that is specifically tailored towards
the LUT-based hardware of FPGAs. It allows for significant
performance improvements while lowering the energy demands.
While introducing an insignificant average relative error of just
0.14%, we achieve a 45.9% area reduction in terms of LUTs while
decreasing the delay by 30.6% compared to the Xilinx Vivado
multiplier IP core. Our proposed design is open source and
available at https://github.com/niemann-c/approx-mult-for-fpga.
I. I NTRODUCTION
Approximate computing is of growing interest in today’s
arithmetic systems. One approach towards approximate com-
puting is the design of approximate compressors. Usually, they
are designed to save a number of transistors and/or logic gates
compared to an exact compressor. FPGAs becoming more and
more popular for arithmetic processing, particularly in the
fields of interest for approximate computing. Therefore, the
application of the approximate computing paradigm towards
FPGAs is important for FPGA designs as it promises substan-
tial performance benefits. However, only very few approaches
have been proposed so far. FPGAs are built of programmable
logic blocks (PLBs). Those PLBs are typically implemented
as static random-access memory (SRAM) based lookup tables
(LUTs). An n-input LUT can implement arbitrary n-input
Boolean functions. Nowadays, six-input LUTs are the standard
logic resource. In this work we use a Xilinx Virtex-7 FPGA
as reference. As most state-of-the-art FPGAs, its six-input
LUTs can alternatively be configured as two five-input LUTs.
However, this is only possible if both five-input LUTs share
the same inputs [1]. Our contributions are:
• We discuss the required properties of approximate 4:2
compressors to fit the specific hardware characteristics
of FPGAs.
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• We propose a partial product generation considering
the specific hardware properties of FPGAs and derive
novel building blocks for partial product generation.
• We present multiplier designs based on these compres-
sors and the improved partial product generation that
save energy while increasing the throughput.
• We realize approximate image processing cores based
on different approximation approaches. Thereby, we
are able to compare how well these approaches per-
form in a realistic application scenario.
The remainder of this paper is organized as follows: In Sec-
tion II we discuss requirements and objectives for the design
of approximate circuits. These criteria are applied to evaluate
related approaches in Section III. We introduce an approach
towards approximate compressors in Section IV. In Section V
we discuss the composition of optimized multipliers and
propose a partial product generation tailored towards FPGA
hardware resources. We evaluate our approach in Section VI
and show one possible application in Section VII. Section VIII
concludes this paper.
II. R EQUIREMENTS AND F IGURES OF M ERIT FOR
A PPROXIMATE C OMPUTING A PPROACHES
Approximate computing is a promising approach to reduce
power and resource demands of computations. However, it can
only be applied for applications that are able to tolerate a
certain amount of inaccuracy. The most prominent reason for
this ”allowed tolerance” is the human perception. The use of
this property for lossy data compression methods such as MP3
or JPEG is widely known. Approximate computing applies
the same principle to digital signal processing. Metrics to
evaluate approximate computing approaches should therefore
consider the characteristics of human perception, the so-called
psychophysics. One important characteristic is that the amount
of inaccuracy tolerated by human perception is not an absolute
value, but relative to the signal amplitudes. This is reflected
by Weber’s law [2]:
∆S
k= (1)
S
It states that the just noticeable difference ∆S of a stimulus
S is proportional to the stimulus itself. Applied to metrics for
approximate computing, this means that the error introduced
should be set in relation to the actual (correct) signal value.
However, many proposed and frequently used metrics for
approximate computing are neglecting this principle. Examples
are the Mean Absolute Error (MAE), also called Mean Error
 Distance (MED), and the Normalized Mean Error Distance
(NMED) (both discussed in [3]). The MAE is defined straight
forward:
X |O(i) (i)
correct − Oapprox |
M AE = (2)
2n
∀i
(i)
with the correct output Ocorrect and the actual output Oapprox
of the approximate circuit for the i-th input pattern, respec-
tively. Whereas, the NMED sets the error in relation to the
maximum possible signal value to compensate for the effects
of differing bit widths. Hence, when comparing designs with
the same bit-width, both metrics are equivalent. Therefore, we
will solely use the NMED in the remainder of this paper.
M AE
N M ED =
max(Ocorrect )
Obviously, the NMED behaves just like the Peak Signal to
Noise Ratio (PSNR) whereas metrics related to the actual
Signal to Noise Ratio (SNR) would be more adequate. That
holds true not only for the human perception but also for
many technical applications, as the wide use of the metric
SNR reflects. However, the SNR holds the problem that it is
highly dependent on the signal processed. Because of that, we
choose other metrics closely related to the metrics used by [4].
Therefore, we divide the introduced error by the correct output
value instead of the maximum one. Obviously, this metric gets
infinite for a correct output value of zero. This somehow makes
sense, as for example in acoustics, an error in a surrounding
of absolute silence would be extremely disturbing. However,
to have a usable metric we normalize errors that occur at
the correct output of zero with the smallest possible non-zero
output value, i.e., one for non-fractional number systems. We
call this metric the Relative Error (RE).
(i) (i)
|Ocorrect − Oapprox |
REi = (i)
max(1, Ocorrect )
Two important metrics can be derived from the relative
error: the mean relative error (MRE) and the worst-case relative
error (WCRE).
P
REi
M RE = ∀i n (5)
2
defines the mean relative error with n being the number of
input bits. The worst-case relative error is defined as
W CRE = max(REi )
∀i
As discussed, these metrics reflect the characteristic of
the error tolerance better than, e.g., an absolute error. The
fact that the relative error is more relevant than the absolute
error value is not only important for proper evaluation of
approximate circuits. Rather, it is the major motivation for
the design decisions and is the basis for our novel approach
towards approximate arithmetic structures on FPGAs.
III. R ELATED W ORK
Mody et al. propose an approximate compressor for mul-
tipliers on FPGAs [5]. They propose to neglect the internal
carry paths within 4:2 compressors, which we find an inspiring
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4:2 Compressor critical path
an+1 bn+1 cn+1 dn+1 an bn cn dn an-1 bn-1 cn-1 dn-1
Full Adder Full Adder Full Adder
(i) Internal carry
Full Adder Full Adder Full Adder
out h,n+1 Out l,n+1 out h,n out l,n out h,n-1 out l,n-1
Fig. 1. Critical path in a 4:2 compressor.
(3)
idea. However, they aim to reduce logic gates which does not
yield optimal results for LUT based FPGAs. Therefore, their
design shows inexact outputs in 4 of 16 input vectors, which
is sub-optimal, as we discuss in Section IV. As the authors
do not specify any metric that evaluates the quality of their
approximation, we re-implemented their solutions exactly as
described in the publication. The approximation causes huge
errors that reflect in an NMED of about 44%.
In [6], the authors propose an approximate multiplier based
on approximate adders. Their key innovation is to extract the
sign and than round to the nearest number in the form 2n
to execute a multiplication as simple shift. Precise resource
savings in terms of LUTs are not specified. However, the
worst-case relative error for an 8 bit multiplier is stated to be
more than 8%. The authors of [7] compose multipliers from
a variety of approximate compressors. Their area savings are
most impressive. However, they introduce a mean relative error
(4) that is at least one order of magnitude higher than our solution.
In [8], the authors propose different 8x8 bit multipliers recur-
sively constructed from 4x4 bit multipliers. The mean relative
error of their most precise multiplier proposed is in the same
order of magnitude but slightly worse than our approach.
In [4], the authors propose a very interesting approach
towards the automated generation of approximate multiplier
designs by means of multi-objective Cartesian genetic pro-
gramming. The impressive results are published as a library of
approximate multipliers, too. As this approach targets ASIC
(6) technologies, they are outperformed by designated FPGA
approaches, as shown in [9]. In [10], the authors argue that
a choice of suitable designs from this library is indeed com-
petitive on FPGAs. They propose a machine learning (ML)
supported methodology to pick suitable implementations for
FPGAs from huge libraries of approximate designs. Ullah et
al. propose small (4x2) approximate multipliers [9]. Based on
these they compose bigger multipliers in two different ways,
introducing further approximation. We found this approach the
most technically sound. It provides very good results in terms
of quality of the approximation and saved resources. Therefore,
we use it as baseline to compare our approach to.
We provide a quantitative comparison of related approaches
with this work in Section VI.
24
 TABLE I. T RUTH TABLE FOR APPROXIMATE 4:2 COMPRESSOR .
IV. A PPROXIMATE C OMPRESSORS
a b c d outh outl Relative
Approximate computing aims to reduce the demand for Error
resources by reducing the complexity of the circuitry, allowing 0 0 0 0 0 0 0%
0 0 0 1 0 1 0%
some amount of error. Typically, that is reducing the amount 0 0 1 0 0 1 0%
of logic gates within a structure. However, as FPGAs do not 0 0 1 1 1 0 0%
0 1 0 0 0 1 0%
map the logic to gates, but to SRAM based LUTs, a different 0 1 0 1 1 0 0%
approach is necessary to fit FPGA properties in an optimal 0 1 1 0 1 0 0%
manner. As LUTs can represent arbitrary logical functions, 0 1 1 1 1 1 0%
1 0 0 0 0 1 0%
the specific logical function of any LUT has no influence on 1 0 0 1 1 0 0%
the demanded resources. Any FPGA specific approach towards 1 0 1 0 1 0 0%
approximate computing needs to consider this fact. 1 0 1 1 1 1 0%
1 1 0 0 1 0 0%
1 1 0 1 1 1 0%
One of the most frequently used basic building blocks for 1 1 1 0 1 1 0%
arithmetic structures are compressors. As a basic element of 1 1 1 1 1 1 25%
the reduction tree, they are part of typical multiplier designs
such as Wallace or Dadda-Tree structures. In signal processing, Factor a
7 6 5 4 3 2 1 0
they can be used as accumulator-stage in multiply-accumulate
operations as well. Typically, designers use 3:2 or 4:2 compres- PPU_A 0

sors. The latter tend to result in a more regular structure of the 1

PPU_B
design which is beneficial for reducing routing congestions and
"AND" 2
delay. Therefore, we focus on 4:2 compressors.
3

In ASIC implementations, such 4:2 cells are typically
composed from two full adders. The carry path includes two
full adders, as shown in Fig. 1. In a five-input-LUT based
FPGA implementation, the carry path dominates the timing
behavior. Hence, an approximation that omits the carry may
yield significant advantages in terms of speed in FPGA based
designs. Therefore, it makes sense to omit the carry path as
proposed for 4:2 compressors by [11] and for various other
basic adder blocks by [12]. However, we adopted the logical
mapping proposed by [11] for ASICs for our FPGA design,
as it produces less errors and maps nicely to LUTs.
The four inputs of a 4:2 compressor are all equal and
represent a value of one. Hence, the four equal inputs can
represent numbers from zero to four. As we want to omit the
carry path, we need to perform an approximate compression of
4 inputs to two outputs. With just two output bits remaining,
it is only possible to represent numbers with a numerical
value of zero to three using a standard unsigned number
representation. Therefore, the scenarios of all inputs being
one cannot be mapped correctly to outputs without a carry.
Whereas, we are able to assign the correct output to all other
inputs due to the freely configurable LUTs. Therefore, an
error is solely introduced in one of the sixteen possible input
configurations [11]. Furthermore, this error is introduced in the
case producing the highest correct output value. Therefore, the
relative error is rather small as compared to the relative errors
of other approaches (e.g., [5]). Table I represents the truth table
of the approximate 4:2 compressor.
V. A PPROXIMATE M ULTIPLIERS
A. Multiplier implementations
Many approaches towards approximate multiplications aim
at optimized compressors or small basic multiplication cells
(e.g., [5], [9]). However, the actual multiplier implementation
(i.e., the way of composing a multiplier from these basic cells)
has an enormous impact on the results. This holds true for
resource savings, as well as for the amount of inaccuracy
caused by the approximate basic elements. This fact compli-
cates the comparison of different approximate multiplication
Factor b
4
5
6
7
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig. 2. Proposed arrangement of PPUs.
results as it is not trivial to distinguish between benefits of
the approximation and those of the chosen implementation
of the multiplier. Therefore, we implemented some interesting
approaches from literature to achieve a realistic quantification
of advantages and disadvantages of each approach.
B. Optimized partial product generation for FPGAs
The straightforward way of generating the necessary partial
products for a multiplication is
P Pi,j = Ai ∧ Bj (7)
This can be mapped to ASICs very efficiently in the form
of an AND gate. Contrarily, applying this approach to FPGAs
leads to inefficient utilization of resources. Just two AND gates
can be mapped two a single LUT when reconfigured into two
independent two-input LUTs. However, a LUT can represent
arbitrary (complex) logical functions. In our approach, we take
advantage of this fact to save resources.
We propose a combination of creating partial products
with some amount of compression, both joined together and
mapped efficiently to LUT based logic. Such a partial product
unit (PPU) needs to generate multiple partial products and
compress them. The partial product bits generated by one PPU
can depend on a maximum of six input bits, as this is the
number of input pins of a LUT. However, in this case the LUT
can generate only a single output bit. We found it beneficial to
configure LUTs into two five-input LUTs with shared inputs.
Therefore, a PPU should generate a maximum number of
partial product bits out of five input bits. Furthermore, it should

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 TABLE II. R EQUIRED RESOURCES FOR PARTIAL PRODUCT GENERATION (8 BIT ).
Number of AND LUTs for AND gates PPUs LUTs for PPUs Overall LUTs Number of partial
gates product bits
’Conventional’ approach 64 32 0 0 32 64
Proposed PPU approach 4 2 12 24 26 52

TABLE III. O UTPUT BITS OF PPU A COMPARED WITH

’ CONVENTIONAL’ PARTIAL PRODUCT GENERATION FOR THE SAME INPUT TABLE V. PPU A O UTPUT TABLE VI. PPU B O UTPUT
PROBABILITY. PROBABILITY.
BITS .

Numeric value Number of Number of PPU A Output bit Oi P (Oi = 1) Output bit Oi P (Oi = 1)
’conventional’ partial output bits 0 25% 0 37.5%
product bits 1 37.5% 1 37.5%
2 37.5% 2 21.875%
20 1 1
3 9.375% 3 6.25%
21 2 1
22 2 1
23 0 1
Numeric range [0,13] [0,15] PPUs, the asymptotic delay is O(1), which makes our approach
perfectly suitable for the construction of bigger multipliers.
TABLE IV. O UTPUT BITS OF PPU B COMPARED WITH Furthermore, Fig. 2 depicts that we need to create some partial
’ CONVENTIONAL’ PARTIAL PRODUCT GENERATION FOR THE SAME INPUT
BITS .
product bits individually, i.e., outside the PPUs depending on
the specific bit-width of the multiplier. These individual partial
Numeric value Number of Number of PPU B
’conventional’ partial output bits
product bits are generated by feeding both input bits into a
product bits LUT configured as an AND gate. The small overhead added
20 2 1 this way is almost negligible. For example, in our 8-bit case it
21 2 1 adds two additional LUTs, each configured as two individual
22 1 1
23 0 1 two-input AND gates. As shown in Table II, our approach
Numeric range [0,10] [0,15] saves 19% of the resources as compared to a traditional AND-
gate approach. It is not only saving resources during the
partial product creation itself, but due to the integrated partial
need a minimum (optimally even) number of output bits to compression it also demands only 81% of the partial product
represent the pre-compressed partial product. bits of the traditional AND-gate approach. Therefore, it allows
for further resource savings in the compressor tree following
We found that a combination of two different types of PPUs the partial product generation.
is optimal regarding these requirements. We call them PPU
type A and B. Fig. 2 depicts this combination of different C. Statistical optimization of the compression tree
PPUs. In our design, each PPU has five inputs. For example,
the highlighted PPU A has the inputs a0 , a1 , b0 , b1 , and b2 . As described in Section IV, our approximate compressor
The highlighted PPU B has the inputs a0 , a1 , b2 , b3 , and works accurately in 15 out of 16 cases. As only the case
b4 . With ai and bi being the ith bit of the respective input with all inputs being ’one’ introduces an error it should be
factors a and b for the multiplication. Each PPU derives five avoided if possible. In other words, the probability of that case
’conventional’ partial product bits from these inputs. These in- should be minimized. As shown in Fig. 3 there is some degree
ternal ’conventional’ partial product bits have different numeric of freedom in the choice which PPU outputs should be fed
values with some of them appearing multiple times. Hence, into which compressor. The PPU output signals have different
they form a redundant number representation. The numeric probabilities for having the value ’one’. Hence, the assignment
value of this internal redundant partial product is compressed of PPU outputs to the compressors should be made in a way
to a four bit non-redundant number at the output of the PPU. that minimizes the probability of all inputs of a compressor
The specific configuration of each type of PPU concerning being ’one’. The precise PPU output probability depends on
this matter is documented in Tables III and IV. Note that the the multiplier inputs, too. However, the statistics concerning
internal ’conventional’ partial products do not exist as real this cannot be determined without domain knowledge and
signals within the FPGA. In fact, they are just a theoretical exponential simulation times. Therefore, we determined the
concept to design and understand the logical function mapped output probabilities of the PPUs with a behavioral simulation
to the LUTs. We decided to use just five internal ’conventional’ assuming uniformly distributed PPU inputs. Results are shown
partial products in each PPU even though it would be possible in Tables V and VI. Based on this data, we assigned the
to derive six of them from the five input bits. However, the PPU outputs to the compressor inputs in such a way, that
representation of their numeric range would demand more the probability of all inputs being ’one’ is minimized for the
PPU output bits resulting in a worse compression and higher approximate compressors. With this method we achieved a
resource consumption in terms of LUTs. significant improvement of the quality of the results of our
approximate multiplier.
One of the most important characteristics of an approach
towards optimized partial product generation is its asymptotic VI. A NALYSIS AND R ESULTS
behavior with respect to delay, as it determines its suitability
for longer bit-width multipliers. The different PPUs are ar- To evaluate our approach we compared it to the state
ranged in a regular structure. Therefore, bigger multipliers can of the art. As image processing is one of the most im-
be constructed by just extending the pattern shown in Fig. 2. portant applications of approximate computing, we chose a
As there is no data-path interconnection between the individual bit width of 8 bit, typically used in such applications, for

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 PPU_A output bits 100
[7] I 1-II 4
PPU_B output bits
[9] Cc, Ca
"AND" output bit
[8] T1-T8
Compressor assignment
[13]
10−1

Mean relative error

[14]
[3]
[15]
[10]
10−2 This work

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit index

Fig. 3. Choice of PPU outputs for compression. 10−3

our comparison. To achieve a meaningful comparison of the

quality of the approximation, we determined the metrics of
each approach with an exhaustive simulation of all possible 0 20 40 60 80 100
input patterns. For that purpose, we used the open source Number of LUTs
data of [9] and [10] and re-implemented the designs T1-T8
from [8] as described in the paper. For comparable results Fig. 4. Comparison of this work with state-of-the-art regarding logic
regarding ressource utilization and delay we synthesized all resources. Data for [3], [7], [13]–[15] taken from [7].
desings of these three publications on our tool chain. For other
referenced desings we used data from the literature, as there
is no open source implementation available. Results are listed [7] I 1-II 4
in Table VII. Obviously, there are approaches that save more [9] Cc, Ca
resources. However, the delivered quality of the approximation [8] T1-T8
varies in a range of multiple orders of magnitude. When [13]
10−1
Mean relative error

compared to state of the art approaches that allow for a
similar saving in terms of resources, our approach delivers
the best results in terms of the mean relative error. Therefore,
our design seems to be most suitable for applications that
have a limited tolerance regarding the introduced error. Fig. 4
depicts the Pareto comparison regarding this metric. Note,
that this comparison also includes designs that are not meant
to be used on FPGAs, but for ASICs. Besides averaging
metrics, the worst-case behavior of an approximate circuit
is of great interest as well. Unfortunately, some authors do
not specify it in their publications. Compared to the known
data, our approach outperforms the state of the art by a factor
of two. In terms of hardware characteristics the delay is of
huge importance, too. Fig. 5 illustrates that our design is
outperforming the state of the art in this regard.
Our approach is perfectly suitable for the construction of
multipliers with larger bit widths. As discussed in Section V-B,
our partial product generation has a constant asymptotic delay,
while the compression tree scales with O(log(n)). Therefore,
larger designs exhibit low latencies as well. For example, a
16x16 bit multiplier design following our approach has a delay
of just 3.249 ns and consumes 220 LUTs on a Virtex-7 FPGA.
While, e.g., the 16 bit extension of [9] (design Ca) consumes
245 LUTs and causes a delay of 4.547 ns when synthesized on
the same tool chain for the same target platform. However,
a comprehensive discussion and comparison of 16 bit designs
is out of scope due to limited space and is planned as future
work.
VII. APPLICATION E XAMPLE : A PPROXIMATE I MAGE
P ROCESSING C ORE
To illustrate the usability of our approximate multipliers
and compressors, we implemented a convolutional image
[14]
[3]
[15]
[10]
10−2 This work
10−3
0 2 4 6 8
Delay [ns]
Fig. 5. Comparison of this work with state-of-the-art regarding its delay.
Data for [3], [7], [13]–[15] taken from [7].
processing core, as it is used for edge detection, blurring,
and many other image processing tasks. More specifically,
we chose a filter kernel that processes a 3x3 pixel window
per clock cycle. However, results scale to bigger kernels very
well. We applied different approximate computing approaches
to the multipliers and compressors within the core, to compare
their impact on image quality, required logic resources, and
delay. As baseline, we chose a Wallace tree multiplier utilizing
exact 4:2 compressors and a carry save (CS) compression tree
for the accumulation. The results shown in Table VIII prove
that our approach does not only work in theory but also in
real applications. Note the tremendous resource savings of
about 40% as well as a 16% speedup when our approximate
compressors are applied not only to the multipliers but in
the accumulate stages of the filter kernel, too. Fig. 6 shows

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 TABLE VII. C OMPARISON WITH STATE - OF - THE - ART - 8- BIT MULTIPLIERS . R ESULTS ARE DETERMINED BY EXHAUSTIVE SIMULATION OF ALL
POSSIBLE INPUT VECTORS OR FROM LITERATURE .

Reference Approach Area [LUTs] delay [ns] MRE WCRE NMED [102 ]
Xilinx Coregen exact multiplier 98 3.447 — — —
Ullah [9] Design Ca elementary multiplier blocks 57 3.167 0.0029 0.1905 0.080
Ullah [9] Design Cc elementary multiplier blocks 56 2.372 0.1294 0.9675 2.430
[7] AM II 4 1 approximate compressors 48 4.330 0.0140 N/A 0.190
[7] AM I 4 1 approximate compressors 55 4.440 0.0117 N/A 0.160
[8] T1 elementary multiplier blocks 57 3.132 0.0017 0.1633 0.055
[10] mul8u 158B ML supported choice from ASIC-Library 73 3.967 0.0036 0.4000 0.023
[10] mul8u 18G6 ML supported choice from ASIC-Library 23 2.732 0.1191 3.0000 0.665
This Work LUT-optimized compressors 53 2.391 0.0014 0.0816 0.068
1
Data for Spartan-6 FPGA

TABLE VIII. R ESULTS FOR APPLICATION OF DIFFERENT APPROXIMATE TECHNIQUES TO A 3X3 CONVOLUTIONAL FILTER KERNEL .

Approach Number of LUTs Relative savings Delay [ns] Relative speedup

Wallace Tree multipliers, CS compression tree 872 — 6.046 —
Ullah [9] Design Cc 630 27.75% 6.634 -9.73%
Our approach, CS compression tree with exact 4:2 compressors 636 27.06% 5.788 4.27%
Our approach, CS compression tree with approximate 4:2 compressors 520 40.37% 5.082 15.94%

[2] M. Spering and T. Schmidt, Allgemeine Psychologie kompakt :

Fig. 6. Resulting images: exact multiplier, this approach, Ullah et al. [9]
Design Cc (from left to right).
results of a Gaussian smoothing filter. The multipliers within
the filter kernel are an exact multiplier and our approach.
For comparison we also determined results for multiplier
Design Cc [9], when used in our filter kernel.
VIII. C ONCLUSION
We propose a new approximate compressor design for
efficient arithmetic in error tolerant applications on modern
FPGAs. Furthermore, we discuss the optimal composition of
a multiplier from this compressor design. Our novel approach
is specifically tailored towards the characteristics of human
perception and the resources of modern FPGAs. Thereby,
we achieve a significant improvement in terms of quality
of the approximation while being highly resource efficient.
We are able to save 46% of the FPGA resources while
introducing a mean relative error of just 0.14%. Addition-
ally, our approach decreases the delay by 31% compared
to the Xilinx Coregen multiplier IP core. To fuel further
research, our proposed design is open source and available
at https://github.com/niemann-c/approx-mult-for-fpga.
IX. ACKNOWLEDGEMENT
We want to thank Hooma Amjad for her practical support.
This research was funded by the Deutsche Forschungsgemein-
schaft (DFG, German Research Foundation) SFB 1270/1 -
299150580.
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