Ecad Vlsi Manual

IV BTech I Semester ECAD & VLSI Lab ECE Department
PROGRAM- 1
Aim: Write a VHDL code for all Logic gates.
Software: Xilinx ISE 9.2i, ISE Simulator(VHDL/Verilog).
PROGRAM-1(A):
VHDL Code for AND gate:
Block Diagram:
Logic Diagram:
1
SPHOORTHY ENGINEERING COLLEGE
Truth Table:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity program1a is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end program1a;
architecture Behavioral of program1a is
begin
C<=A and B;
end Behavioral;
2
Waveform:
PROGRAM-1(B):
VHDL Code for OR gate:
Block Diagram:
Logic Diagram:
3
Truth Table:
library IEEE;
entity program1b is
B : in STD_LOGIC;
C : out STD_LOGIC);
end program1b;
architecture Behavioral of program1b is
begin
C<=A or B;
end Behavioral;
4
Waveform:
PROGRAM-1(C):
VHDL Code for NOT gate:
Block Diagram:
Logic Diagram:
5
TruthTable:
library IEEE;
entity program1c is
C : out STD_LOGIC);
end program1c;
architecture Behavioral of program1c is
begin
C<= not A;
end Behavioral;
6
Waveform:
PROGRAM-1(D):
VHDL Code for NOR gate:
Block Diagram:
Logic Diagram:
7
Truth Table:
library IEEE;
entity program1d is
B : in STD_LOGIC;
C : out STD_LOGIC);
end program1d;
architecture Behavioral of program1d is
begin
C<=A nor B;
end Behavioral;
8
Waveform:
PROGRAM-1(E):
VHDL Code for NAND gate:
Block Diagram:
Logic Diagram:
9
Truth Table:
library IEEE;
entity program1e is
B : in STD_LOGIC;
C : out STD_LOGIC);
end program1e;
architecture Behavioral of program1e is
begin
C<=A nand B;
end Behavioral;
10
Waveform:
PROGRAM-1(F):
VHDL Code for XOR gate:
Block Diagram:
Logic Diagram:
11
Truth Table:
library IEEE;
entity program1f is
B : in STD_LOGIC;
C : out STD_LOGIC);
end program1f;
architecture Behavioral of program1f is
begin
C<=A xor B;
end Behavioral;
12
Waveform:
PROGRAM-1(G):
VHDL Code for XNOR gate:
Block Diagram:
Logic Diagram:
13
Truth Table:
library IEEE;
entity program1g is
B : in STD_LOGIC;
C : out STD_LOGIC);
end program1g;
architecture Behavioral of program1g is
begin
C<=A xnor B;
end Behavioral;
14
Waveform:
Result: The Logic Gates Design have been realized and Simulated using VHDL Code.
15
PROGRAM- 2
Aim: Write a VHDL code for 2 to 4 Decoder.
PROGRAM:
VHDL Code for 2 to 4 Decoder:
Block Diagram:
16
Logic Diagram:
Truth Table:
library IEEE;
entity program2 is
Port ( I : in STD_LOGIC_VECTOR (1 downto 0);
en : in STD_LOGIC;
17
Z : out STD_LOGIC_VECTOR (3 downto 0));

end program2;
architecture Behavioral of program2 is
begin
process(I,en)
begin
case I is
when "00"=>Z<="0001";
when "01"=>Z<="0010";
when "10"=>Z<="0100";
when "11"=>Z<="1000";
when others=>Z<="0000";
end case;
end process;
end Behavioral;
Waveform:
Result: The 2 to 4 Decoder Designs have been Realized and Simulated using VHDL Code.
18
PROGRAM- 3
Aim: Write a VHDL code for 8 to 3 Encoder.

PROGRAM:
VHDL Code for 8 to 3 Encoder:
Block Diagram:
Logic Diagram:
19
Truth Table:
library IEEE;
entity program3 is
Port ( S : in STD_LOGIC_VECTOR (7 downto 0);
D : out STD_LOGIC_VECTOR(2 downto 0));
end program3;
begin
process(S)
begin
case S is
when "00000001"=>D<="000";
when "00000010"=>D<="001";
when "00000100"=>D<="010";
when "00001000"=>D<="011";
when "00010000"=>D<="100";
20
when "00100000"=>D<="101";
when "01000000"=>D<="110";
when "10000000"=>D<="111";
when others=>D<="000";
end case;
end process;
end Behavioral;
Waveform:
Result: The 8 to 3 Encoder Designs have been Realized and Simulated using VHDL Code.
21
PROGRAM- 4
Aim: Write a VHDL code for 8 to 1 Multiplexer.

PROGRAM:
VHDL Code for 8 to 1 Multiplexer:
Block Diagram:
Logic Diagram:
Truth Table:
22
library IEEE;
entity program4 is
Port ( I : in STD_LOGIC_VECTOR (7 downto 0);
S : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC);
end program4;
begin
process(I,S)
begin
case S is
when "000"=>y<=I(0);
23
when "001"=>y<=I(1);
when "010"=>y<=I(2);
when "011"=>y<=I(3);
when "100"=>y<=I(4);
when "101"=>y<=I(5);
when "110"=>y<=I(6);
when "111"=>y<=I(7);
when others=>null;
end case;
end process;
end Behavioral;
Waveform:
Result: The 8 to 1 Multiplexer Designs have been Realized and Simulated using VHDL Code.
24
PROGRAM- 5
Aim: Write a VHDL code for 4-Bit Binary to Gray Code Converter.
PROGRAM:
VHDL Code for Binary to Gray code converter:
Block Diagram:
Logic Diagram:
Truth Table:
25
library IEEE;
Entity program5 is
Port(B: in std_logic_vector(3 downto 0);
G:out std_logic_vector(3 downto 0));
End binarytogray;
Architecture behavioral of program5 is
Begin
Process(B)
Begin
Case B is
When "0000" =>G<= "0000";
When "0001" =>G<= "0001";
26
When "0010" =>G<= "0011";
When "0011" =>G<= "0010";
When "0100" =>G<= "0110";
When "0101" =>G<= "0111";
When "0110" =>G<= "0101";
When "0111" =>G<= "0100";
When "1000" =>G<= "1100";
When "1001" =>G<= "1101";
When "1010" =>G<= "1111";
When "1011" =>G<= "1110";
When "1100" =>G<= "1010";
When "1101" =>G<= "1011";
When "1110" =>G<= "1001";
When "1111" =>G<= "1000";
When others =>G<= "0000";
End case;
End process;
End behavioral;
Waveform:
27
Result: The 4 Bit Binary to Gray Converter Designs have been Realized and Simulated using
VHDL Code.
PROGRAM- 6
28
Aim: Write a VHDL code for 1 to 4 Demultiplexer.

PROGRAM-6(A):
VHDL Code for 1 to 4 Demultiplexer:
Block Diagram:
Logic Diagram:
library IEEE;
29
entity program6a is
Port ( E : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end program6a;
begin
process(E,S)
begin
case S is
when "00"=>Y<="0001";
when "01"=>Y<="0010";
when "10"=>Y<="0100";
when "11"=>Y<="1000";
when others=>null;
end case;
end process;
end Behavioral;
Waveform:
30
Result: The 1 to 4 Demultiplexer Design have been Realized and Simulated using VHDL Code
PROGRAM-6(B):
VHDL Code for 4 bit comparator:
Block Diagram:
Logic Diagram:
31
library IEEE;
entity program6b is
port(a,b:in bit_vector(3 downto 0);
AeqB,AltB,AgtB:out bit);
end program6b;

begin
process(a,b)
begin
32
AeqB<='0';AltB<='0';AgtB<='0';
if a=b then AeqB<='1';
elsif a<b then AltB<='1';
elsif a>b then AgtB<='1';
end if;
end process;
end Behavioral;
Waveform:
Result: The 4 Bit Comparator Design have been Realized and Simulated using VHDL Code.
33
PROGRAM- 7
Aim: Write a VHDL code for Full Adder.
PROGRAM:
VHDL Code for Full Adder:
Block Diagram:
Logic Diagram:
34
Truth Table:
library IEEE;
entity program7 is
B : in STD_LOGIC;
C : in STD_LOGIC;
35
SUM : out STD_LOGIC;

CARRY : out STD_LOGIC);
end program7;

begin
SUM<=A xor B xor C;
CARRY<=(A and B) or (B and C) or (C and A);end Behavioral;
Waveform:
Result: The Full Adder Designs have been Realized and Simulated using VHDL Code.
PROGRAM- 8
36
Aim: Write a VHDL code for Flip flops.
PROGRAM-8(A):
VHDL Code for SR:
Block Diagram:
Logic Diagram:
Truth Table:
37
library IEEE;
entity program8a is
port(S,R,CLK: in std_logic;
Q,Q1,Z: inout std_logic);
end program8a;

begin
process(CLK)
begin
if CLK='1' then
Z<=S or ((not R) and Q);
Q<=Z after 5ns;
Q1<=not Z after 5ns;
end if;
end process;
end Behavioral;
38
Waveform:
Result: The SR-FlipFlop Design have been Realized and Simulated using VHDL Code.
PROGRAM-8(B):
VHDL Code for D Flip flop:
Block Diagram:
Logic Diagram:
39
Truth Table:
library IEEE;
entity program8b is
Port ( CLK : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end program8b;
40
begin
process(CLK)
begin
if(CLK' event and CLK='1')then
Q<=D;
end if;
end process;
end Behavioral;
Waveform:
Result: The D-FlipFlop Design have been Realized and Simulated using VHDL Code.
PROGRAM-8(C):
41
VHDL Code for JK Flip flop:
Block Diagram:
Logic Diagram:
Truth Table:
42
library IEEE;
entity program8c is
Port ( JK : in STD_LOGIC_VECTOR(1 downto 0);
CLK : in STD_LOGIC;
--RST : in STD_LOGIC;
Q : out STD_LOGIC;
Qb : out STD_LOGIC);
end program8c;
architecture Behavioral of program8c is
begin
process(CLK)
variable temp1,temp2:std_logic;
begin
if rising_edge(CLK)then
case JK is
43
when "01"=>temp1:='0';
when "10"=>temp1:='1';
when "00"=>temp1:=temp1;
when "11"=>temp1:=not temp1;
--when "00"=>temp1:=temp1;
--when "11"=>temp1:=not temp1;
when others=>null;
end case;
Q<=temp1;
temp2:=not temp1;
Qb<=temp2;
end if;
end process;
end Behavioral;
Waveform:
Result: The JK-FlipFlop Design have been Realized and Simulated using VHDL Code.
PROGRAM-8(D):
44
VHDL Code for T Flip flop:
Block Diagram:
Logic Diagram:
Truthtable:
45
T Qn+1
0 Qn
1 Qnbar
library IEEE;
entity program8d is
Port ( T : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC);
end program8d;
architecture Behavioral of program8d is
begin
process(CLK)
begin
if(CLK 'event and CLK='1')then
Q<=not T;
end if;
46
end process;
end Behavioral;
Waveform:
Result: The T-FlipFlop Design have been Realized and Simulated using VHDL Code.
47
PROGRAM- 9
Aim: Write a VHDL code for BCD Counter.
PROGRAM:
VHDL Code for BCD Counter:
Block Diagram:
library IEEE;
entity program9 is
port(
reset : in STD_LOGIC;

clk : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR(3 downto 0)
48
);
end program9;
begin
count : process (reset,clk) is
variable m : std_logic_vector (3 downto 0) := "0000";
begin
if (reset='1') then
m := "0000";
elsif (rising_edge (clk)) then
m := m + 1;
end if;
if (m="1010") then
m := "0000";
end if;
dout <= m;
end process count;
end Behavioral;
Waveform:
Result: The BCD Counter Design have been Realized and Simulated using VHDL Code.
PROGRAM- 10
49
Aim: Write a VHDL code for FSM.
PROGRAM:
VHDL Code for FSM:
library IEEE;
entity program10 is
port( clk : in std_logic; --clock signal
reset : in std_logic; --reset signal
S_in : in std_logic; --serial bit Input sequence
S_out : out std_logic); -- Output
end program10;
--Defines the type for states in the state machine
type state_type is (S0,S1,S2,S3,S4);
--Declare the signal with the corresponding state type.
signal Current_State, Next_State : state_type;
begin
-- Synchronous Process
process(clk)
begin
if( reset = '1' ) then --Synchronous Reset
Current_State <= 'S0';
50
elsif (clk'event and clk = '1') then --Rising edge of Clock

Current_State <= Next_State
end if;
end process;
-- Combinational Process
Process(Current_State, S_in)
begin
case Current_State is
when S0 =>
S_out <= '0';
if ( s_in = '0' ) then
Next_State <= S0;
else
Next_State <= S1;
end if;
when S1 =>
S_out <= '0';
if ( S_in = '0' ) then
Next_State <= S3;
else
Next_State <= S2;
end if;
when S2 =>
S_out <= '0';
Next_State <= S0;
else
51
Next_State <= S3;

end if;
when S3 =>
S_out <= '0';
if (S_in = '0' ) then
Next_State <= S2;
else
Next_State <= S4;
end if;
when S4 =>
S_out <= '1';
Next_State <= S2;
else
Next_State <= S1;
end if;
--when others=>null;
end if;
end case;
--end process;
end Behavioral;
Result: The FSM Design have been Realized and Simulated using VHDL Code.
52
PART-B
PROGRAM- 1
53
Aim: To simulate the Logic gates and observe its input and output waveforms.
Software: Microwind 3.1
PROGRAM-1(A):
Layout for AND gate:
Waveform:
54
PROGRAM-1(B):
55
Layout for OR gate:
Waveform:
56
PROGRAM-1(C):
57
Layout for NOR gate:
Waveform:
58
PROGRAM-1(D):
59
Layout for NAND gate:
Waveform:
60
PROGRAM-1(E):
Layout for XOR gate:
61
Waveform:
62
Result: The response of logic gates is observed for the given input waveform.
PROGRAM-2
63
Aim: To simulate the CMOS Nand gate & CMOS Inverter and observe its input and output
waveforms.
PROGRAM-2(A):
Layout for CMOS NAND gate:
Waveform:
64
PROGRAM-2(B):
Layout for CMOS INVERTER gate:
65
Waveform:
66
Result: The response of CMOS Nand gate & Inverter is observed for the given input waveform.
PROGRAM-3
Aim: To simulate the CMOS and observe its input and output waveforms.
67
PROGRAM:
Layout for CMOS:
Waveform:
68
Result: The response of CMOS is observed for the given input waveform.
PROGRAM-4
Aim: To simulate the Analog Inverter and observe its input and output waveforms.
69
PROGRAM:
Layout for Analog Inverter:
Waveform:
70
Result: The response of Analog Inverter is observed for the given input waveform.
PROGRAM-5
Aim: To simulate the PLL and observe its input and output waveforms.
71
PROGRAM:
Layout for PLL:
Waveform:
72
Result: The response of PLL is observed for the given input waveform.
73
PART-C
PROGRAM- 1
74
NMOS CHARACTARISTICS
Aim: To perform layout extraction, parasitic values estimation, schematic and design rule
checking of NMOS.
Software: Microwind 3.1, LT SPICE
Schematic Diagram:
Netlist:
A) Keeping Vds 5v constant vary the Vgs from 0 to 5v for nmos and plot Id vs. Vgs.
Model nmos level=1
M1 N-2N-3 GND N-1NMOS L=2 W=22,AD=66P,PD=24, AS=66P PS=24
Vbb N-1 gnd 0
Vds N-2 gnd 5
Vgs N-3 gnd 5
dc vgs 0 5 0.5
.print dc I(m1)
.End
75
B) Keeping Vgg 5v constant vary the Vds from 0 to 5v for nmos and plot Id vs. Vds.
Model nmos nmos level=1
M1 N-2N-3 GND N-1NMOS L=2 W=22,AD=66P,PD=24, AS=66P PS=24
Vbb N-1 gnd 0
Vds N-2 gnd 5
Vgs N-3 gnd 5
dc vds 0 5 0.5
Vgs 0 5 0.5
.print dc i(m1)
.End
C) Keeping Vgs and V ds constant and vary Vbb from –5 to 0v for NMOS and plot Ids Vs Vdd
curve
Model nmos nmos level=1
M1 N-2N-3 Gnd N-1NMOS L=2 W=22,AD=66P,PD=24, AS=66P PS=24
Vbb N-1 gnd 0
Vds N-2 gnd 5
Vgs N-3 gnd 5
dc vbb –100 0.01
Vgs 0 5 0.5
.print dc i(m1)
.End
Output Waveform:
76
Result: The schematic, layout extraction, parasitic values estimation, design rule checking and
wave forms of NMOS Charactaristics are observed.
PROGRAM-2
CMOS CHARACTARISTICS
77
checking of CMOS (NOT GATE, NAND GATE, NOR GATE).
Software: Microwind 3.1, Lt Spice
PROGRAM-2(A):
Schematic Diagram:
Netlist:
* C:\Program Files\LTC\LTspiceIV\examples\krish\Draft6.asc
M1 Z A 0 0 NMOS
M2 Z A 1 1 PMOS
V1 A 0 5v
V2 1 0 5v
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Program Files\LTC\LTspiceIV\lib\cmp\standard.mos
.tran 0 2ms 1ms 1ms
.backanno
.end
Output Waveform:
78
PROGRAM-2(B):
Schematic for NAND Gate:
Netlist:
* C:\Program Files\LTC\LTspiceIV\examples\krish\NAND Gate.asc
M1 Z A 2 2 NMOS
M2 2 B 0 0 NMOS
79
M3 Z A 1 1 PMOS
M4 Z B 1 1 PMOS
V1 1 0 5v
V2 A 0 0v
V3 B 0 5v
.model NMOS NMOS
.model PMOS PMOS
.tran 0 2ms 1ms 1ms
.backanno
.end
Output Waveform:
NAND(a=b=5v=1)
A=0,b=1,or a=1,b=0,or a=b=0
80
PROGRAM-2(C):
Schematic for NOR GATE:
Netlist:
M1 P001 A N001 N001 PMOS
M2 Z B P001 P001 PMOS
M3 Z B 0 0 NMOS
81
M4 Z A 0 0 NMOS
V1 N001 0 5v
V2 A 0 0v
V3 B 0 5V
.model NMOS NMOS
.model PMOS PMOS
.tran 0 2ms 1ms 1ms
.backanno
.end
Output Waveform: ( A=B=0)
A=0,B=1 OR A=1,B=0 OR A=B=1
82
wave forms of CMOS CHARACTARISTICS are observed.
PROGRAM-3
DIFFERENTIAL AMPLIFIER
83
checking of DIFFERENTIAL AMPLIFIER.
Schematic Diagram:
Netlist:
M1 Vout1 5 3 3 NMOS
M2 Vout2 0 3 3 NMOS
V1 5 0 5v
R1 4 Vout1 49.9 tol=1 pwr=0.1
R2 4 Vout2 49.9 tol=1 pwr=0.1
V2 4 0 12v
I1 3 0 50A
.model NMOS NMOS
.model PMOS PMOS
.tran 0 2ms 1ms 1ms
84
.backanno
.end
Output Waveform:
wave forms of DIFFERENTIAL AMPLIFIER are observed.
PROGRAM-4
COMMON SOURCE AMPLIFIER
85
checking of common source amplifier.
Schematic Diagram:
Net list:
M1 2 3 4 4 NMOS
R1 5 input 1K tol=1 pwr=0.1
R2 0 3 1Meg tol=1 pwr=0.1
R3 2 1 3.32K tol=1 pwr=0.1
R4 0 4 2.21K tol=1 pwr=0.1
C1 4 0 4.7µ V=6.3 Irms=0 Rser=6 Lser=0 mfg="AVX" pn="TAJA475K006" type="Tantalum"
C2 output 2 1µ V=16 Irms=0 Rser=11 Lser=0 mfg="AVX" pn="TAJA105K016"

type="Tantalum"
C3 3 5 1µ V=16 Irms=0 Rser=11 Lser=0 mfg="AVX" pn="TAJA105K016" type="Tantalum"
V1 input 0 SINE(0m 1m 1k) AC 100mv
86
V2 1 0 12v
.model NMOS NMOS
.model PMOS PMOS
.tran 0 2ms 1ms 1ms
.backanno
Output Waveform:
wave forms of common source amplifier is observed.
PROGRAM-5
COMMON DRAIN AMPLIFIER
87
checking of common drain amplifier.
Schematic Diagram:
Net list:
M1 1 3 4 4 NMOS
V1 input 0 SINE(0 1m 1k) AC 100m
R1 4 0 2.21K tol=1 pwr=0.1
R2 3 0 1Meg tol=1 pwr=0.1
R3 2 input 1K tol=1 pwr=0.1
C1 3 2 1µ V=16 Irms=0 Rser=11 Lser=0 mfg="AVX" pn="TAJA105K016" type="Tantalum"
C2 output 4 1µ V=16 Irms=0 Rser=11 Lser=0 mfg="AVX" pn="TAJA105K016"

type="Tantalum"
V2 1 0 12v
.model NMOS NMOS
.model PMOS PMOS
88
.tran 0 2ms 1m 1m
.backanno
.end
Output Waveform:
89
wave forms of common drain amplifier is observed.
90

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IV BTech I Semester ECAD & VLSI Lab ECE Department

Aim: Write a VHDL code for all Logic gates.

Software: Xilinx ISE 9.2i, ISE Simulator(VHDL/Verilog).

VHDL Code for AND gate:

architecture Behavioral of program1a is

VHDL Code for OR gate:

architecture Behavioral of program1b is

VHDL Code for NOT gate:

architecture Behavioral of program1c is

VHDL Code for NOR gate:

architecture Behavioral of program1d is

VHDL Code for NAND gate:

architecture Behavioral of program1e is

VHDL Code for XOR gate:

architecture Behavioral of program1f is

VHDL Code for XNOR gate:

architecture Behavioral of program1g is

Aim: Write a VHDL code for 2 to 4 Decoder.

Software: Xilinx ISE 9.2i, ISE Simulator(VHDL/Verilog).

VHDL Code for 2 to 4 Decoder:

Z : out STD_LOGIC_VECTOR (3 downto 0));

Aim: Write a VHDL code for 8 to 3 Encoder.

Aim: Write a VHDL code for 8 to 1 Multiplexer.

Port ( I : in STD_LOGIC_VECTOR (7 downto 0);

S : in STD_LOGIC_VECTOR (2 downto 0);

architecture Behavioral of program4 is

Software: Xilinx ISE 9.2i, ISE Simulator(VHDL/Verilog).

VHDL Code for Binary to Gray code converter:

Port(B: in std_logic_vector(3 downto 0);

G:out std_logic_vector(3 downto 0));

Architecture behavioral of program5 is

When "0000" =>G<= "0000";

When "0001" =>G<= "0001";

When "0010" =>G<= "0011";

When "0011" =>G<= "0010";

When "0100" =>G<= "0110";

When "0101" =>G<= "0111";

When "0110" =>G<= "0101";

When "0111" =>G<= "0100";

When "1000" =>G<= "1100";

When "1001" =>G<= "1101";

When "1010" =>G<= "1111";

When "1011" =>G<= "1110";

When "1100" =>G<= "1010";

When "1101" =>G<= "1011";

When "1110" =>G<= "1001";

When "1111" =>G<= "1000";

When others =>G<= "0000";

Aim: Write a VHDL code for 1 to 4 Demultiplexer.

port(a,b:in bit_vector(3 downto 0);

architecture Behavioral of program6b is

if a=b then AeqB<='1';

elsif a<b then AltB<='1';

elsif a>b then AgtB<='1';

Aim: Write a VHDL code for Full Adder.

Software: Xilinx ISE 9.2i, ISE Simulator(VHDL/Verilog).

VHDL Code for Full Adder: