VHDL

By

Jayasanthi Ranjith - PhD Scholar

Anna University
Coimbatore

E-mail: mjayasanthi@yahoo.co.in,
 VLSI!!!
1. Digital VLSI Design
2. Analog VLSI Design
3. Mixed signal VLSI Design
WHY VLSI and HOW?
 STRUCTURAL DOMAIN
 BEHAVIOURAL DOMAIN
 PHYSICAL DOMAIN

DESIGN DOMAINS
 Structural Behavioral
domain
domain
high level of
abstraction

VHDL models
low level of
abstraction
Level of
abstraction

Physical domain
Domains of Description
Gajski’s Y-Chart
 Structural Functional/Behavioral

Algorithm
(behavioral)

Register-Transfer
Language

Boolean Equation

Differential Equation

Geometric/physical

Domains and Levels of Modeling

 Structural
Functional

Processor

Register-Transfer

Gate

Transistor

Geometric
Domains and Levels of Modeling
 Structural Functional

Polygons

Sticks

Standard Cells

Floor Plan

Geometric

Domains and Levels of Modeling

 Requirements

RTL Model Simulate

Synthesize

Gate-level
Model Simulate Test Bench

ASIC or FPGA Place & Route

Timing
Model Simulate

Basic Design Methodology

 U.S. Department of Defense initiated in 80’s
later transferred to the IEEE
 Initial objective was modeling only and thus
only a simulator was envisaged
 Subsequently tools for VHDL synthesis were
developed

VHDL History
 VHDL
 V-VHSIC-Very High Speed Integrated Circuit
HDL-Hardware Description Language

 VHDL is a programming language that allows

one to model and develop complex digital
systems in a dynamic environment.

 Allows you to designate in/out ports (bits) and

specify behavior of the system.

What is VHDL?
 Abstraction
 Modularity
 Concurrency
 Hierarchy

VHDL Benefits
 Abstraction is hiding of details
 Differentiate between essential and nonessential
information
 only the essential information is considered,
nonessential information is left out

Abstraction
LEVELS OF ABSTRACTION
 Modularity allows the partitioning of big
functional blocks into smaller units and to
group closely related parts in self-contained
sub blocks, so called modules.

 This way, a complex system can be divided into

manageable subsystems. The guidelines for
partitioning can differ from design to design.

Modularity
 process 1 process 2 process n

Concurrency
 C0

C1 C2 C3

C4 C5 C6 C7 S11

S12
S1 S3 S6 S7

S2 S4 S8

S9
S13
S10
S14

S5

Hierarchy allows the building of a design out

of modules which themselves may be built
out of (sub-)modules.

Hierarchy
 VHDL for
FPGA/ASIC
 In the first step, Boolean equations are
derived from the VHDL description, no matter,
whether an ASIC or a FPGA is the target
technology.
 This Boolean code has to be partitioned into
the configurable logic blocks (CLB) of the
FPGA. This is more difficult than the mapping
onto an ASIC library.
 Another big problem is the routing of the CLBs
as the available resources for interconnections
are the bottleneck of current FPGAs.

VHDL for FPGA

 VHDL is used mainly for the development of
Application Specific Integrated Cicuits (ASICs).
 Tools for the automatic transformation of
VHDL code into a gate-level netlist were
developed already
 Eg-Xilinx
 This transformation is called synthesis and is an
integral part of current design flows.

VHDL for ASIC

library ieee;
use ieee.std-logic-1164. all ;
 invoke the std-logic-1164 package from the ieee
library.
 The package and library allow us to add additional
types, operators, functions, etc. to VHDL.
 Standard: bit
 std-logic-1164:Multivalued logic/X’s and 3 state
buses
 All: all defns in package are to be used

Library and package

 Dataflow or RTL (Register Transfer
Language) Modeling
 Structural or gate level modeling
 Behavioral modeling

Modeling Styles
Entity name is
port(A1,A2: IN std_logic;
x,y: OUT std_logic);
End name;
Architecture arch of name is
Begin
-----
-----
end arch;

Program structure
Half adder
 Ituses statements that defines the
actual flow of data
Entity hadd is
port(A1,A2: IN std_logic;
Sum, Cout: OUT std_logic);
End hadd;
architecture HA_CONCURRENT of hadd is
begin
SUM <= A xor B after 8 ns;
CARRY <= A and B after 4 ns;
end HA_CONCURRENT;

Data flow Modeling Eg.

 It describes the algorithm performed by the
module
It contains
 process statements, each containing
◦ sequential statements, including
 signal assignment statements and
 wait statements

Behavioral Modeling
 Entity hadd is
port(A1,A2: IN std_logic;
Sum, Cout: OUT std_logic);
End hadd;
Architecture a of hadd is
Begin
process(A1,A2)
Begin
Sum <= A1 XOR A2;
Cout <= (A1 AND A2) ;
end process;
end a;

Behavioral Modeling Eg.

Structural architecture
◦ implements the module as a composition of
subsystems
(Signals) + (Component instances + Port maps)

contains
 signal declarations, for internal interconnections
the entity ports are also treated as signals
 component instances instances of previously
declared entity/architecture pairs
 port maps in component instances
 connect signals to component ports

Structural Modeling-Components
 architecture HA_STRUCTURE of HADD is
component XOR2
port (X, Y: in BIT; Z: out BIT);
end component;
component AND2
port (L, M: in BIT; N: out BIT);
end component;
begin
X1: XOR2 port map (A, B, SUM);
A1: AND2 port map (A, B, CARRY);
end HA_STRUCTURE;

Structural modeling of Half adder

 Mixed Behavior and Structure
 An architecture can contain both behavioral and
structural parts
◦ process statements and component instances
 collectively called concurrent statements
◦ processes can read and assign to signals
 Example: register-transfer-level (RTL) Model
◦ data path described structurally
◦ control section described behaviorally

Mixed modeling
 Procedural
(textual order => execution
order)
 Sequential statements
 Control constructs alter
normal sequential flow
Called Behavioral
description in VHDL
Behavioral
 Non-procedural
(textual order NOT =>
execution order)
 Concurrent statements
 Data flow (or rather data
dependency restricts
concurrency)
Called Data flow
description in VHDL
Vs Dataflow
 VHDL is an Object Oriented Programming
(OOP) Language. Objects can have values,
attributes and methods. We will primarily use
the following VHDL data objects:

Signals
Constants
Variables

VHDL Data Objects

 There is an implied or explicit delay between the
signal assignment and when the signal is
updated.
 To represent nets (i.e. wires) in our circuits.
 They can be implemented in hardware.
 Signals are defined in port statements and
architecture declaration blocks.

Signals
 Variables are data objects in which the value of
the object can be changed. This change occurs
instantaneously.

 Variables can only be defined within a process

declaration block.

 They cannot be implemented in hardware.

Variables
 Constants are data objects in which the value of
the object cannot be changed.

 They are defined within an architecture or

process declaration block.

 They cannot be implemented in hardware.

Constants
Data types
 The six logical operators are
and or nand nor xor not
 The relational operators are
= /= < <= > >=
 Adding Operators are
+ - &
 Multiplying Operators are
* / mod rem
 Miscellaneous Operators are
abs **

Operators
 Entity declaration

 Architecture body

 Configuration declaration

 Package declaration

 Package body

Design units
 •Specifies the name of the entity being
modeled and lists the set of I/O interface
ports.
entity name port names port mode (direction)

entity reg4 is
port ( d0, d1, d2, d3, en, clk : in bit;
q0, q1, q2, q3 : out bit ); punctuation
end reg4;

reserved words port type

Entity Declaration
 in: signal values are read-only
 out: signal values are write-only
multiple drivers
 Buffer: output signal values may be read as well
 inout:1.In order to model busses, where
multiple units have access to the same
data lines
2. Bidirectional port

I/O port modes

 Entity HA is
port ( A,B : in bit;
SUM,CARRY : out bit );
end HA;

ENTITY Eg.
● Describes an implementation of an entity

● may be several per entity

● As a set of interconnected components

● As a set of concurrent assignment statements

● As a set of sequential assignment statements

● Any combination of the above three.

Architecture
architecture HA_CONCURRENT of HA is
begin
SUM <= A xor B after 8 ns;
CARRY <= A and B after 4 ns;
end HA_CONCURRENT;

Architecture Eg.
 A configuration declaration is used to select one
of the possibly many architecture bodies that an
entity may have
 we also have to choose between various alternative
entities.
 suppose an alternate architecture of half adder is
available or the component is defined in the library as
HALF_ADD.
 In such case, we need to use a configuration
statement in the declaration zone i.e. after component
declaration and before “begin”

Configuration
Configuration Eg.
 entity HA is
port(a, b :in BIT; s, c: out BIT);
end HA;
 architecture dataflow of HA is
begin
……..
end dataflow;
 architecture struct of HA is
begin
………
end struct;

Configuration Eg.
  entity HALF_ADD is
port(sum, cy: out std_logic; x, y: in std_logic;);
end HALF_ADD;
architecture DF of HALF_ADD is
begin
sum <= x xor y;
cy <= x and y;
end DF;

Configuration Eg.
 Configuration MYCONFIG of FA is
For struct
For H1: HA use entity HA (dataflow); end for;
For H2: HA use entity COMP_LIB.HALF_ADD
(DF)
port map (x => a, y => b, sum => s, cy => c);
end for;
For ORG: OR2 use entity OR2 (dataflow);
end for;
End for;
End MYCONFIG;

Configuration Eg.
 A package declaration is used to store a set of
common declarations like components,
types, procedures, and functions.

 These declarations can then be imported into

other design units

 A package body contains the definitions of

subprograms declared in a package declaration.

Package Declaration & Body

package EXAMPLE_PACK is
type SUMMER is (MAY, JUN, JUL, AUG, SEP);
component D_FLIP_FLOP
port (D, CK: in BIT; Q, QBAR: out BIT);
end component;
constant PIN2PIN_DELAY: TIME := 125 ns;
function INT2BIT_VEC (INT_VALUE:
INTEGER)
return BIT_VECTOR;
end EXAMPLE_PACK;

Package Declaration Eg.

package body EXAMPLE_PACK is
function INT2BIT_VEC (INT_VALUE:
INTEGER)
return BIT_VECTOR is
begin
--Behavior of function described here.
end INT2BIT_VEC;
end EXAMPLE_PACK;

Package Body Eg.

 The “generate” statement can be used for
replicating any set of concurrent
statements/Multiple copies of a component

 E.g. Iterative networks like generating an n-bit

ripple-counter from n T flip-flops, n-bit shift
register from n D flip-flops, word-adder from a
16 bit-adders etc.

 The statement has two forms namely

“for … generate” and “if…generate”.

GENERATE
Byte adder
architecture structural of BA is
component FA
port(x,y,ci:in std_logic;sum,co:out std_logic);
end component;
signal c:std_logic_vector(6 downto 0);
begin
FA0 :FA port map(a(0),b(0),cin,s(0),c(0));
FAmid:for i in 1 to 6 generate
FAm:FA port map(a(i),b(i),c(i-1),s(i),c(i));
end generate;
FA7 :FA port map(a(7),b(7),c(6),s(7),cout);
end structral;

Byte adder using “for…generate”

FA_GEN: for i in 0 to 7 generate
If i = 0 generate
FA0:FA port map(a(i),b(i), cin,s (i),c(i));
end generate;
If i >0 and I<7 generate
FAm:FA port map(a(i),b(i),c(i-1),s(i),c(i));
end generate;
If i =7
generate FA7:FA port map(a(i),b(i),c(i),s(i),cout);
end generate;
end generate FA_GEN;

Byte adder using “if…generate”

 In behavioral modeling, sequential
blocks like process, procedures and
functions are heavily used

Behavioral modeling
Architecture a of b is
Begin
Process(sensitivity list)
………….
…………….
End process
End a;

Process
 The statements within a procedure get
executed sequentially.
 A procedure can not return a value in its name
but it can return any number of values
through its “out” parameters.
 The formal parameters of a procedure can be
constants, variables or signals and their
modes can be in, out, or inout.

Procedures
 The statements within a function body get
executed sequentially.
 A function returns a single value in its name.
 The formal parameters of a function
can have only the input mode.
 By default, the “out” and “inout” parameters are
assumed to be “variable” objects and the “in”
parameters are assumed to be constants.

Function
The syntax of a “case” statement is as
follows.
case EXPRESSION is
when value1 => STATEMENT(S);
when value2 => STATEMENT(S);
-----------------
when others => STATEMENT(S);
end case;

CASE STATEMENT
entity GetRate is
port(HOUR:in integer;RATE:out real);
end GetRate;
architecture DATAFLOW of GetRate is
begin
process(HOUR)
begin
Case HOUR is
When 0|23 => RATE <= 1.00;
When 20 to 22|1 to 3 =>RATE <= 1.50;
When others =>RATE <= 2.00;
End case;
end process;
end DATAFLOW;

CASE STATEMENT
 Simple loop: The loop statement is used
to repeatedly execute a set of sequential
statements

 This is an endless loop and therefore,

“next”, “exit” or “return” statement
should be included.

 Syntax 1 (Simple loop):

[LABEL]: loop
Statement(s);
End loop [LABEL];

Simple loop
 While loop: The statement body is
repeatedly executed as long as the
CONDITION is true.

 However, an additional exit path may be

provided through an “exit” statement.

 Syntax 2 (While loop):

[LABEL]: while CONDITION loop
Statement(s);
End loop [LABEL];

While loop
•Syntax
[label]: for LOOP_VAR_NAME in
RANGE loop
Statement(s);
End loop [LABEL];

FOR Loop
Other statements are

 Next
 Exit
 Null
 Assert etc.

OTHER STATEMENTS
 test bench is a model that is used to verify the
correctness of a hardware model.
 A test bench has three main purposes:

TEST BENCH
entity TEST_BENCH is
end;
architecture TB_BEHAVIOR of TEST_BENCH is
component ENTITY_UNDER_TEST
port ( list-of-ports-their-types-and-modes);
end component;
Local-signal-declarations;
begin
Generate-waveforms-using-behavioral-constructs;
Apply-to-entity-under-test;
EUT: ENTITY_UNDER_TEST port map ( port-associations
);
Monitor-values-and-compare-with-expected-values;
end TB_BEHAVIOR;

TEST BENCH SYNTAX

process
constant OFF_PERIOD: TIME := 30 ns;
constant ON_FERIOD : TIME := 20 ns;
begin
wait for OFF_PERIOD;
D_CLK <= '1';
wait for ON_PERIOD;
D_CLK <= '0';
end process

Waveform Generation
EXAMPLES
Full adder
entity fulladder is
port(x,y,cin:in bit;cout,sum:out bit);
end fulladder;
architecture equations of fulladder is
begin
sum<=x xor y xor cin;
cout<=(x and y)or(x and cin)or(y and cin);
end equations;

FULL ADDER
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY mux IS
PORT (i0, i1, i2, i3, a, b: IN std_logic;
q : OUT std_logic);
END mux;
ARCHITECTURE better OF mux IS
BEGIN
q <= i0 WHEN a = '0' AND b = '0' ELSE
i1 WHEN a = '1' AND b = '0' ELSE
i2 WHEN a = '0' AND b = '1' ELSE
i3 WHEN a = '1' AND b = '1' ELSE
'X';
END better;

MULTIPLEXER
library ieee;
use IEEE.std_logic_1164.all;
entity clk is
port (ck:buffer bit);
end clk;
architecture clk1 of clk is
begin
process
begin
ck <='0';
wait for 10 ns;
ck <='1' ;
wait for 20 ns;
end process;
end clk1;

CLOCK GENERATION
entity tff is
port(t,c:in bit;q:inout bit;qn:inout bit:='1');
end tff;
architecture tff1 of tff is
begin
process(c)
begin
if c='0' then
if t='0' then
q<=q;
else if t='1'then
q <= not q;
end if;
end if;
end if;
end process;
qn<= not q;
end tff1;

T FLIPFLOP
Simulation Tool- ModelSim
 Basic Logic Gates

DRIVER
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------
entity Driver is
port( x: in std_logic;
F: out std_logic
);
end Driver;
----------------------------------------
architecture behv1 of Driver is
begin
process(x)
begin
-- compare to truth table
if (x='1') then
F <= '1';
else
F <= '0';
end if;
end process;
end behv1;
architecture behv2 of Driver is
begin
F <= x;
end behv2;

Driver Program & Simulation