Faculty Aswan Faculty of Engineering Unit Code

Department Electrical Engineering Dep. Unit Title Experiment (3)

Year/ Year 3 Lecturer
Semester Semester 2 ( 2016-2017) Assistant
Course Electrical Testing (Digital Design) LAB Computers and Systems
Engineering Lab
Student name:……………………….. Evaluator
Eng: …………………………
Date :………/………/……….
Marke: ……………../……….

 Experiment name:
Adder-Subtractor

 Main Goals:
 Providing introduction to adders, subtractors, decimal adders, and comparators.
 Designing a simple adder-subtractor circuit.
 Designing a comparator combinational circuit to compare between two different
numbers and output the results on LEDs.

 Exp. Purpose(s):
Constructing various adder and subtractor circuits as well as a comparator to compare
two numbers.

 Theoretical background:
Binary Adder-Subtractor
Digital computers perform a variety of information processing tasks. Among the
functions encountered are the various arithmetic operations. The most basic arithmetic
operation is the addition of two binary digits. This simple addition consists of four
possible element operations: 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = l and 1 + 1 = 10. The first three
operations produce a sum of one digit, but when both augend and addend bits are equal
to 1, the binary sum consists of two digits. The higher significant bit of this result is
called a carry. When the augend and addend numbers contain more significant digits, the
carry obtained from the addition of two bits is added to the next higher order pair of
significant bits. A combinational circuit that performs the addition of two bits is called a
half adder. One that performs the addition of three bits (two significant bits and a
previous carry) is a full adder. The names of the circuits stem from the fact that two half
adders can be employed to implement a full adder.
A binary adder-subtractor is a combinational circuit that performs the arithmetic
operations of addition and subtraction with binary numbers. We will develop this circuit
by means of a hierarchical design. The half adder design is carried out first, from which

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 we develop the full adder. Connecting n full adders in cascade produces a binary adder
for two n-bit numbers. The subtraction circuit is included by providing a complementing
circuit.

Half Adder
From the verbal explanation of a half adder, we find that this circuit needs two binary
inputs and two binary outputs. The input variables designate the augend and addend bits;
the output variables produce the sum and carry. We assign symbols x and y to the two
inputs and S (for sum) and C (for carry) to the outputs. The truth table for the half adder
is listed in Table 1. The C output is 1 only when both inputs are 1. The S output
represents the least significant bit of the sum.
The simplified Boolean functions for the two outputs can be obtained directly from the
truth table. The simplified sum of products expressions are

S  x' y  xy '
C  xy

The logic diagram of the half adder implemented in sum of products is shown in Figure
1(a). It can be also implemented with an exclusive-OR and an AND gate as shown in
Figure 1(b).
This form is used to show that two half adders can be used to construct a full adder.

Figure 1. Implementation of Half-Adder

Full-Adder
A full-adder is a combinational circuit that forms the arithmetic sum of three bits. It
consists of three inputs and two outputs. Two of the input variables, denoted by x and y,
represent the two significant bits to be added. The third input, z, represents the carry
from the previous lower significant position. Two outputs are necessary because the
arithmetic sum of three binary digits ranges in value from 0 to 3, and binary 2 or 3 needs
two digits. The two outputs are designated by the symbols S for sum and C for carry.
The binary variable S gives the value of the least significant bit of the sum. The binary
variable C gives the output carry. The truth table of the full adder is listed in Table 2.
The eight rows under the input variables designate all possible combinations of the three
variables. The output variables are determined from the arithmetic sum of the input bits.
When all input bits are 0, the output is 0. The S output is equal to 1 when only one input
is equal to 1 or when all three inputs are equal to 1. The C output has a carry of 1 if two
or three inputs are equal to 1.
The input and output bits of the combinational circuit have different interpretations at
various stages of the problem. Physically, the binary signals of the inputs are considered

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 binary digits to be added arithmetically to form a two-digit sum at the output. On the
other hand, the same binary values are considered as variables of Boolean functions
when expressed in the truth table or when the circuit is implemented with logic gates.
The maps for the outputs of the full adder are shown in Figure 2. The simplified
expressions are:

S  x' y ' z  x' yz ' xy ' z ' xyz

C  xy  xz  yz

Figure 2. Maps for Full Adder

The logic diagram for the full adder implemented in sum of products is shown in Figure
3. It can be also implemented with two half adders and one OR gate, as shown in Figure
4. The S output from the second half adder is the exclusive-OR of z and the output of the
first half adder, giving:
S  z  ( x  y)
 z ' ( xy' x' y )  z ( xy ' x' y )'
 z ' ( xy' x' y )  z ( xy  x' y ' )
 zy ' z ' x' yz ' xyz  x' y ' z

The carry output is:

C  z ( xy' x' y)  xy  xy' z  x' yz  xy

Figure 3. Implementation of Full Adder in Sum of Products

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 Figure 4. Implementation of Full Adder with two Half Adders and an OR gate

Decimal Adder
Computers or calculators that perform arithmetic operations directly in the decimal
number system represent decimal numbers in binary coded form. An adder for such a
computer must employ arithmetic circuits that accept coded decimal numbers and
present results in the same code. For binary addition, it is sufficient to consider a pair of
significant bits together with a previous carry. A decimal adder requires a minimum of
nine inputs and five outputs, since four bits are required to code each decimal digit and
the circuit must have an input and output carry. There is a wide variety of possible
decimal adder circuits, depending upon the code used to represent the decimal digits.
Here we consider a decimal adder for the BCD code.

BCD Adder
Consider the arithmetic addition of two decimal digits in BCD, together with an input
carry from a previous stage. Since each input digit does not exceed 9, the output sum
cannot be greater than 9 + 9 + 1 = 19, the 1 in the sum being an input carry. Suppose we
apply two BCD digits to a 4-bit binary adder. The adder will form the sum in binary and
produce a result that ranges from 0 through 19. These binary numbers are listed in Table
3 and are labeled by symbols K, Z8, Z4, Z2, and Z1. K is the carry, and the subscripts
under the letter Z represent he weights 8, 4, 2, and 1 that can be assigned to the four bits
in the BCD code. The columns under the binary sum list the binary value that appears in
the outputs of the 4-bit binary adder. The output sum of two decimal digits must be
represented in BCD and should appear in the form listed in the columns under BCD
sum. The problem is to find a rule by which the binary sum is be converted to the correct
BCD digit representation of the number in the BCD sum.
In examining the contents of the table, it is apparent that when the binary sum is equal to
or less than 1001, the corresponding BCD number is identical, and therefore no
conversion is needed. When the binary sum is greater than 100l, we obtain a non-valid
BCD representation. The addition of binary 6 (0110) to the binary sum converts it to the
correct BCD representation and also produces an output carry as required.
The logic circuit that detects the necessary correction can be derived from the table
entries. It is obvious that a correction is needed when the binary sum has an output carry
K = 1. The other six combinations from 1010 through 1111 that need a correction have a
1 in position 4. To distinguish them from binary 1000 and 1001, which also have a 1 in
position 4, we specify further that either Z4 or Z2 must have a 1. The condition for a
correction and an output carry can be expressed by the Boolean function

C  K  Z8 Z 4  Z8 Z 2

When C = 1, it is necessary to add 0110 to the binary sum and provide an output carry
for the next stage.

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 A BCD adder that adds two BCD digits and produces a sum digit in BCD is shown in
Figure 5. The two decimal digits, together with the input carry, are first added in the top
4-bit adder to produce the binary sum. When the output carry is equal to zero, nothing is
added to the binary sum. When it is equal to one, binary 0110 is added to the binary sum
through the bottom 4-bit adder. The output carry generated from the bottom adder can
be ignored, since it supplies information already available at the output carry terminal. A
decimal parallel adder that adds n decimal digits needs n BCD adder stages. The output
carry from one stage must be connected to the input carry of the next higher-order stage.

Figure 5. Block diagram of a BCD adder

 Equipments (photos):

1. IC type 7483 4-bit binary adder,

2. IC type 7404 Hex inverters,
3. IC type 7408 Quadruple 2-input AND gates,
4. Toggle switches to provide logic-1 and -0 signals,
5. LEDs (light-emitting diode) indictor lamps,
6. Multimeter,
7. Breadboard,
8. Connecting wires,
9. DC voltage supplies (5-Volts, 0-Volts).

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 IC type 7483 4-bit binary adder IC type 7404 Hex inverters

IC type 7408 Quadruple 2-input AND gates Toggle switch

LED Multimeter

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 Breadboard Connecting Wires

0-30V Power Supply

 Type of Input data:

DC voltage (5-Volts, 0-volts).

 Execution steps:
In this experiment, you will construct and test various adder and subtractor circuits. The
subtractor circuit is then used for comparing the relative magnitude of two numbers.

Half-Adder
Design, construct, and test a half-adder circuit using one XOR gate and two NAND
gates

Full-Adder
Design, construct, and test a full-adder circuit using two ICs, 7486, and 7400.

Parallel Adder
IC type 7483 is a 4-bit binary parallel adder. The pin assignment is shown in Figure 6.
The two 4-bit input binary numbers are A1 through A4 and B1 through B4. The 4-bit sum
is obtained from S1 through S4; C0 is the input carry and C4 the output carry.
Test the 4-bit binary adder 7483 by connecting the power supply and ground terminals.
Then connect the four A inputs to a fixed binary number such as 1001 and the B inputs
and the input carry to five toggle switches. The five outputs are applied to indicator
lamps. Perform the addition of a few binary numbers and check that the output sum and
output carry give the proper values. Show that when the input carry is equal to 1, it adds
1 to the output sum.

Adder-Subtractor
The subtraction of two binary numbers can be done by taking the 2’s complement of the
subtrahend and adding it to the minuend. The 2’s complement can be obtained by taking
the l’s complement and adding 1. To perform A - B, we complement the four bits of B,
add them to the four bits of A, and add 1 through the input carry. This is done as shown
in Figure 7. The four XOR gates complement the bits of B when the mode select M = 1
(because x 1  x' ) and leave the bits of B unchanged when M = 0 (because x 0  x ).
Thus, when the mode select M is equal to 1, the input carry C0 is equal to 1 and the sum

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 output is A plus the 2’s complement of B. When M is equal to 0, the input carry is equal
to 0 and the sum generates A + B.

Figure 6. IC type 7483 4-bit binary adder

Figure 7. 4-bit adder-subtractor

Task:
Connect the adder-subtractor circuit and test it for proper operation. Connect the four A
inputs to a fixed binary number 1001 and the B inputs to switches. Perform the
following operations and record the values of the output sum and the output carry C4:

9+5 9-5
9+9 9-9
9 + 15 9 - 15

Show that during addition, the output carry is equal to 1 when the sum exceeds 15. Also
show that when A ≥ B, the subtraction operation gives the correct answer, A - B, and the
output carry C4 is equal to 1. But when A < B, the subtraction gives the 2’s complement
of B - A and the output carry is equal to 0.

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 Magnitude Comparator
The comparison of two numbers is an operation that determines whether one number is
greater than, equal to, or less than the other number. Two numbers, A and B, can be
compared by first subtracting A - B as done in Figure 7. If the output in S is equal to
zero, we know that A = B. The output carry from C4 determines the relative magnitude;
when C4 = 1, we have A ≥ B; when C4 = 0, we have A < B; and when C4 = 1 and S ≠ 0,
we have A > B.

It is necessary to supplement the subtractor circuit of Figure 7 to provide the comparison

logic. This is done with a combinational circuit that has five inputs, S1 through S4 and
C4, and three outputs designated by x, y, and z, so that:

x=1 if A = B (S=0000)
y=1 if A < B (C4=0)
z=1 if A > B (C4 = 1 and S ≠ 0000)

The combinational circuit can be implemented with the two ICs, 7404 and 7408.
Task:
Construct the comparator circuit and test its operation. Use at least two sets of numbers
for A and B to check each of the outputs x, y, and z.

 Type of Results:
 All outputs are directed to be displayed in the form of on/off LEDs,

 Safety Precautions:
 Make sure that Vcc, are connected in right way and have a common ground for
each ICs and connect in the right pins.
 Check the configuration of each IC by using the function for each pin in the IC
using IC's datasheet.
 Check the fabrication of each IC to know power dissipation and the maximum
number of loaded ICs.
 Each wire used in connection in experiment must be securely connected and
does not get crossed with other wires.
 Make sure no short circuits occur between any two pins.
 Check the direction and the arrangements of pins in ICs before starting
connecting the experiment.

 Exceptions and Error messages:

The amplitude of the input/output signal must be kept in TTL range; otherwise LEDs
will not show any results.

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 Check list:
Table 1. Half Adder
x y C S
0 0
0 1
1 0
1 1
Table 2. Full Adder
x y z C S
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3. Derivation of BCD Adder
Binary Sum BCD Sum
Decimal
K Z8 Z4 Z2 Z1 C S8 S4 S2 S1
0 0 0 0 0 0
0 0 0 0 1 1
0 0 0 1 0 2
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1 19

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