+

COMPUTER ORGANIZATION & ARCHITECTURE

Van-Khoa Pham (PhD.)
+ Chapter 3
A Top-Level View of Computer
Function and Interconnection
+
Computer Components

 Hardwired program
 The result of the process of connecting the various components in the desired
configuration

 Hardwired systems are inflexible

 Lots of work to re-wire, or re-toggle

 General purpose hardware can do different tasks. Instead of re-wiring, supply

a new set of control signals
+
Computer Components
 von Neumann architecture is a simple structure, capable of executing
any kind of program, given a properly programmed control unit,
without the need of hardware modification

 three key concepts:

 Data and instructions are stored in a single read-write memory
 The contents of this memory are addressable by location
 Execution occurs in a sequential fashion (unless explicitly modified) from
one instruction to the next Processor or
Central processing unit
Memory

Datapath Data
A control unit (control path) featuring a Registers Data
program counter for controlling program and
Instructions
execution
Instruction Address
An arithmetic and logic unit (ALU) also register
PC
register
Address

called data path for program execution Controllpath

+ Data
Sequence of
arithmetic
and logic
functions
Results

(a) Programming in hardware

Hardware
and Software Instruction Instruction

Approaches
codes interpreter

Control
signals

General-purpose
Data arithmetic Results
and logic
functions

(b) Programming in software

Figure 3.1 Hardware and Software Approaches

Levels of Representation
temp = v[k];
v[k] = v[k+1]; High Level Language
Program
v[k+1] = temp;
Compiler
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2) Assembly Language
sw $15, 4($2) Program

Assembler
0000 1001 1100 0110 1010 1111 0101 1000
1010 1111 0101 1000 0000 1001 1100 0110 Machine Language
1100 0110 1010 1111 0101 1000 0000 1001 Program
0101 1000 0000 1001 1100 0110 1010 1111

Machine Interpretatio

Control Signal
Specification
°
°
+ Bottlenecks in VN Architecture 7
 The Von Neumann Computer
8

 Advantage:
 Simplicity.
 Flexibility: any well coded program can be executed

 Drawbacks:
 Speed efficiency: Not efficient, due to the sequential program
execution (temporal resource sharing).
 Resource efficiency: Only one part of the hardware
resources is required for the execution of an instruction.
The rest remains idle.
 Memory access: Memories are about 5 times slower than
the processor
 CPU Main Memory
0
System 1
2
PC MAR Bus
Instruction
Instruction
Instruction
IR MBR

I/O AR
Data
Execution
unit Data
I/O BR Data
Data

I/O Module n–2

n–1

PC = Program counter
Buffers IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register

Figure 3.2 Computer Components: Top-Level View

 Memory Memory buffer
address register (MBR)
register (MAR) MEMORY
• Contains the data
• Specifies the to be written into
address in memory memory or
for the next read or receives the data
write read from memory

MAR
I/O address I/O buffer
register (I/OAR) register (I/OBR)
• Specifies a • Used for the
particular I/O exchange of data
+ device between an I/O
module and the
CPU
MBR
+
Fetch Execute Cycle
At the beginning of each instruction cycle

 The processor fetches an instruction from memory

 The program counter (PC) holds the address of the instruction to be

fetched next

 The processor increments the PC after each instruction fetch so that it will
fetch the next instruction in sequence

 The fetched instruction is loaded into the instruction register (IR)

 The processor interprets the instruction and performs the required action
0 3 4 15
Opcode Address

(a) Instruction format

0 1 15
S Magnitude

(b) Integer format

Program Counter (PC) = Address of instruction

Instruction Register (IR) = Instruction being executed
Accumulator (AC) = Temporary storage

(c) Internal CPU registers

0001 = Load AC from Memory

0010 = Store AC to Memory
0101 = Add to AC from Memory

(d) Partial list of opcodes

Figure 3.4 Characteristics of a Hypothetical Machine

 Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 0 PC 300 1 9 4 0 3 0 1 PC
301 5 9 4 1 AC 301 5 9 4 1 0 0 0 3 AC
302 2 9 4 1 1 9 4 0 IR 302 2 9 4 1 1 9 4 0 IR
• •
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 2
Step 1 Step 2
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 1 PC 300 1 9 4 0 3 0 2 PC
301 5 9 4 1 0 0 0 3 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 5 9 4 1 IR 302 2 9 4 1 5 9 4 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3 3+2=5
941 0 0 0 2 941 0 0 0 2
Step 3 Step 4
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 2 PC 300 1 9 4 0 3 0 3 PC
301 5 9 4 1 0 0 0 5 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 2 9 4 1 IR 302 2 9 4 1 2 9 4 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 5
Step 5 Step 6

Figure 3.5 Example of Program Execution

(contents of memory and registers in hexadecimal)
 Read Memory
Write
N Words
Address 0 Data

Data N–1

Read I/O Module Internal

Write Data

External
Address M Ports Data

Internal
Data Interrupt
Signals
External
Data

Instructions Address

Control
Data CPU Signals

Interrupt Data
Signals

Figure 3.15 Computer Modules

The interconnection structure must support the
following types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory

An I/O
module is
allowed to
exchange
data
Processor Processor
directly
reads an Processor reads data Processor
with
instruction writes a from an I/O sends data
memory
or a unit of unit of data device via to the I/O
without
data from to memory an I/O device
going
memory module
through the
processor
using direct
memory
access
A communication pathway
connecting two or more
devices
• Key characteristic is that it is a
shared transmission medium
Typically consists of multiple
communication lines
• Each line is capable of
transmitting signals representing
binary 1 and binary 0
System bus
• A bus that connects major
computer components (processor,
memory, I/O)
Signals transmitted by any
one device are available for
reception by all other
devices attached to the bus
I
• If two devices transmit during the
n
same time period their signals will
overlap and become garbled
n
e
Computer systems contain a t
B c
number of different buses
that provide pathways
between components at e
u t
various levels of the
computer system hierarchy
r
s i
c
The most common computer o
o
interconnection structures
are based on the use of one
or more system buses
n
n
 Data Bus
 Data lines that provide a path for moving data among system
modules

 May consist of 32, 64, 128, or more separate lines

 The number of lines is referred to as the width of the data bus

 The number of lines determines how many bits can be

transferred at a time

 The width of the data bus

is a key factor in
determining overall
system performance

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+ Address Bus Control Bus

 Used to designate the source or

destination of the data on the  Used to control the access and the
data bus use of the data and address lines
 If the processor wishes to
read a word of data from  Because the data and address lines
memory it puts the address of are shared by all components there
the desired word on the must be a means of controlling their
use
address lines
 Control signals transmit both
 Width determines the maximum command and timing information
possible memory capacity of the among system modules
system
 Timing signals indicate the validity
 Also used to address I/O ports of data and address information
 The higher order bits are
used to select a particular  Command signals specify operations
module on the bus and the to be performed
lower order bits select a
memory location or I/O port
within the module
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
 CPU Memory Memory I/O I/O

Control lines

Address lines Bus

Data lines

Figure 3.16 Bus Interconnection Scheme

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