Assignment

Dataflow Modeling
Write verilog code for the following, perform functional verification

1. Implement all gates

Code:
module logic_gates (input a,b, output y,z,c,d,e,f,g); //port declarations
assign y= a&b; //And logic
assign z= a|b; // OR logic
assign c= ~a; // NOT logic
assign d= ~(a&b); // Nand logic
assign e= ~(a|b); //Nor logic
assign f= a^b; // Ex-or logic
assign g= ~(a^b); // Ex-nor logic
endmodule

Simulation:

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2. 4 bit Binary to Gray code convertor

Code :
// implementation of 4bit binary to gray code converter
module bin2gray(input [3:0] bin,output [3:0] g_out); //port declaration
assign g_out[3]=bin[3]; // take input as same
assign g_out[2]=bin[3]^bin[2]; // do ex-or operation with 4th and 3rd bit
assign g_out[1]=bin[2]^bin[1]; // ex-or operation of 3rd and 2nd bit
assign g_out[0]=bin[1]^bin[0]; // ex-or operation of 2nd and 1st bit
endmodule

simulation:

3. 4 bit Binary to BCD convertor

Code:
module bintobcd(input a,b,c,d,output [4:0] b_out); //port declerations
assign b_out[0]=d;
assign b_out[1]= ((a&b)&(~c))| ((~a)&c);
assign b_out[2]= ((~a)&b)| (c&b);
assign b_out[3]= (a&(~b))&(~c);
assign b_out[4]= (a&b)|c;
endmodule

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Simulation:

4. 4 bit BCD to XS-3 code convertor

Code:
module bcd_to_xs3(
input a,
input b,
input c,
input d,
output w,
output x,
output y,
output z
);

assign w = (a | (b & c) | (b & d));

assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d)));
assign y = ((c & d) | ((~c) & (~d)));
assign z = ~d;
endmodule

Simulation:

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5. 1 bit comparator using equation

Code:
module bit1_comp (input a,b,output l,e,g);
assign l= (((~a))&b);
assign e= ~(a^b);
assign g= (a&(~b));
endmodule

Simulation:

6. 2 bit comparator using equation

Code:
module bit2_comp(input a0,a1,b0,b1,output l,e,g);
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 assign l=(((~a0)&(~a1)&(~b0)&b1)|(a0&(~a1)&b0&b1)|((~a0)&b0&(~b1))|
((~a0)&a1&b0));
assign e=(((~a0)&(~a1)&(~b0)&(~b1))|(a0&(~a1)&b0&(~b1))|((~a0)&a1&(~b0)&b1)|
(a0&a1&b0&b1));
assign g=((a1&(~b0)&(~b1))|(a0&a1&(~b1))|(a0&(~b0)));
endmodule

Simulation:

7. 2 bit comparator using operators

8. 8 bit comparator using vectors

Code:
module bit8_comp(input [3:0]a,b,output [2:0] y);
assign y[0]= a>b;
assign y[1]= (a==b);
assign y[2]= a<b;
endmodule

Simulation:

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9. Half adder using using derived equations

Code:
// implementation of half adder
module half_adder (input a,b,output sum,carry); //port decleration
assign sum= a^b; //sum logic
assign carry= a&b; //carry logic
endmodule

Simulation:

10. Full adder using derived equations

Code:
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module full_adder (input a,b,c_in,output sum,c_out);
//assign sum= a^b^c_in;
//assign c_out= (a&b)| (b&c_in) | (c_in&a);

assign sum =(a==b)?c_in:(~c_in),

c_out=(a==b)?a:c_in;
endmodule
Simulation:

11. Half subtractor

Code:
module half_subtractor(input a,b, output d,b_out);
assign d= a^b;
assign b_out=((~a)&b);
endmodule

Simulation:

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12. Full subtractor

Code:
module half_subtractor(input a,b, output d,b_out);
assign d= a^b;
assign b_out=((~a)&b);
endmodule
Simulation:

13. 4 bit Carry look ahead adder

14. 4 bit Carry Ripple Adder
15. 2 x 1 mux

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 Code:
module mux2_1 (input s,i0,i1,output y);
assign y= (s)?i0:i1;
//assign y=(((~s)&i0)|(s&i1));
Endmodule
Simulation:

16. 4 x 1 mux

Code:
module mux4_1(input i0,i1,i2,i3,
input [1:0]s,
output y);
assign y=(i0 & ~s[1] & ~s[0])| (i1 & ~s[1] & s[0])| (i2 & s[1] & ~s[0])|
(i3 & s[1] & s[0]);
// assign y=(s==2'b11)?i3:(s==2'b10)?i2:(s==2'b01)?i1:i0;
// assign y=s[1]?(s[0]?i3:i2):(s[0]?i1:i0);
Endmodule
Simulation:

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17. 8 x 1 mux using conditional operator
18. 4 x 2 encoder
19. Octal to binary encoder
20. Decimal to BCD encoder
21. 8 x 3 priority encoder
22. 8 x 3 priority encoder using conditional operator
23. Decimal to BCD priority encoder

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24. Octal to binary priority encoder
25. 2 x 4 decoder
26. 3 x 8 decoder

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