DCF Lab Question 9

Serial In Serial Out

Aim: To verify Serial In Serial Out using truth table.

Components used: 1 Switch, 4 D Flip Flops, 1 Battery (12 V), 1 Clock, 1 Ground,
1 Red Probe.
Principle: The data is loaded serially and retrieved serially. The output of the
first DFF is fed into the input of the next DFF at each clock cycle, eventually
reaching the last DFF / Output. This Shift register output is delayed from the
input.
Circuit Diagram:

Truth Table:

CLK Q3 Q2 Q1 Q0
Initially 0 0 0 0
1st Pulse 1 0 0 0
2nd Pulse 1 1 0 0
3rd Pulse 1 1 1 0
4th Pulse 1 1 1 1

Result: The circuit of Serial In Serial Out is verified with the truth table.
 Serial In Parallel Out

Aim: To verify Serial In Serial Out using truth table.

Components used: 1 Switch, 4 D Flip Flops, 1 Battery (12 V), 1 Ground, 1 Clock,
4 Red Probe.
Principle: SIPO mode accepts data serially under clock control i.e. the data
transmitted is one bit at a time in either left or right direction. The stored
information is produced as its output.
Circuit Diagram:

Truth Table:
CLK Q3 Q2 Q1 Q0
Initially 0 0 0 0
1st Pulse 1 0 0 0
2nd Pulse 1 1 0 0
3rd Pulse 1 1 1 0
4th Pulse 1 1 1 1

Result: The circuit of Serial In Serial Out is verified using truth table.
 Parallel In Parallel Out

Aim: To verify Parallel In Parallel Out using truth table.

Components used: 4 Switches, 4 D Flip Flops, 1 Battery (12 V), 1 Ground, 1
Clock, 4 Red Probe.
Principle: In PIPO mode of Shift Registers, there is no serial shifting of the data
and hence the Flip-Flops are not interconnected. The input and output to each
Flip-Flop is separate.
Circuit Diagram:

Truth Table:

CLK I3 I2 I1 I0
1 1 1 1 1

Result: The circuit of Serial In Serial Out is verified using truth table.
 Parallel In Serial Out

Aim: To verify Parallel In Serial Out using truth table.

Components used: 4 Switches, 1 D Flip Flops, 1 Battery (12 V), 1 Ground, 1
Clock, 4 Red Probe.
Principle: In PIPO mode of Shift Registers, there is no serial shifting of the data
and hence the Flip-Flops are not interconnected. The input and output to each
Flip-Flop is separate.
Circuit Diagram:

Truth Table:
CLK I3 I2 I1 I0 Output
1st Pulse 1 1 0 1 1
2nd Pulse 0 1 1 0 0
3rd Pulse 1 0 1 1 1
4th Pulse 0 0 0 1 1
Result: The circuit of Parallel In Serial Out is verified using truth table.