NAME OF THE SUBJECT: EE (MPMC Lab)

SUB CODE: 224

B-Tech (CSE) 3rd Semester

Submitted by: Ritu Raj Chanda

(Scholar id: 2012157)

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

NATIONAL INSTITUTE OF TECHNOLOGY SILCHAR
ASSAM, PIN-788010

(September-December 2021)
 Experiment-6
Aim of the experiment: Write a program to arrange number in ascending order using 8085 & verify.
Theory:
Instruction Cycles and Machine Cycles

During normal operation the microprocessor fetches sequentially, decodes and executes one
instruction after another until a HLT (halt) instruction is executed. The fetching, decoding and
execution of a single instruction constitutes an instruction cycle which consist of one to five read or
write operations between processor and memory or between processor and memory or between
processor and input/output devices.

Each memory or I/O operation requires a particular time period, called machine cycles. i.e the time
required to complete one operation of accessing memory, I/O, or acknowledging an external request.

Each machine cycle consists of 3 to 6 clock periods/cycles referred as T-states. T-state is defined as
one subdivision of the operation performed in one clock period. The terms T-state and clock period
are often used synonymously.
1. ORG Addr. Directive reserves the starting address for Program Code or data in specified memory
array,
2. LDA (LOAD ACCUMULATOR DIRECT) copies contents of specified memory location to
accumulator.
3. MOV A, M copies the data byte into accumulator from the memory specified by the address in H-L
pair.
4. MVI (MOVE IMMEDIATE DATA)moves immediate value to specified register.
5. LXI H (LOAD REGISTER PAIR IMMEDIATELY) loads 16 bit data in register pair designated by
operand.
6. INX Reg. (INCREMENT REGISTER PAIR) increments the contents of the register pair by one.
7. DCXReg.(INCREMENT REGISTER PAIR) decrements the contents of the register pair by one
8. CMP (COMPARE WITH ACCUMULATOR) compares the register/memory content to
accumulator
If (A) < (Reg/Mem) ; carry flag is set and zero flag is reset.
If (A) = (Reg/Mem) ; carry flag is reset and zero flag is set.
If (A) > (Reg/Mem) ; both carry flag and zero flag are reset.
9. JCAddr. instruction jump the execution to the specified Address if carry flag is set.
10. JNZAddr. instruction jump the execution to the specified Address if zero flag is reset.
11. DCR instruction decrement the specified register content by 1.
12. ADD M (ADDTION) adds the contents of memory to accumulator.
13. RST 1 (RESET) finishes the execution of the current instruction and stops any further execution.
14. DB Directive is defined to store values in specified memory array.
Program
# ORG 2000H
LDA F100 // Load count from F100 to Acc.
DCR A // Decrement A by 1
MOV C,A // A=>C
MOV B,C // C=>B
LXI H,F200 // HL <= F200
up:MOV A,M // [HL] =>A
INX H // HL+1=>HL
CMP M // Compare reg. M to A
JC down // If A< M jump condition is true
MOV D,M // M=> D
MOV M,A // A=>M
DCX H // HL-1 => Hl
MOV M,D // D<=M
INX H // HL+1=>HL
down:DCR B // Decrement b by 1
JNZ up // Jump until B=0
DCR C // Decrement C by 1
JNZ 2005 // Jump until C=0
RST 1 // Terminate

# ORG F100H // Store number count at the address

# DB 04 // Store Count
#ORG F200H // Store numbers at the address
#DB DD,CC,BB,AA // Store numbers at the address

Flowchart:-
Result: After execution of the programs we got the final results which are attached in the snapshots.
****End of experiment****