CHAPTER 1

INTRODUCTION

1.1The Operational Transconductance Amplifier

The operational transconductance amplifier (OTA) is an amplifier whose differential input

voltage produces an output current. Thus, it is a voltage controlled current source (VCCS). There
is usually an additional input for a current to control the amplifier's Transconductance. The
principle differences from standard op-amp are-
 Its output of a current contrasts to that of standard operational amplifier whose output is a
voltage.

 It is usually used "open-loop"; without negative feedback in linear applications. This is

possible because the magnitude of the resistance attached to its output controls its output
voltage. Therefore a resistance can be chosen that keeps the output from going into
saturation, even with high differential input voltages.

The schematic symbol of an Operational Transconductance Amplifier (OTA) is shown in Figure

1.1

Figure 1.1 OTA Symbol

1
The OTA converts an input voltage to an output current relative to a transconductance gain
parameter Gm=io/vi. Ideally the input and output resistances are infinite (Ri=Ro=∞) such that
ii=iRo=0 and the output current is absorbed solely by the load. The conventional OTA is classified
as a Class A amplifier and is capable of generating maximum output currents equal to the bias
current applied. The equivalent circuit model indicates the transconductance amplifier generates
an output current (io) proportional to an input voltage (vi) based on the transconductance gain Gm.
The open circuit voltage gain of the conventional OTA model IN Figure 1.1 (B) is given by
A=GmRo.

1.2 Local Common Mode Feedback

Industry is researching techniques to reduce power requirements, while increasing speed, to meet
the demands of low (battery) powered wireless systems. These systems require amplifiers with
low bias currents, capable of producing large dynamic currents. Application of Local Common
Mode Feedback (LCMFB) techniques to the conventional OTA architecture produces an
efficient class AB amplifier with enhanced gain-bandwidth and slew rate.

1.3 Characterization Parameters

Several common characterization methods are used to classify the functionality of OTA
structures. These performance measurement techniques will be used to analyze designed
structures via theoretical calculation, simulation, and experimentation throughout the
documentation presented in the following chapters. A list of the measured characteristics is
provided below.

1. Open Loop Gain (AOL)

2. Gain Bandwidth (GB)

3. Maximum Output Current (IOUTMAX)

4. Slew Rate (SR)

5. Static Power Dissipation (PSTATIC)

2
 CHAPTER 2

LITERATURE REVIEW

Xin Lei et al. [1]have discussed an operational amplifier structure which can increase SR
and GBW. The GBW of the whole operational amplifier is increased using transconductance
multiplication technology. Dynamic bias current controlling technology is utilized in the input
stage. Thus, the additional current source can enter the circuit of whole operational amplifier at
large-signal input and provide the extra conversion current to enhance SR. Output setting time of
operational amplifier consists of output large-signal setting time and output small-signal setting
time. In order to increase the output setting time, it is necessary to increase both the slew rate and
the gain-bandwidth product at the same time.

Mai M. Kamel et al. [2] have discussed the designing of a high bandwidth CMOS fully
differential tunable Second Generation Current Conveyor (CCII) based Operational
Transconductance Amplifier (OTA). The fully differential OT A is realized using two single-
ended CClls. The OTA is tuned via a variable MOS resistor. The transconductance gain (Gm) is
varied from 300.64pAN to IOI1.07pAN. The tunable OTA is used to realize a third order Gm-C
low pass filter with tunable cut-off frequency. The tuning range of the filter's cut-off frequency
varies from 48.42MHz to I30.32MHz. LTSPICE simulation results for both the OTA and the
filter using the 90nm CMOS technology model with IV single-ended voltage supply are
presented.

Raj Tiwari [3] has proposed a design of an 8- bit ADC. The maximum conversion rate for
the designed ADC is 4 Mega sampled per second. As literature suggests for medium resolution
ADCs (8 to 14 bit) pipelined architecture is most suited, hence in this design pipelined
architecture has been chosen. Use of Common Mode Feedback Network has been shown. Input
differential range of the ADC is 1v with 0.9v common mode. The analog to digital conversion is

3
achieved in three stages. First two stages generate 3 bit MSB each, last two bits are obtained
using a 2 bit flash stage. The design has been done using TSMC 0.18um CMOS technology.

Siddhartha et al. [4] presents a fast settling SRE (Slew Rate Enhancement) technique for
operational amplifiers. An op-amp using a constant-gm biasing together with the proposed SRE
circuit is designed and it is shown that stable large and small signal characteristics can be
achieved across the wide range of temperature. The op-amp was designed and laid out in Jazz
0.18μm process using 1.8V supply voltage. The core circuit consumes 3mA while the SRE
circuit has a static power consumption of only 200uA (%6.67 of the power of the core circuitry).
The slew rate of the op-amp has increased from 25 V/us to 150 V/us at room temperature. The
low variation of both small signal as well as large signal characteristics of the op-amp across the
temperature has been verified by Spectre simulation using PSP models.

Zahra Haddad Derafshi et al. [5] have proposed a fully-differential, high gain, high speed
and low power CMOS Operational Transconductance Amplifier (OTA). Gain boosting technique
which is proper for low supply voltage applications, has been used to achieve high gain and
common-mode feedback (CMFB) is used to stable the designed OTA against temperature and
other process variations.

Antonio J. López-Martín et al. [6] have proposeda simple technique to achieve low-
voltage power-efficient class AB operational transconductance amplifiers (OTAs) is presented. It
is based on the combination of class AB differential input stages and local common-mode
feedback (LCMFB) which provides additional dynamic current boosting, increased gain-
bandwidth product (GBW), and near-optimal current efficiency. LCMFB is applied to various
class AB differential input stages, leading to different class AB OTA topologies. Three OTA
realizations based on this technique have been fabricated in a 0.5- m CMOS technology. For an
80-pF load they show enhancement factors of slew rate and GBW of up to 280 and 3.6,
respectively, compared to a conventional class A OTA with the same 10- A quiescent currents
and 1-V supply voltages. In addition, the overhead in terms of common-mode input range, output
swing, silicon area, noise, and static power consumption, is minimal.

4
 Priyanka Kakoty et al. [7] have discussed the design of anOperational Transconductance
Amplifier (OTA) which employs a Miller capacitor and is compensated with a current buffer
compensation technique. The unique behavior of the MOS transistors in saturation region not
only allows this circuit to work at a low voltage, but also at a high frequency.

Houda Bdiri Gabbouj et al. [8] have discussed the design of the OTA. It operates at
supply voltages of about ±0.8V. Simulation results for 0.18μm TSMC CMOS technology show a
good input range of 1Vpp with a high DC gain of 81.53dB and a total harmonic distortion of -
40dB at 1MHz for an input of 1Vpp.

Tsung-Hsien Lin et al. [9] has presented a low-voltage low-power CMOS operational
transconductance amplifier (OTA) with near rail-to-rail output swing has been presented. The
proposed circuit is based on the current-mirror OTA topology. In addition, several circuit
techniques are adopted to enhance the voltage gain. Simulated from a 0.8-V supply voltage, the
proposed OTA achieves a 62-dB dc gain and a gain–bandwidth product of 160 MHz while
driving a 2-pF load. The OTA is designed in a 0.18- m CMOS process. The power consumption
is 0.25 mW including the common-mode feedback circuit.

Maxim Pribytko et al. [10] have proposed a high CMRR single-ended current-mirror
OTA employing a novel current CMFB. The OTA input/output common mode range, die area,
power and slewing speed are not affected. The settling speed is reduced by 5%-20%. The current
CMFB boosts the OTA CMRR by a factor of 30 while allowing integration of conventional OTA
improvements. A unified approach relating the CMRR and transistor mismatches is proposed.
The OTA was manufactured in a standard 0.25micrometer CMOS process as a precision
functional block of a 12 bit algorithmic ADC.

Anne-Johan Annema et al. [11] have discussed modern and future ultra-deep-submicron
(UDSM) technologies which introduce several new problems in analog design. Practical rules of
thumb based on measurements have been derived.

Chaiyan Chanapromma et al. [12] have proposed the design of a low-power, low-voltage
CMOS fully differential operational transconductance amplifier (OTA) operating in weak
inversion region. The proposed element allows the use of very small current for low-power and
lowvoltage features. The performances are examined through PSPICE simulations, displaying

5
usabilities of the new active element. The power consumption is about 35.5pW at ±0.75V. The
description includes examples as a current-mode full-wave rectifier and current splitter.

Seyed Javad Azhariet al. [13]have presented a linear Operational Transconductance

Amplifier (OTA) that combines two linearization techniques, one with adaptive biasing of
differential pairs and second with using of resistive source degeneration. OTA has ±0.9v power
supply and consumes 250 μw. Improvement of adaptive bias circuit and using class AB output
stage and CMFB circuit has enhanced the CMRR to 169dB in DC that reduces to 131dB at
1MHz. OTA has been simulated with TSMC 0.18μm CMOS technology in Hspice. The
simulated third order harmonic distortion (HD3) with applying a 600mvP-P differential input is -
65dB at 1MHz frequency.

6
 CHAPTER 3

DESIGN METHODOLOGY OF OPERATIONAL

TRANSCONDUCTANCE AMPLIFIER

3.1 The conventional transconductance amplifier

A conventional, one stage, Operational Transconductance Amplifier (OTA) configuration is

shown in Figure 3.1.

Fig. 3.1 Circuit of Conventional OTA

The OTA employs a differential input pair and three current mirrors. The differential input pair is
comprised of transistors M1, 2. The differential pair is biased by MB1, 2. Mirrors formed by M3,
5 and M4, 6 reflect currents generated in the differential pair to the output shell. The current
generated by the mirror of M3, 5 is then reflected to the output via the mirror formed by M7, 8.
The mirror gain factor, K, indicates the gain in mirrors formed by M3, 5 and M4, 6 with the

7
following relations: β5=Kβ3, β6=Kβ4 where β= (KP/2) (W/L). Cascoding transistors M9, 10 are
biased by Vcasn/Vcaspand provide increased gain via increased (cascoded) output resistance.

The conventional OTA is differentiated from other amplifiers by the fact that its only high
impedance node is located at the output terminal. The conventional OTA does not employ an
output buffer and is therefore, only capable of driving capacitive loads. The gain of the OTA
(GmRo) is dependent on the large output resistance of shell (M5-M10) and is decreased to
GmRo//RL≈GmLif a parallel resistive load RLis applied.

Common mode signals (Vi(+)=Vi(-)) are, ideally, rejected. For a common mode input voltage,
the currents are constant and will be: id1=id2=IBIAS/2, and iout=0. A differential input signal will
generate an output current proportional to the applied differential voltage based on the
transconductance of the differential pair. Although the output stage is a push-pull structure, the
conventional OTA is only capable of producing an output current with a maximum amplitude
equal to the bias current in the output shell (K*IBIAS,OS). For this reason, the conventional OTA is
a referenced as a Class A structure capable of producing maximum signal currents equal to that
of the bias current applied. Slew rate (SR) is directly proportional to the maximum output current
and is defined as the maximum rate of change of the output voltage.

SR = max (dvout(t)/dt)

For a single stage amplifier, the slew rate is the output current divided by the total load
capacitance. The conventional OTA therefore suffers the consequence that high speed requires
large bias currents which translates to large static power dissipation. Wireless and battery
powered systems require high slew rate and gain bandwidth values with low static power
dissipation. These requirements are difficult to achieve with class A structures such as the
conventional OTA. The proposed class AB structure with Local Common Mode Feedback
(LCMFB), presented ahead, can meet these requirements.

3.2 Signal Analysis

3.2.1 Open Loop Gain

Figure 3.2 will be referenced to determine the open loop gain.

8
 Figure 3.2 Conventional One Stage OTA Open Loop Gain Schematic

The output current, in terms of the mirror gain factor (K), is given by:

iout= Kid2 - Kidi 3.1

where,

idi= gm1Vi(-), id2= gm2Vi(+) 3.2

Assuming: gm1=gm2, and substituting (3.2) into (3.1):

iout= Kgm1,2{Vi(+)-Vi(-)} 3.3

This indicates the transconductance gain of the OTA is given by:

Gm= Kgm1, 2 3.4

The output resistance is a cascode resistance and is given by:

Rout=gm10r010r06||gm9r09r08 3.5

Combining equations (3.3) and (3.5), the output voltage is then given by:

9
 vout= ioutRout= Kgm1,2{Vi(+)-Vi(-)}gm10r010r06||gm9r09r08 3.6

and the open loop gain is:

Aol = vout/vin = Kgm1,2gm10r010r06||gm9r09r08 3.7

3.2.2 AC Analysis
Figure 3.2 will be referenced for AC analysis.

Figure 3.3 Conventional One Stage OTA AC Analysis Schematic

The gain bandwidth of the conventional one stage OTA is limited mainly by the low impedance,
high frequency, poles at nodes A/B, in conjunction with the high impedance, low frequency pole
at the output node.

The following analysis will define the high frequency pole and will assume nodes A and B are
equivalent nodes in terms of resistance and parasitic capacitance (M1=M2, M3=M4, and
M5=M6). The resistance at nodes A/B is dominated by the diode connected resistance (1/gm) of
M3, 4 and is given by:

1 1
RA, B = gm ||r 01 ,2 ≈ gm 3.8
3,4 3 ,4

10
The parasitic capacitance at A/B is given by:

C A , B= C dg1 , 2+C db1 , 2+C gs 3 ,4 +C db3 , 4 +C gd 5 ,6 +C gs 5 ,6 ≈ C gs3 , 4+C gs 5 ,6 3.9

Combining equation (3.8), (3.9), and the relation Cgs5, 6=KCgs3, 4the pole at A/B is:

1 gm 3 ,4
fp A, B= 2 π C R = 2 π (K +1)C R 3.10
A ,B A , B A ,B A ,B

The output node capacitance is dominated by the load capacitance (CL) and is:

C out= C dg 9+C db 9+C dg10 +C db10 +C L ≈ C L 3.11

Combining equation (3.5) and (3.11), the dominant pole/bandwidth of the OTA is given by:

1 1
fPout = 2 π R C = 2 π C (gm r r ∨¿ gm r r ) =f3dB
out out L 10 010 06 9 08 09

3.12

This analysis indicates the relation between the phase margin and the mirror gain factor (K).
Equation (3.10) indicates the high frequency pole f pA,B is inversely proportional to K. An increase
in K will result in a decrease in f pA,B and consequently a decrease in phase margin. The bandwidth
of the conventional OTA is given in Equation (3.12) and is inversely proportional to the load
capacitance (CL).

3.2.3 Gain Bandwidth

Equations (3.7) and (3.12) are combined for the gain bandwidth (GB) product:

GB = Kgm1, 2 / 2πCL 3.13

3.2.4 Maximum Output Current

The maximum output current of the conventional OTA is limited by the mirror gain factor (K)
and the bias current and is given by:

max
I out = KIBias 3.14

11
3.2.5 Slew Rate
The slew rate (SR) is given by:

SR= I max max

out / CL = I out / KIBias 3.15

The slew rate therefore, increases linearly with K.

3.3 DC Analysis

3.3.1 Static Power Dissipation

The static power dissipation (PSTATIC) is the product of the sum of the currents flowing through
the current sources or sinks with the power supply voltages and is given by:

PStatic = (VDD - VSS)[ I D ,M 1 + I D , M 2 + I D , M 5 + I D , M 6 + I D , MB 1] 3.16

and in terms of IBIASand K (Figure 3.1):

PStatic = (VDD - VSS)IBias (K+2) 3.17

An increase in the mirror gain factor (K) will increase the SR and GB of the conventional OTA
at the cost of increased area and static power dissipation and a decrease in phase margin.

3.3.2 Output Voltage Range

The output voltage range is defined asV max min
out , V out which represents the maximum output swing

available. The output range of the conventional OTA is reduced due to cascoding at the output
shown in Figure 3.4

12
 .

Figure 3.4 Conventional OTA Cascoded Output

The output voltage range is given as:

out = VDD- VDS, SAT6 – VDS, SAT10

V max 3.18

V out = VDD+ VDS, SAT8 + VDS, SAT9

min
3.19

3.3.3 Input Common Mode Range

The common mode range (CMR) is defined as the range of voltage ( V max min
¿ , V ¿ ) for which the

input differential pair will remain in saturation. This range is determined by the amplifier
structure, transistor sizes, and bias current. For the differential input stage with diode connected
loads, the minimum and maximum input voltages can be found by analysis of Figure 3.5.

13
 Figure 3.5 Input Differential Pair with Diode Connected Load

The minimum input voltage can be expressed as:

Sat Q Sat Q Sat

V ¿Min= V SS + V DSMB2 + V GS 1=V SS + V DSMB2 + V GS 1+V THN 1 + V DS 1 3.20

and substituting:

Sat
V DS 1=
√ 2 LI D
WKP
3.21

The minimum input voltage becomes:

V ¿ = V SS +V THN 1 +
Min

√ 2 I Bias LMB 2
KP N W MB 2 √I L
+ Bias 1
KP N W 1
3.22

Where, VTHN1is body effected and may be larger than the zero bias threshold voltage. The
minimum input voltage is therefore limited by the VDS, SATdrop requirements across M1, MB2 and
a threshold drop across M1. The minimum input voltage is inversely proportional to the widths
of transistors M1, MB2 and directly proportional to the bias current. To reduce V ¿Min the bias
current must be reduced or the widths of the input transistors must be increased.

14
3.3.4 Maximum Input Voltage
The maximum input voltage (Figure 3.4) can be expressed as:

Q Sat Q
V ¿ = V DD - V SG 3 - V DS 1+V GS 1=V DD - V GS 3+V THN 1
Max
3.23

Again, VTHN1is body effected and will be larger than anticipated. In this case, the body effect

actually increases input range by contributing toV ¿Max . These results indicate the bias current
must be reduced and the width of M3 must be increased to increase V ¿Max . The maximum input
voltage is, therefore, only limited by a VGSdrop across M3. For this reason, the input voltage
range is typically limited byV ¿Min. The common mode range of the NMOS differential pair is
capable of swinging further in the positive direction than the negative direction.

3.4 The Proposed Transconductance Amplifier

The proposed operational transconductance amplifier (OTA), with Local common mode
feedback (LCMFB) is shown in Figure 3.6

Figure 3.6 OTA with Local common mode feedback (LCMFB)

15
Similar to the conventional OTA, the LCMFB OTA utilizes a differential pair (M1, 2) and three
current mirrors (M3, 5, M7, 8, and M4, 6). In the LCMFB circuit however, the active load
transistors M3, 4 are reconnected to have a common gate (node C) and matched resistors R1, R2
(Figure 3.6) are used to connect the gate and drain terminals of M3, M4. This simple
modification has several performance enhancing benefits versus the conventional OTA
architecture including class AB operation which provides enhancement in slew rate (SR), gain
bandwidth (GB), and linearity, with equal static power dissipation. Implementation of resistors
R1, R2 with MOS transistors MR1, MR2, shown in Figure 3.8, provides programmable
performance characteristics (via the control voltage VR), allowing utilization of the same OTA
for multiple applications. Class AB operation characteristics allow the LCMFB structure to
outperform the conventional structure with unity mirror gain. The analysis for the LCMFB OTA
will therefore be based on a unity mirror gain factor (K=1, M3=M4=M5=M6, and M7=M8).

3.5 Why Local Common Mode Feedback is so advantageous?

There are several benefits of using LCMFB technique some of which are:

 Increase Slew Rate (SR)

 Increase Gain-Bandwidth (GB)

 Class AB Operation

 Low Static Power Dissipation

 Increase Amplifier Versatility Via Programmability

 Silicon minimal area (vs. conventional)

16
3.5.1 Common mode feedback circuit for the op-amp

Op-amp outputs

Common mode
C
Reference

Nominal Bias

Figure 3.7 Switched capacitor CMFB circuit

There are two type of CMFB circuit which are commonly used continuous time and switched
Capacitor. As clocks are already available for ADC stage, in this design Switched Capacitor
CMFB is used. The switches are controlled by sample and hold clocks.

In hold mode

Charge on the node Vc during hold mode

Q H =2 ( V bias−V cmref ) C

In Sample mode

Vc

Charge on the node Vc during sample mode

17
 QS =( V cmfb−V outp ) C+ ( V cmfb−V outm ) C

In Sample mode node Vc is not driven thus charge accumulated in HOLD phase will remain
same in Sample phase. Thus equating QH and QS and simplifying we get

V outp +V outm
V cmfb=V bias + −V cmref
2

Or

V cmfb =V bias +V outcm −V cmref

This shows the common mode error voltage (V outcm −V cmref ¿ to the amplifier.

3.6 Signal Analysis

3.6.1 Open Loop

Calculation of the open loop gain of the LCMFB OTA structure shown in figure 3.6 requires two
independent analyses. The differential input must be first analyzed followed by common source
output shell. The collective LCMFB OTA gain will then be defined as the combination of the
previous analyses. The following analysis will assume transistor matching for the following
devices M1=M2, M3=M4=M5=M6, M7=M8, and MR1=MR2. The gain will be analyzed
focusing on the path from the negative input terminal (at the gate of M1) to the output terminal.
This analysis will therefore focus on transistors M1, M3, MR1, and M5 but it should be noted
that analysis of the positive signal input (at the gate of M2) would yield identical results with
equivalent transistor substitutions as listed above.

3.6.2 Differential Input

The differential input stage is shown in Figure 3.8

18
 Figure 3.8 LCMFB OTA Differential Input Stage

The source and gate terminals of M3 are grounded (vgs3=0) in the small signal model eliminating
the dependent current source gm3vgs3. Thus the small signal current is given by:
id1, 2 = gm1, 2 vgs1, 2 3.24
and the equivalent resistance is given by:
RA, B = r01, 2|| r03, 4|| RMR1, 2 3.25

vA, Bare then a combination of (3.24) and (3.25) and is given by:
VA, B= iD1, 2 Rout = (r01, 2|| r03, 4|| RMR1, 2)(gm1, 2vgs1, 2 3.25
vd/2=vgs1,2and the gain of the differential (ACORE) input stage is given by:
V A , B gm 1 ,2 R A , B (r 01 , 2∨¿ r 03 , 4∨¿ R MR 1 ,2)(g m1 , 2)
Acore = VD
= =
2 2

3.26

3.6.3 Common Source Output Shell

The common source output shell is shown in Figure 3.9 and consists of two common source
amplifiers (M5, M6), a current mirror (M7, M8), and cascoding output transistors (M9, M10).
The cascoded output provides the large output resistance required for large gain in the output

19
shell. The output resistance of the LCMFB OTA is identical to that of the conventional OTA and
is given by:
ROUT = gm10r010r06||gm9r09r08 3.27

Figure 3.9 LCMFB OTA Common Source Output Shell

The current mirror has unity gain, and the gain of the output stage (AOS) is given by:
Ashell = 2gm5, 6(gm10r010r06||gm9r09r08) 3.28

3.6.4 Collective Open Loop Gain

The open loop gain of the LCMFB OTA is then given by the multiplication of the gain of the
input stage (ACORE) and the output shell (ASHELL) and is given by:

AOL = gm1, 2 RA, B gm5, 6 Rout 3.29

This definition indicates that the gain of the LCMFB OTA is a function of the programmable
resistance RMR1, 2. This dependence provides an interesting characteristic of functionality. For
RMR1, 2≈1/gm, RMR1, 2will dominate the parallel combination ro1, 2//ro3, 4//RMR1, 2, and the structure
will behave as a one stage amplifier(ACORE<<ASHELL). An increase in RMR1, 2≈ro1, 2//ro3, 4will result
in increased gain in the input stage and the structure will behave as a two stage amplifier
(ACORE<ASHELL). Two stage operations would eliminate the need for cascading transistors M9, 10
and would require compensation.

20
3.6.5 AC Analysis
Figure 3.10 is referenced for AC analysis

Figure 3.10 LCMFB One Stage OTA AC Analysis Schematic

Similar to the conventional OTA, the frequency response of the LCMFB OTA is determined
mainly by the low impedance, high frequency, poles at nodes A/B, in conjunction with the high
impedance, low frequency pole at the output node.
The following analysis defines the high frequency pole and assumes nodes A and B are
equivalent nodes in terms of resistance and parasitic capacitance (M1=M2, M3=M4, M5=M6,
MR1=MR2). The resistance at nodes A/B becomes a function of the triode resistance (RMR1, 2)
created by MR1, 2 and is given by:
RA, B = r01, 2||r03, 4||RMR1, 2 3.30
Given that node C is a virtual ground, the parasitic capacitance at nodes A/B does not include
Cgs3, 4. The addition of MR1, 2 does introduce an additional parasitic C sb, MR1, 2, but the well known
relation Cgs >> Csb, and the relative dimensions of the transistors W3 >> WMR, indicate the
parasitic capacitance at A/B is reduced by a factor close to 2 (K=1) versus the conventional
structure. The parasitic capacitance at A/B is given by:
CA, B = Cdb1, 2+Cdb3, 4+Cgd1, 2+Cgd5, 6+Cgs5, 6+CsbMR1, 2 ≈ Cgs5, 6 3.31

21
Combining equations (5.14) and (5.13), the pole at A/B is:
1
fPA, B= 2 πC gs 5 , 6(r 01 , 2∨¿ r 03 , 4∨¿ R MR 1 ,2)

3.32
The output node capacitance is dominated by the load capacitance and is equal to that of the
conventional structure
Cout = Cdg9 + Cdg10 + Cdb9 + Cdb10 + CL≈ CL 3.33
Thus, the dominant pole/bandwidth of the OTA is also equivalent to the conventional structure
and is given by:
1 1
fPout= 2 π C R = 2 π C (r 01 , 2∨¿ r 03 , 4∨¿ R MR 1 , 2) 3.34
out out L

3.6.6 Gain Bandwidth

gm 1 ,2 R A , B ( gm5 , 6 R out )
GB = 3.35
2 π C L Rout

The GB is dependent on the programmable resistance RMR1, 2. As RMR1, 2 increases, the GB

increases.

3.6.7 Maximum Output Current

The maximum output current can be found by analysis of Figure 3.11.

Figure 3.11 LCMFB OTA Maximum Output Current Schematic

Class AB operation provides large non-symmetric currents in the output shell. These currents are
created by the large gate-source voltage swings (generated at nodes A/B)applied to M5, M6.

22
Maximum output current generation occurs when the maximum gate-source differential is
applied to M6 (or M5) and M5 (or M6) is in cutoff.

The maximum output current is given by:

Out = (V SD ,Sat 3 , 4 +∆ V GS 5 , 6) × β 5 ,6
I Max Q Max 2
3.36

Max I Bias
∆ V GS 5 , 6= RMR1, 3.37
2

represents the maximum swing at nodes A and B.

3.6.8 Slew Rate

The slew rate (SR) is then given by:

Max
I Out
SR = 3.38
CL

An increase in RMR1, 2 translates to an increase in the slew rate.

3.6.9 Static Power Dissipation

The static power dissipation (PSTATIC) is the product of the sum of the currents flowing through
the current sources or sinks with the power supply voltages and is given by:

PStatic = (VDD- VSS) [ID, M1+ ID, M2+ ID, M5+ ID, M6+ ID, MB1] 3.39

And in terms of IBIAS (K=1 for the LCMFB structure):

PStatic = (VDD- VSS) 3Ibias 3.40

Class AB operation in the LCMFB OTA produces signal currents much larger than the bias
current applied with the same static power dissipation as that of the conventional structure
(K=1). The advantage of this operation is the capability to design high slew rate architectures
with low static power dissipation.

23
 CHAPTER 4
SOFTWARE TOOLS USED

4.1 LTSPICE IV

LTSpice IV is free high performance SPICE simulator software. LTSpice IV provides a

schematic capture and waveform viewer with enhancements and models to speed the simulation
of switching regulators. Included with LTspice IV are macro models for 80% of Linear
Technology's switching regulators and operational amplifiers models, as well as resistors,
transistors and MOSFET models.

LTSpice IV is node unlimited and 3rd party models can be imported. Circuit simulations based
on transient, AC, noise and DC analysis can be plotted as well as Fourier analysis. Heat
dissipation of components and efficiency reports can also be generated.

Figure 4.1 LTSpice IV Desktop

24
LTSpice IV is extensively used by IC designers and application engineers within LTC. It is used
by engineers professionally, and is used by academics as well, in RF, power electronics, digital
and other disciplines. LTSpice IV does not natively support PCB layout, but netlist can be
imported into various layout programs.

4.2 Tanner EDA Tools

Tanner EDA is a business unit of Tanner Research. It was founded in 1988 by Dr. John Tanner
as a means to develop and market cost-effective, easy-to- use EDA tools. Tanner had previously
founded Stac Electronics, a company responsible for the introduction of a patented disk-doubler
technology. Over the years, Tanner's extensive experience with ICs and other electronic
components made it readily apparent that few flexible, affordable tools existed for the creation of
innovative new products, thereby motivating the creation of Tanner EDA tools.

Tanner's S-Edit™ schematic capture tool, has been completely re-architected and rebuilt into a
new tool with user interface, performance and interoperability enhancements added. S-Edit
supports integrated analog simulation with automatic conversion from Cadence® and
ViewDraw® schematics. Users can run simulations and cross-probe from S-Edit, making the
design process real-time and more efficient. The ability to view operating point simulation
results directly on the schematic is another S-Edit productivity enhancing feature, plus multiple
libraries and language support for English, Chinese, Russian and Japanese, all combine to deliver
a comprehensive and interactive design environment.

25
 Figure 4.2 Tanner EDA Design Flow

The T-Spice™ Circuit Simulator product delivers highly accurate results by supporting the latest
foundry models, along with state-of-the-art numerical methods. T-Spice offers options and
commands not found in Berkeley SPICE or most derivatives, such as design optimization, Monte
Carlo analysis, multi-dimensional parameters, source and temperature sweeping. Tightly
integrated with Tanner EDA's S-Edit schematic entry and W-Edit waveform probing tools, T-
Spice provides the highest level of complexity for modeling and analysis.

Tanner’s L-Edit® tools for physical design product features integrated solutions for layout
editing, verification, placement and routing of Analog/Mixed-Signal ICs and MEMS. Its intuitive
and customizable interface minimizes the user’s learning curve. Plus its fast rendering – the
fastest on the market – significantly speeds the design cycle.

4.3 Microwind 3.0

The MICROWIND software allows the designer to simulate and design an integrated circuit at
physical description level. Microwind3 unifies schematic entry, pattern based simulator, SPICE
extraction of schematic, Verilog extractor, layout compilation, on layout mix-signal circuit
simulation, cross sectional & 3D viewer, netlist extraction, BSIM4 tutorial on MOS devices and

26
sign-off correlation to deliver unmatched design performance and designer productivity.
The package contains a library of common logic and analog ICs to view and simulate.

Figure 4.3 Microwind 3.0 Desktop

27
 CHAPTER 5

DESIGN AND IMPLEMENTATION OF PROPOSED OTA

5.1 Single Ended Proposed OTA

The conventional OTA (Figure 3.1(a)) uses a differential pair in conjunction with three current
mirrors to convert an input voltage into an output current. A Differential Amplifier has been
implemented using Microwind 3.0 with its simulation result shown in Figure 6.1 in Chapter 6.

Fig. 5.1 Differential Amplifier MSK

An approach to show that current mirror circuit is more beneficial than conventional Diode load
has been implemented using Microwind 3.0. The simulation of this circuit has been shown in
next chapter in Figure 6.2.

28
 Figure 5.2 Proposed OTA Circuit MSK

The schematic layout of Conventional Operational Transconductance Amplifier (Figure 3.1(a))

in S-Edit Tanner EDA Tool and LTSPICE IV is shown in Figure 5.3 below.

Fig. 5.3 S-edit Tanner EDA conventional OTA

29
Class AB operation characteristics allow the LCMFB structure to outperform the conventional
structure with unity mirror gain. The analysis for the LCMFB OTA will therefore be based on a
unity mirror gain factor (K=1, M3=M4=M5=M6, and M7=M8).
Figure 5.4 shows the LCMFB OTA structure with transistors MR1, MR2 implemented to
function in the triode region and act as programmable resistors.

Figure 5.4Schematic layout of Proposed OTA Circuit in S-Edit TANNER EDA Tool

For quiescent (or common mode) operation, the drain currents of transistors M1-M10 have equal
values (ID1-10=Ibias/2) while the current iR in transistors MR1, 2 is zero. The gate-source voltage of
M3, 4 is the same as their drain-source voltage. For common mode signals, these transistors
perform as low impedance (diode connected loads) with value:

1
RCM
L = 5.1
gm 3 , 4

Upon application of a differential signal, the signal current component (id=ir) flows through
transistors MR1, 2, and iD1, 2are given by:

30
 I Bias
iD1, 2=ID+ iD = + ir 5.2
2

where,

ir= gm3 , 4
vd
2 √1−
( v d /2
V GS 1 ,2−V THN 1 ,2 )( v d /2
V GS 1 ,2 −V THN 1 ,2 ) 5.3

and, vd is the applied differential voltage. The drain currents in M3, 4 remains unchanged
(iD3,4=IBIAS/2). The current ir generates differential complementary voltage changes at nodes A and
B while node C remains at a constant voltage.Signal voltages at nodes A and B are given by:

VA = -VB = irRMR1, 2 5.4

Where RMR1, 2 is the resistance generated by transistors MR1, MR2 and, based on the triode
channel resistance equation, is given by:

1
RMR1, 2= β 5.5
MR 1 ,2 ( V C −V THP −V R )

Where VR is the applied control voltage (Figure 5.1 (b)), βMR1, 2=KP (WMR1,2/LMR1,2), and VC is the
constant voltage at node C. This complementary swing at A, B generates large, non-
complimentary, signal current in the shell (M5-10) of the OTA by creating large gate-source
voltage differentials for common source transistors M5, M6, respectively. The schematic layout
of Proposed OTA architecture in S-Edit Tanner EDA tool and LTSPICE IV has been shown
below:

5.2 Design Parameters of Proposed OTA

The gain bandwidth of the conventional OTA is defined as:

GB = (Kgm1, 2)/ 2CL π 5.6

Rearranging equation (5.24), with unity mirror gain (K=1), the following equation can be used to
calculate the transconductance gain of the input differential pair.

2 π CL GB = gm1, 2 5.7

31
The transconductance of a MOS transistor can be calculated with the following expression:

gm =
√ 2 KPW I D
L
5.8

Using this expression, the width of the NMOS differential input pair (M1, 2) can be determined
based on a fixed bias current and predetermined length by rearranging Equation (5.26) for the
following relation:

W1, 2 = {(gm1, 2)2 L1, 2}/2KPNID 5.9

Utilizing a drain current of ID=IBIAS/2=250μA (for VDS, SAT≈0.25V), a length L1=3λ (L1, 2>LMIN=2λ
for improved matching) and recognizing KPN=3KPP, Equations (5.25) and (5.27) can be used to
size all transistors for the conventional OTA.Designed transistor sizes and corresponding VDS,
SAT voltages, based on theoretical calculations are listed below in Table 5.1.

Table 5.1 Conventional OTA Theoretical Design Transistor Sizes

TRANSISTORS DIMENSIONS (W/L) VDS, Sat (V)

M1=M2 4.122/0.18 µm 0.25
M3 1.912/0.18 µm 0.28

M4 7.21/0.18 µm 0.28

M5 7.7/0.18 µm 0.28

M6=M7=M8 5.18/0.18 µm 0.23

M9=M10, (LMIN) 1.098/0.18 µm 0.24

Cascoding output transistors (M9, M10) do not require matching design and were designed with
minimum length for speed. Their widths were reduced by a factor 2 to reduce area.

The SE-LCMFB OTA is designed for comparison with the conventional structure. For an
equivalent comparison, the SE-LCMFB structure is designed with core transistor sizes identical
to those of the conventional OTA listed in Table 5.1. The core of the SE-LCMFB structure is
therefore identical to the conventional structure and the only design required is the sizing of
triode resistance transistors MR1, MR2.

32
The resistance formed by MR1, 2 (RMR1, 2) can be used to trade slew rate and gain bandwidth
enhancement with phase margin for the class AB SE-LCMFB OTA. The high frequency pole at
nodes A/B, maximum output current, and open loop gain are all functions of R MR1, 2. RMR1, 2 is
programmable, is determined by the control voltage VR, and is given by:

1
RMR1, 2= (V −V −V ) β 5.10
C R TH MR 1 ,2 P

Where, VR is the control voltage applied at the gate of MR1, 2, VC is the constant voltage at node
C, and βMR1,2=KPP(WMR/LMR). For design of MR1, 2, a range of ΔRMR1, 2can be determined based
on a desired range of phase margin ΔPM. Simplifying for the position of the high frequency pole
(phase margin) as a function of the resistance RMR (assuming ro1≈ro2≈ro3≈ro4) the following
expression is obtained:

1
fpA, B = 2 π RMR 1, 2 C gs 5 ,6 5.11

This relationship indicates a decrease in fpA, Band consequently, a decrease in phase margin, as
RMR1, 2increases. A decrease in RMR1, 2 would then lead to an increase in fpA, Band an increase in the
phase margin. The design method for sizing MR1, 2 involves replacing transistors MR1, 2 with
resistors R1, 2 as shown in Figure 5.5.

33
 Figure 5.5 Schematic layout of Proposed OTA Circuit in LTSICE IV

A parametric step of resistors R1, 2 in simulation will then determine a desired range of
resistance (ΔRMR1, 2) corresponding to a desired range of phase margin (ΔPM≈40°<PM<80°). A
parametric simulation of the structure shown in Figure 5.5, with core transistor sizes listed in
Table 5.2, resulted in a resistance range of (RMR,MIN=200Ω>RMR1,2<RMR,MAX=1000Ω)
corresponding to a range of phase margin (40°<PM<80°).

WMRand LMRcan then be determined analytically by rearranging Equation (5.30) for the
following:

w MR 1 ,2 1
= K P (V −V −V ) R
L MR 1 ,2 P C R TH MR 1 , 2
P

5.12

The voltage at node C (VC) can be calculated, leaving the control voltage range ΔVR=VRMAX-
VRMINas the unknown variables. Simultaneous functions of Equation (5.30) can then be solved for
WMR1, 2/LMR1, 2based on a voltage range ΔVR that corresponds to the desired resistance range
ΔRMR1, 2. Results are shown below in Table 5.2.

34
 Table 5.2 SE-LCMFB MR1, 2 Design Transistor Sizes

PARAMETER MINIMUM VALUE MAXIMUM VALUE

Phase Margin 40° 90°
RMR1, 2 200 1000
VR (V) -1.75 -0.75
Transistors WMR1, 2(µm)/LMR1, 2(µm)
MR1, MR2 1.4/0.18 µm
MB1 1.098/0.18 µm
MB2 2.677/0.18 µm

35
 CHAPTER 6

RESULTS

6.1 Simulation Results

Point of maximum Current

Curve showing that NMOS and PMOS take some finite time
duration to get from ON state to OFF state and vice versa

Figure 6.1 Output waveform of Differential Amplifier Circuit

The simulation result of the differential amplifier shown in figure 5.1 is shown above. It is a
graph plotted between output voltage (y-axis) and input voltage (x-axis). It is evident that there is
a point of maximum current shown by dotted circle. There are various regions of operation
indicating the ON OFF time period of NMOS and PMOS. The curves indicate that NMOS and
PMOS don’t turn off or turn on instantly and take some finite duration.

36
 Figure 6.2 Output waveform of Proposed OTA Circuit

The simulation result of Proposed OTA Circuit (Figure 5.2) is shown above. From the simulation
graph it is evident that settling time is fast and due to the presence of NMOS Diode connected
load, rather than a current mirror circuit, the system is instable.

37
 Figure 6.3 Settling time comparison of Conventional and Proposed OTA Circuit

The Simulation graph of settling time of Conventional and Proposed OTA Circuit in LTSPICE
IV is shown in figure above. The settling time of Proposed OTA (1.44ns) is faster as compared
to Conventional architecture (0.54ns).

38
 (a)

(b)

Figure 6.4(a) Slew Rate and (b) Frequency response comparison of Conventional and Proposed OTA Circuit

From the simulation results above it is evident that the slew rate and frequency response of
Proposed OTA is better than the Conventional architecture.

39
 (a)

The phase margin is defined as the difference (in degrees) in the phase at unity gain and -180°.
The phase margin should be greater than 45° with an optimum, critically damped, value of 60°.
For PM values less than 60° the system is under-damped, and the transient response will indicate
increased slew rate at the cost of rise and fall peaking. For PM values greater than 60° the system
is over-damped, and the transient response will indicate decreased slew rate.

(b)

Figure 6.5 Phase margin comparison of (a) Conventional OTA Circuit (b)Proposed OTA Circuit

It can be seen that for conventional OTA the PM is higher than 60° indicating a decrease in slew
rate, whereas, for proposed method it is lower than 60°, thus, assuring greater slew rate and
marginal instability.

40
 Bandwidth for linear gain of conventional OTA

(a)

Bandwidth for linear gain of proposed OTA

(b)

Figure 6.6 Gain comparison of (a) Conventional OTA Circuit (b) Proposed OTA Circuit

The gain comparison shows that Bandwidth of proposed OTA is linear over larger frequency
band as compared to conventional architecture.

41
Figure 6.7 L-edit layout of Conventional OTA Circuit

Figure 6.8L-edit layout of Proposed OTA Circuit

42
The L-edit Tanner layouts indicate a slight increase in silicon area of proposed architecture due
to additional hardware of common mode feedback circuit.

6.2 Results

Result analysis and result summary, for the single ended (SE-CONV, SE-LCMFB), with and
without local common mode feedback are presented in the following sections.

6.2.1 Result Analysis

Table 6.1 Table for comparative analysis

PARAMETERS [1] PROPOSED

WORK

Slew Rate (V/µs) 9.1 150

Bandwidth (GHz) 2.4 2.6

Maximum O/P 0.5 1.3

Current (mA)

Static Power 4.95 6.5

Dissipation (mW)

Phase Margin 88.3 55

(Degree)

From the above result analysis following conclusion can be derived

 Slew Rate increases by a factor of 16.

 Improved Bandwidth with proposed architecture.

 Slight increase in static power dissipation.

43
  Slight decrease in phase margin indicating better stability with increase in slew rate.

 Increase in output current.

CHAPTER 7

CONCLUSION

An optimized compensation strategy for two-stage CMOS OTA has been proposed for a high
frequency OPAMP design. Here, the slew rate and bandwidth has been increased by employing
thin and long transistors into the design at output stage and wide transistors in input stage. These
two techniques are able to increase the gain up to a great extent by increasing the output
resistance and input transconductance respectively. There is a slight increase in static power
dissipation of proposed architecture, but, the overall advantage of increased slew rate and gain
bandwidth product which is very important parameter of communication so it compensates for
this limitation.

44
 CHAPTER 8

APPLICATIONS

 The single ended Local Common Mode Feedback Network CMOS Operational
Transconductance Amplifier serves as prototype, and, hence, can be reconfigured to
many OTA architectures to be used in smart cards, credit cards, etc. for random number
generations.

 Implementation of pipelined Analog-to-digital converters.

 Fully Differential Charge Scaling Digital-to-Analog Converter.

 Battery powered system requires high gain bandwidth values, high slew rate and at the
same time very low static power dissipation. The Class AB characteristics of both the
single ended and fully differential OTA structures with local common mode feedback
match these requirements. The programmability of the LCMFB architecture, in
conjunction with its ability to generate large dynamic currents with low static power
dissipation, makes it an ideal choice for analog filtering, data conversion, and wireless
applications.

45
 CHAPTER 9

FUTURE WORK

The single ended Local Common Mode Feedback Network CMOS Operational
Transconductance Amplifier serves as prototype, and, hence, can be reconfigured to many OTA
architectures to be used in smart cards, credit cards, etc. for random number generations. This
single ended LCMFB CMOS OTA can be further enhanced to a fully differential LCMFB
Operational Transconductance Amplifier for improved performance in gain and phase margin as
well.

46
 REFERENCES

[1] Xin Lei, Dongbing Fu, Dongmei Zhu, and Chen Su, “A novel high-transconductance
operational amplifier with fast setting time”, 978-1-4244-5798-4/10/$26.00 ©2010 IEEE

[2] Mai M. Kamel, Eman A. Soliman, Soliman A. Mahmoud, “High Bandwidth Second
Generation Current Conveyor based Operational Transconductance Amplifier”, 978-1-61284-
857-0/11/$26.00 ©2011 IEEE

[3] Raj Tiwari, “Implementation of 8-bit 4 MSPS pipeline ADC”, National Conference on
Innovations in Communication System and System Design (ICS 2D-12), Gyan Ganga Institute of
Technology and Sciences, Jabalpur, 2012

[4] Siddhartha, Gopal Krishna, Bahar Jalali-Farahani, “A Fast Settling Slew Rate Enhancement
technique for Operational Amplifiers”,978-1-4244-7773-9/10/$26.00 ©2010 IEEE

[5] Zahra Haddad Derafshi, Mohammad Hossein Zarifi, “Low-Power High-Speed OTA in
0.35μm CMOS Process”, European Journal of Scientific Research ISSN 1450-216X Vol.37 No.3
(2009)

[6] Antonio J. López-Martín, Sushmita Baswa, Jaime Ramirez-Angulo, and Ramón González
Carvajal, “Low-Voltage Super Class AB CMOS OTA Cells With Very High Slew Rate and Power
Efficiency”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005

[7] Priyanka Kakoty, “Design of a high frequency low voltage CMOS operational amplifier”,
International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March
2011

[8] Houda Bdiri Gabbouj, Néjib Hassen and Kamel Besbes, “Low Voltage High Gain Linear
Class AB CMOS OTA with DC Level Input Stage”, World Academy of Science, Engineering
and Technology 80 2011

47
[9] Tsung-Hsien Lin, Member, IEEE, Chin-Kung Wu, and Ming-Chung Tsai, “A 0.8-V 0.25-mW
Current-Mirror OTA With 160-MHz GBW in 0.18µm CMOS”, IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 2, FEBRUARY 2007

[10] Maxim Pribytko, Patrick Quinn, “A CMOS Single-Ended OTA with High CMRR”, Solid-
State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European, Publication
Year: 2003 , Page(s): 293 – 296, IEEE Conference Publications

[11]Anne-Johan Annema, Member, IEEE, Bram Nauta, Senior Member, IEEE, Ronald van
Langevelde, Member, IEEE, and Hans Tuinhout, “Analog Circuits in Ultra-Deep-Submicron
CMOS”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005.

[12] Chaiyan Chanapromma, Phamorn Silapan, Danupat Duangmalai and Montree

Siripruchyanun, “An Ultra Low-Power Fully Differential Operational Transconductance
Amplifier (FD-OTA) Operating in Weak-inversion Region and Its Applications”, Proceedings of
the 1st International Conference on Technical Education (ICTE2009) January 21-22, 2010
Bangkok, Thailand

[13] Seyed Javad Azhari and Farzan Rezaei, “High linear, High CMRR, Low Power OTA with

Class AB Output Stage”, International Journal of Computer Theory and Engineering, Vol. 2, No.
4, August, 2010 1793-8201

[14]Current-Feedback Op Amp Analysis,Literature Number SLOA080, Texas Instruments

[15] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill

48
 APPENDIX

A. Design Issues

A.1 CMOS 0.18 µm process parameters for the designing of Proposed OTA

 KPn= 171e10-6  VDD= 1.8 Volts

 KPp= 37e10-6  GB-W= 100 MHz

 VTHN= 0.42  VR= -0.75 Volts

 VTHP= 0.41  IBias= 600e10-6

 CGDON= 8.58e10-10  ID= 300e10-6

 CGDOP= 7.82e10-10  CL= 10e10-12

 CJN= 9.47e10-4  COX= 8.488e10-3

 CJP= 1.21e10-3

A. 2 W/L ratio for CMOS 0.18 µm for the designing of Proposed OTA

W1 = W2 = 4.122 WB1 = 1.098

W3 = 1.912 WB2 = 2.677

W4 = 7.21 WR1 = WR2 = 1.4

W5 = 7.7

W6 = W7 =5.18

W8 = W9 = W10 = 1.098

49
B. Calculations

B.1 DESIGN SPECIFICATIONS:

IBIAS = 600 µA ID = 300 µA gm1 = GBW. 2π.CL

W1 = [((gm1)2.L1) / (2 KPN. ID)]

B.2 IMPORTANT FORMULAE FOREXPERIMENTAL ANALYSIS:

B.2.1 Open loop- gain

AOL = gm1, 2 RA, B gm5, 6 Rout

B.2.2 Gain Bandwidth

gm 1 ,2 R A , B ( gm5 , 6 R out )
GB =
2 π C L Rout

B.2.3 Maximum O/P Current

I Out = (V SD ,Sat 3 , 4 +∆ V GS 5 , 6) × β 5 ,6
Max Q Max 2

B.2.4 Slew Rate

Max
I Out
SR =
CL

Where, I Out = (V SD ,Sat 3 , 4 +∆ V GS 5 , 6) × β 5 ,6

Max Q Max 2

B.2.5 Power Dissipation

PStatic = (VDD- VSS) 3Ibias

B.2.6 Voltage at node C

50
 √
Vc = VDD- [VTHP +
I Bias L3
KP P L3
]

B.2.7 DOMINANT POLE

1
F3db = 2 π C R
L out

B.2.8 PARAMETRIC SWEEP TO DETERMINE RANGE OF R

CORRESPONDING TO: 40>PM>90:

RMRMIN = 200 RMRMAX = 1000

VRMIN = -1.75 V VRMAX = -0.75 V

51