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NAME: K.NITHESH SAI

ROLL NUMBER: 18R11A0515
SECTION: CSE 2A

1. Differentiate between RISC and CISC with at least

ten differences.
ANS->
RISC CISC
 Focus on software  Focus on hardware

 Transistors are used for more registers.  Transistors are used for storing
complex

Instructions.

 Code size is large.  Code size is small.

 An instruction execute in single clock cycle.  Instructions take more than one clock cycle.

 An instruction fit in one word.  Instruction are larger than size of one word.

 Very fewer instructions are present. The  A large number of instructions are present in the
numbers of instructions are generally less architecture.
than 100.

 Fixed-length encodings of the instructions  Variable-length encodings of the instructions. Example:

are used. Example: In IA32, generally all IA32 instruction size can range from 1 to 15 bytes.
instructions are encoded as 4 bytes.

 Simple addressing formats are supported.  Multiple formats are supported for specifying operands. A
Only base and displacement addressing is memory operand specifier can have many different
allowed. combinations of displacement, base and index registers.

 CISC supports array.

 RISC does not support array.
 Arithmetic and logical operations can be applied to both
 Arithmetic and logical operations only use memory and register operands.
register operands. Memory referencing is
only allowed by load and store instructions,
i.e. reading from memory into a register
and writing from a register to memory
respectively.  Implementation programs are hidden from machine level
programs. The ISA provides a clean abstraction between
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 Implementation programs exposed to programs and how they get executed.
machine level programs. Few RISC
machines do not allow specific instruction  Condition codes are used.
sequences.
 The stack is being used for procedure arguments and
 No condition codes are used. return addresses.

 Registers are being used for procedure

arguments and return addresses. Memory
references can be avoided by some
procedures

2. List and describe at least 10 computer

architectures
ANS->

1. Von Neumann Architecture: also known as the Von Neumann model, the
computer consisted of a CPU, memory and I/O devices. The program is stored in
the memory. The CPU fetches an instruction from the memory at a time and
executes it. Thus, the instructions are executed sequentially which is a slow
process. Neumann m/c are called control flow computer because instruction are
executed sequentially as controlled by a program counter. To increase the
speed, parallel processing of computer have been developed in which serial
CPU’s are connected in parallel to solve a problem. Even in parallel computers,
the basic building blocks are Neumann processors. The von Neumann
architecture is a design model for a stored-program digital computer that uses a
processing unit and a single separate storage structure to hold both instructions
and data. It is named after mathematician and early computer scientist John von
Neumann. Such a computer implements a universal Turing machine, and the
common "referential model" of specifying sequential architectures, in contrast
with parallel architectures. One shared memory for instructions (program) and
data with one data bus and one address bus between processor and memory.
Instructions and data have to be fetched in sequential order (known as the Von
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Neuman Bottleneck), limiting the operation bandwidth. Its design is simpler than
that of the Harvard architecture. It is mostly used to interface to external memory.

2. The Harvard architecture: It is computer architecture with separate storage and signal
pathways for instructions and data. It contrasts with the von Neumann architecture, where
program instructions and data share the same memory and pathways. The term originated from
the Harvard Mark I relay-based computer, which stored instructions on punched tape (24 bits
wide) and data in electro-mechanical counters. These early machines had data storage entirely
contained within the central processing unit, and provided no access to the instruction storage as
data. Programs needed to be loaded by an operator; the processor could not initialize itself.
Modern processors appear to the user to be von Neumann machines, with the program code
stored in the same main memory as the data. For performance reasons, internally and largely
invisible to the user, most designs have separate processor caches for the instructions and data,
with separate pathways into the processor for each. This is one form of what is known as the
modified Harvard architecture.
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1. Burroughs large systems:

In the 1970s, Burroughs Corporation was organized into three divisions with very
different product line architectures for high-end, mid-range, and entry-level business
computer systems. Each division's product line grew from a different concept for how to
optimize a computer's instruction set for particular programming languages. The
Burroughs Large Systems Group designed large mainframes using stack machine
instruction sets with dense syllables [NB 1] and 48-bit data words. The first such design
was the B5000 in 1961. It was optimized for running ALGOL 60 extremely well, using
simple compilers. It evolved into the B5500. Subsequent major redesigns include the
B6500/B6700 line and its successors, and the separate B8500 line. 'Burroughs Large
Systems' referred to all of these product lines together, in contrast to the COBOL-
optimized Medium Systems (B2000, B3000, B4000) or the flexible-architecture Small
Systems (B1000).
Founded in the 1880s, Burroughs was the oldest continuously operating entity in
computing, but by the late 1950s its computing equipment was still limited to
electromechanical accounting machines such as the Sensimatic; as such it had nothing to
compete with its traditional rivals IBM and NCR who had started to produce larger-scale
computers, or with recently founded Univac. While in 1956 it branded as the B205 a
machine produced by a company it bought, its first internally developed machine, the
B5000, was designed in 1961 and Burroughs sought to address its late entry in the market
with the strategy of a completely different design based on the most advanced computing
ideas available at the time. While the B5000 architecture is dead, it inspired the B6500
(and subsequent B6700 & B7700). Computers using that architecture are still in
production as the Unisys Clear Path Libra servers which run an evolved but compatible
version of the MCP operating system first introduced with the B6700. The third and
largest line, the B8500, had no commercial success. In addition to a proprietary CMOS
processor design Unisys also uses Intel Xeon processors and runs MCP, Microsoft
Windows and Linux operating systems on their Libra servers.
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2. PDP-11 architecture
The PDP-11 architecture is an instruction set architecture (ISA) developed by Digital
Equipment Corporation (DEC). It is implemented by central processing units (CPUs) and
microprocessors used in PDP-11 minicomputers. It was in wide use during the 1970s, but

was eventually replaced by the more powerful VAX-11 architecture in the 1980s. Sixteen-bit
words are stored little-endian (with least significant bytes first). Thirty-two-bit data—
supported as extensions to the basic architecture, e.g., floating point in the FPU Instruction
Set, double-words in the Extended Instruction Set or long data in the Commercial Instruction
Set—are stored in more than one format, including an unusual middle-endian format

sometimes referred to as "PDP-endian". The PDP-11's 16-bit addresses can address 64 KB.
By the time the PDP-11 yielded to the VAX, 8-bit bytes and hexadecimal notation were
becoming standard in the industry; however, numeric values on the PDP-11 always use octal
notation, and the amount of memory attached to a PDP-11 is always stated as a number of
words. The basic logical address space is 32K words, but the high 4K (addresses 1600008
through 1777778) are not populated because input/output registers on the bus responded to
addresses in that range. So originally, a fully loaded PDP-11 had 28K words.
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3. MIL-STD-1750A

MIL-STD-1750A or 1750A is the formal definition of a 16-bit computer instruction set

architecture (ISA), including both required and optional components, as described by the military
standard document MIL-STD-1750A (1980).In addition to the core ISA, the definition defines
optional instructions, such as a FPU and MMU. Importantly, the standard does not define the
implementation details of a 1750A processor. The 1750A supports 216 16-bit words of memory
for the core standard. The standard defines an optional memory management unit that allows 220
16-bit words of memory using 512 page mapping registers (in the I/O space), defining separate
instruction and data spaces, and keyed memory access control. Most instructions are 16 bits,
although some have a 16-bit extension. The standard computer has 16 general purpose 16-bit
registers (0 through 15). Registers 1 through 15 can be used as index registers. Registers 12
through 15 can be used as base registers.
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6.SuperH (or SH): It is a 32-bit reduced instruction set computing (RISC) instruction set
architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented
by microcontrollers and microprocessors for embedded systems. As of 2015, many of the
original patents for the SuperH architecture are expiring and the SH2 CPU has been
reimplemented as open source hardware under the name J2. Hitachi and STMicroelectronics
started collaborating as early as 1997 on the design of the SH-4. In early 2001, they formed the
IP Company SuperH, Inc., which was going to license the SH-4 core to other companies and was
developing the SH-5 architecture, the first move of SuperH into the 64-bit area. In 2003, Hitachi
and Mitsubishi Electric formed a joint-venture called Renesas Technology, with Hitachi
controlling 55% of it. In 2004, Renesas Technology bought STMicroelectronics's share of
ownership in the SuperH Inc. and with it the license to the SH cores. Renesas Technology later
became Renesas Electronics, following their merger with NEC Electronics. The SH-5 design
supported two modes of operation. SHcompact mode is equivalent to the user-mode instructions
of the SH-4 instruction set. SHmedia mode is very different, using 32-bit instructions with sixty-
four 64-bit integer registers and SIMD instructions. In SHmedia mode the destination of a branch
(jump) is loaded into a branch register separately from the actual branch instruction. This allows
the processor to prefetch instructions for a branch without having to snoop the instruction stream.
The combination of a compact 16-bit instruction encoding with a more powerful 32-bit
instruction encoding is not unique to SH-5; ARM processors have a 16-bit Thumb mode (ARM
licensed several patents from SuperH for Thumb]) and MIPS processors have a MIPS-16 mode.
However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather
than the 32-bit encoding. The evolution of the SuperH architecture still continues. The latest
evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting
unified into a superscalar SH-X core which forms a kind of instruction set superset of the
previous architectures. Today, the SuperH CPU cores, architecture and products are with
Renesas Electronics, a merger of the Hitachi and Mitsubishi semiconductor groups and the
architecture is consolidated around the SH-2, SH-2A, SH-3, SH-4 and SH-4A platforms giving a
scalable family.
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6.Power Architecture: Power Architecture is a registered trademark for similar reduced
instruction set computing (RISC) instruction sets for microprocessors developed and
manufactured by such companies as IBM, Freescale, Applied Micro, LSI, e2v and Synopsys.

The governing body is Power.org, comprising over 40 companies and organizations. "Power
Architecture" is a broad term including all products based on newer POWER, PowerPC and
Cell processors. The term "Power Architecture" should not be confused with IBM's different
generations of "POWER Instruction Set Architecture", an earlier instruction set for IBM
RISC processors of the 1990s from which the PowerPC instruction set was derived. Power
Architecture is a family name describing processor architecture, software, toolchain,
community and end-user appliances and not a strict term describing specific products or
technologies.

7. Intel Itanium architecture: Itanium is a family of 64-bit Intel microprocessors that

implement the Intel Itanium architecture (formerly called IA-64). Intel markets the
processors for enterprise servers and high-performance computing systems. The Itanium
architecture originated at Hewlett-Packard (HP), and was later jointly developed by HP and
Intel. Itanium-based systems have been produced by HP (the HP Integrity Servers line) and
several other manufacturers. As of 2008, Itanium was the fourth-most deployed
microprocessor architecture for enterprise-class systems, behind x86-64, Power Architecture,
and SPARC. The Poulson processor was released on November 8, 2012. While Intel said in
April 2015 that it continued to work on Poulson's successor Kittson, Hewlett-Packard was
the only remaining volume customer and even HP has since introduced Xeon-based
machines. It appears that Kittson, announced for mid-2017, will be the last Itanium released,
with a modest performance increase over Poulson. As of February 2016, Poulson was the
most recent processor available.

8. ETRAX CRIS:

The ETRAX CRIS is a series of CPUs designed and manufactured by Axis Communications for
use in embedded systems since 1993.[1] The name is an acronym of the chip's features: Ethernet,
Token Ring, and Axis - Code Reduced Instruction Set. Token ring support has been taken out
from the latest chips as it has become obsolete. n 1993, by introducing 10 Mbit/s Ethernet and
Token Ring controllers, the name ETRAX was born.The ETRAX-4 had improved performance
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than previous models, along with a SCSI controller. The ETRAX 100 features a 10/100 Mbit/s
Ethernet Controller (hence the name), along with ATA and Wide SCSI support.

9. eSi-RISC: eSi-RISC is a configurable CPU architecture from Ensilica. It is available in five

implementations: the eSi-1600, eSi-1650, eSi-3200, eSi-3250 and eSi-3260. The eSi-1600 and
eSi-1650 feature a 16-bit data-path, while the eSi-32x0s feature 32-bit data-paths. Each of these
processors is licensed as soft IP cores, suitable for integrating into both ASICs and FPGAs.

10. SPARC: The Scalable Processor Architecture (SPARC) is a reduced instruction set
computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems.
Since the establishment of SPARC International, Inc. in 1989, the SPARC architecture has been
developed by its members. SPARC International is also responsible for licensing and promoting
the SPARC architecture, managing SPARC trademarks (including SPARC, which it owns), and
providing conformance testing. SPARC International was intended to open the SPARC
architecture to create a larger ecosystem; and SPARC has been licensed to several
manufacturers, including Atmel, Cypress Semiconductor, Fujitsu, and Texas Instruments. As a
result of SPARC International, SPARC is fully open, non-proprietary and royalty-free.The first
implementation of the original 32-bit SPARC architecture (SPARC V7) were initially designed
and used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems
based on the Motorola 68000 series of processors. Later, SPARC processors were used in SMP
and CC-NUMA servers produced by Sun, Solbourne and Fujitsu, among others, and designed for
64-bit operation. As of July 2016, the latest commercial high-end SPARC processors are
Fujitsu's SPARC64 X+ (introduced in 2014 for its SPARC M10 server)and SPARC64 XIfx
(introduced in 2015 for its PRIMEHPC FX100 supercomputer); and Oracle's SPARC M7
(introduced in October 2015 for its high-end servers).

3. List various Instruction Formats

ANS->
1.Common Instruction Formats: Four common instruction formats:
(a) Zero-address instruction. (b) One-address instruction.
(c) Two-address instruction. (d) Three-address instruction.
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2.UltraSPARC III Instruction Formats:

3.8051 Instruction Formats

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4. Instruction and Data Format of 8085:

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5. IBM System/360 Instruction Format:

Instructions in the S/360 are two, four or six bytes in length, with the opcode in byte 0.
Instructions have one of the following formats:

 RR (two bytes). Generally byte 1 specifies two 4-bit register numbers, but in some cases,
e.g., SVC, byte 1 is a single 8-bit immediate field.
 RS (four bytes). Byte 1 specifies two register numbers; bytes 2-3 specify a base and
displacement.
 RX (four bytes). Bits 0-3 of byte 1 specify either a register number or a modifier; bits 4-7
of byte 1 specify the number of the general register to be used as an index; bytes 2-3
specify a base and displacement.
 SI (four bytes). Byte 1 specifies an immediate field; bytes 2-3 specify a base and
displacement.
 SS (six bytes). Byte 1 specifies two 4-bit length fields or one 8-bit length field; bytes 2-3
and 4-5 each specify a base and displacement. The encoding of the length fields is length-
1.

Instructions must be on a two-byte boundary in memory; hence the low-order bit of the
instruction address is always 0.
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