SWE1003- Digital Logic & Microprocessor Lab 

Digital Record 
 Combinational Circuit 

RegNo:  21MIS0332
Name:  KAUSHIK.K

1. Verification of Logic gates 

a. Verify the working of OR gate with its truth table

 
Inputs  output 
A  B  A+B 
0  0  0 
0  1  1 
1  0  1 
1  1  1
b. Verify the working of AND gate with its truth table 

Inputs  output 
A  B  A.B 
0  0  0 
0  1  0 
1  0  0 
1  1  1 
 c. Verify the working of NOT gate with its truth table

Input Output

A A̅

0 1

1 0
d. Verify the working of NOR gate with its truth table 

Inputs  output 
A  B  A+ B
0  0  1 
0  1  0 
1  0  0 
1  1  0
e. Verify the working of NAND gate with its truth table 

Inputs  output 
A  B  A.B
0  0  1 
0  1  1 
1  0  1 
1  1  0
f. verify the working of X- OR gate with its truth table 

Inputs  output 
A  B  AB

0  0  0
0  1  1 
1  0  1 
1  1  0
 g. Verify the working of X-NOR gate with its truth table 

Inputs  output 
A  B  A ⊕B
0  0  1 
0  1  0
1  0  0
1  1  1

2.Verification of Boolean Expressions 

 a) X+X’Y=X+Y
 
INPUT OUTPUT

X Y X+X’Y X+Y
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 1

Verification:
RHS:
X+Y=X(Y+Y’)+Y(X+X’)
=XY+XY’+XY+X’Y
=XY+XY’+X’Y
=X(Y+Y’)+X’Y
=X+X’Y’ = LHS
b) X’+XY=X’+Y 
 INPUT OUTPUT

X Y X’+XY X’+Y
0 0 1 1
0 1 1 1
1 0 0 0
1 1 1 1

Verification:
RHS:
X’+Y=X’(Y+Y’)+Y(X+X’)
=X’Y+X’Y’+XY+X’Y
=X’Y+XY+X’Y’
=X’(Y+Y’)+XY
=X’+XY = LHS
c) AB+A’C+BC=AB+A’C 
 INPUT OUTPUT

A B C AB+A’C+BC AB+A’C
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 1 1
1 0 0 0 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 1

Verification:
LHS:
AB+A’C+BC = AB(C+C’)+A’(B+B’)C+(A+A’)BC
= ABC+ABC’+A’BC+A’B’C+ABC+A’BC
= ABC+A’BC+ABC’+A’BC
= AB(C+C’)+A’C(B+B’)
= AB+A’C = RHS
 3. Simplify the expression to minimum number of literals and verify the
simplified expression experimentally 
a. (a + b + c’)(a’+ b’ + c) 

= (a+b + c’) (a’+ b’ + c) 

= aa’+ab’+ac+a’b+bb’+bc+a’c’+b’c’+cc’
= 0 +ab’+ac+a’b+0+bc+a’c’+b’c+0
= ab’+ac+a’b+bc+a’c’+b’c
= a’b+ab’+ac+a’c’+bc+b’c’
= a xor b + a xnor c + b xnor c

INPUT

a b c ab’+a’b+c
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
b.(x + y) (x + y’) 
= xx+xy’+xy+yy’
= x+xy’+xy+0
= x+x(y’+y)
= x+x
=x
4. Reduce the following Boolean expressions to the indicated number of
literals: 
a. A’C’ + ABC + AC’ to three literals 

= A’C’+ABC+AC’
= A’C’+A(BC+C’)
= A’C’+A((C’+B)(C+C’))
= A’C’+AC’+AB
= C’(A+A’)+AB
= AB+C’

INPUT OUTPUT

A B C AB+C’
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
b. (A’ + C) (A’ + C’) (A + B + C’D) to four literals 
= (A’A’+A’C’+A’C+CC’)(A+B+C’D)
= (A’+A’(C’+C)+0)(A+B+C’D)
= (A’+A’)(A+B+C’D)
= A’A+A’B+A’CD
= 0+A’(B+CD)
= A’B+A’CD (or) A’(B+CD)
 INPUT OUTPUT

A B C D A’(B+CD)

0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
5)EXPESS THE FOLLOWING EXPRESSION IN THE STANDARD SUM OF PRODUCT
FORM:
(b+d)(a’+b’+c)
=(b+d)(a’+b’+c)
=a’b+bb’+bc+a’d+b’d+cd
=a’d(c+c’)(d+d’)+bc(a+a’)(d+d’)+a’d(b+b’)(c+c’)+b’d(a+a’)(c+c’)+cd(a+a’)(b+b’)
=a’b(cd+cd’+c’d+c’d’)+bc(ad+a’d+ad’+a’d’)+a’d(bc+b’c+c’b+c’b’)
+b’d(ac+a’c+ac’+a’c’)+ cd(ab+a’b+ab’+a’b’)
=a’bcd+a’bcd’+a’bc’d+a’bc’d’+abcd+a’bcd+abcd’+a’bcd’+a’bcd+a’b’cd+a’bc’d+a
’b’c’d+ab’cd+ a’b’cd+ab’c’d+a’b’c’d+abcd+a’bcd+ab’cd+a’b’cd
=a’bcd+a’bcd’+a’bc’d+abc’d’a+abcd+abcd’+a’b’cd+a’b’c’d+ab’cd+ab’c’d’
=m7+m6+m5+m4+m1+m14+m3+m15+m11+m9
=sigma(m1+m3+m4+m5+m6+m7+m9+m11+m14+m15)
=Σm(1,3,4,5,6,7,9,11,14,15)

ab\cd 00 01 11 10
(c’d’) (c’d) (cd) (cd')
00(a’b’) 1 1
01(a’b) 1 1 1 1
11(ab) 1 1
10(ab’) 1 1

= b’d+bc+a’b
VCC
5.0V
S1
U6

U1
Key = Space NOT

AND2
S2 X1
U5
2.5 V
U4
Key = Space NOT
U2

OR3
S3
AND2

Key = Space U3

S4
AND2

Key = Space
6) WRITE THE FOLLOWING EXPRESSION IN STANDARD PRODUCT OF SUMS
FORM:
a’b+a’c’+abc
=a’b(c+c’)+a’c’(b+b’)+abc
=a’bc+a’bc’+a’bc’+a’b’c’+abc
=abc+a’b’c’+a’bc’+a’bc
= 111+000+010+011
=∑m(0,2,3,7)
=πM(1,4,5,6)
a\bc 00 01 11 10
(bc) (bc’) (b’c’) (b’c)
0(a) 0
1(a’) 0 0 0

= (a’+c)(b+c’)
VCC
5.0V

S1
U4

U2
Key = Space NOT X1

OR2 2.5 V
U1
S2

AND2

Key = Space

U3

OR2
S3
U5

Key = Space NOT

7)Simplify the following Boolean functions:
a) F(A, B, C, D) = ∏ (1, 3, 5, 7, 13, 15)
ANSWER:
AB\CD 00 01 11 10
(CD) (CD’) (C’D’) (C’D)
00(AB) 0 0
01(AB’) 0 0
11(A’B’ 0 0
)
10(A’B)

F(A,B,C,D) = (A+D’)(B’+D’)
b)F(A, B, C, D) = ∑(1, 3, 6, 9, 11, 12, 14)
ANSWER:
AB\CD 00 01 11 10
(C’D’) (C’D) (CD) (CD’)
00(A’B’ 1 1
)
01(A’B) 1
11(AB) 1 1
10(AB’) 1 1

F(A,B,C,D) = B’D + BCD’ + ABD’

VCC
5.0V
S1
U1

Key = Space AND3

S2
U5 X1

NOT U2 U4 2.5 V
Key = Space

S3
AND3 OR3

Key = Space
U3
S4
U6
AND2

Key = Space NOT

8) Simplify the following functions, and implement them NAND and NOR gate
circuits:
F(A, B, C, D) = AC’D’ + A’C + ABC + AB’C + A’C’D’
= C’D’(A+A’) +A’C + AC(B+B’)
= C’D’ + A’C + AC
= C’D’ + C(A’+A)
= C’D’ + C
AND/OR gate:
VCC
5.0V
S1
U5
U3
X1
Key = Space NOT
AND2
2.5 V
S2 U1
U6

OR2
Key = Space NOT

Substituting Equivalent NAND gate:

VCC
5.0V

S1
U6

U1 U2
Key = Space NAND2 X1
U4
S2 NAND2 NAND2 2.5 V
U7
U5
NAND2

Key = Space NAND2

U3 NAND2

NAND2
Implementation of NAND gate:
VCC
5.0V

S1
U6

U1
Key = Space NAND2
X1
S2 NAND2 U5
U7 2.5 V

NAND2
Key = Space NAND2
U3

NAND2

Substituting Equivalent NOR gate:

VCC
5.0V

S1
U2 U6 X1
U8

NOR2 NOR2 2.5 V

Key = Space NOR2
U10 U1
S2
U4 U7
NOR2 NOR2

Key = Space NOR2 NOR2

Implementation of NOR gate:

VCC
5.0V

S1
U8 X1

2.5 V
Key = Space NOR2
U10 U1
S2

NOR2 NOR2

Key = Space

9)Design a Half adder and verify the circuit using Multisim

INPUT OUTPUT

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
VCC
5.0V
X1

S1 2.5 V
X2

U1 2.5 V
Key = Space A SUM
B CARRY

S2
HALF_ADDER

Key = Space

10. Design a Full adder and verify the circuit using Multisim.

INPUT OUTPUT
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
VCC
5.0V

S1

X2
Key = Space
2.5 V X1

S2 U1 2.5 V
A SUM
B CARRY
CIN
Key = Space
FULL_ADDER
S3

Key = Space

11) Design a Half Subtractor and verify the circuit using Multisim.
INPUT OUTPUT

A B DIFFERENCE BORROW

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0
VCC
5.0V
X1

S1 2.5 V
U3
U1

Key = Space NOT X2

XOR2
2.5 V
S2

U2

Key = Space
AND2

12) Design a Full Subtractor and verify the circuit using Multisim
INPUT OUTPUT
A B C DIFFERENCE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
VCC
5.0V

S1 X1

2.5 V
U1
Key = Space

XOR2
S2

U2
U3
U4
Key = Space XOR2 X2
NOT
S3 AND2
U7 2.5 V
U6
U5
Key = Space OR2
AND2
NOT

13) Implement the following function using 8x1 Multiplexer

F(A,B,C,D)=Σ(0,1,3,4,8,9,15)
I0 I1 I2 I3 I4 I5 I6 I7
D’ 0 1 2 3 4 5 6 7
D 8 9 10 11 12 13 14 15
1 1 0 D’ D’ 0 0 D

INPUT OUTPUT

A B C D Y

0 0 0 0 1
 0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

VCC
5.0V

S1
U2

X1
Key = Space NOT
2.5 V

U1
D0 Y
S2 D1
D2 ~W
D3
D4
D5
D6
D7
Key = Space A
B
S3 C
~G

MUX_8TO1

Key = Space
S4

Key = Space
14) Design a 3x8 decoder and verify the circuit using Multisim.

INPUT OUTPUT
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 0 1 1 1 1 1 1 1
0 0 1 1 0 1 1 1 1 1 1
0 1 0 1 1 0 1 1 1 1 1
0 1 1 1 1 1 0 1 1 1 1
1 0 0 1 1 1 1 0 1 1 1
1 0 1 1 1 1 1 1 0 1 1
1 1 0 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 0
VCC X4
X3
5.0V X1 X2
2.5 V
2.5 V
2.5 V 2.5 V
S1

U1
A Y0
B Y1
Key = Space C Y2
Y3
Y4
S2 Y5
Y6 X7 X6 X5
Y7 X8
~G

DCD_3TO8
Key = Space
S3 2.5 V 2.5 V 2.5 V
2.5 V

Key = Space

15) You are asked to design the following circuit for your car. The warning
signal W should be set to high voltage (logical 1) if:
a) the engine is running and door is open; or
b) With the engine running, somebody is sitting in the driver‟s seat and the
belt is not fastened.
Otherwise output of the circuit is „0‟. The circuit should rely on the following
sensors:
sensors from engine(C=„1‟ if engine is running, otherwise it is „0‟)
Seat sensor (S=1 if somebody is sitting on the seat, otherwise „0‟)
Door sensor (D=1 if the door is closed, otherwise „0‟)
Belt sensor (B=1 if the belt is fastened, otherwise „0‟)
ANSWER:
 C S D B W

0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

VCC
5.0V

U1

Key = Space AND2 W

S
2.5 V
U3

Key = Space
OR2
D

U2

Key = Space
AND3
B

Key = Space