Computer Organization Questions and Answers –

Basic Organization
1. Assembly language
(A) Uses alphabetic codes in place of binary numbers used in machine language

(B) Is the easiest language to write programs

(C) Need not be translated into machine language

(D) None of these

Answer: Option A

2. Floating point representation is used to store

(A) Boolean values

(B) Whole numbers

(C) Real integers

(D) Integers

Answer: Option C

3. (2FAOC) 16 is equivalent to
(A) (195 084) 10

(B) (001011111010 0000 1100) 2

(C) Both (a) and (b)

(D) None of these

Answer: Option B

4. The idea of cache memory is based

(A) On the property of locality of reference

(B) On the heuristic 90-10 rule

(C) On the fact that references generally tend to cluster

(D) All of the above

Answer: Option A

5. Which of the following is lowest in memory hierarchy?

(A) Cache memory

(B) Secondary memory

(C) Registers

(D) RAM

Answer: Option B

. In a memory-mapped I/O system, which of the following will not be there?

 (A) LDA

(B) IN

(C) ADD

(D) OUT

Answer: Option A

12. In a vectored interrupt.

(A) The branch address is assigned to a fixed location in memory

(B) The interrupting source supplies the branch information to the processor through an interrupt
vector
(C) The branch address is obtained from a register in the processor

(D) None of the above

Answer: Option B

13. The circuit used to store one bit of data is known as

(A) Encoder

(B) OR gate
(C) Flip-Flop

(D) Decoder

Answer: Option C

14. Write Through technique is used in which memory for updating the data
(A) Virtual memory

(B) Main memory

(C) Auxiliary memory

(D) Cache memory

Answer: Option D
15. Generally Dynamic RAM is used as main memory in a computer system as it
(A) Consumes less power

(B) Has higher speed

(C) Has lower cell density

(D) Needs refreshing circuitry

Answer: Option A
Computer System Architecture MCQ

1. RTL stands for:

a. Random transfer language
b. Register transfer language
c. Arithmetic transfer language
d. All of these

2. Which operations are used for addition, subtraction, increment, decrement and complement
function:
a. Bus
b. Memory transfer
c. Arithmetic operation
d. All of these

3. Which operations are used for addition, subtraction, increment, decrement and complement
function:
a. Bus
b. Memory transfer
c. Arithmetic operation
d. All of these

4. Which language is termed as the symbolic depiction used for indicating the series:
a. Random transfer language
b. Register transfer language
c. Arithmetic transfer language
d. All of these

5. The method of writing symbol to indicate a provided computational process is called as a:

a. Programming language
b. Random transfer language
c. Register transfer language
d. Arithmetic transfer language

6. In which transfer the computer register areindicated in capital letters for depicting its function:
a. Memory transfer b. Register transfer
c. Bus transfer d. None of these

7. The register that includes the address of the memory unit is termed as the :
a. MAR b. PC
c. IR d. None of these

8. The register for the program counter issignified as :

a. MAR b. PC
c. IR d. None of these

9. In register transfer the instruction register as:

a. MAR b. PC
c. IR d. None of these
10. Which are the operation that a computer performs on data that put in register:
a. Register transfer b. Arithmetic
c. Logical d. All of these

11. In memory transfer location address is supplied by that puts this on address bus:
a. ALU b. CPU
c. MAR d. MDR

12. Operation of memory transfer are:

a. Read b. Write
c. Both d. None

13. In memory read the operation puts memory address on to a register known as :
a. PC b. ALU
c. MAR d. All of these

14. Which operation puts memory address in memory address register and data in DR:
a. Memory read b. Memory write
c. Both d. None

15. Arithmetic operation are carried by such micro operation on stored numeric data available in

a. Register b. Data
c. Both d. None

16. In arithmetic operation numbers of register and the circuits for addition at :
a. ALU b. MAR
c. Both d. None

17. Which operation are implemented using a binary counter or combinational circuit:
a. Register transfer b. Arithmetic
c. Logical d. All of these

18. Which operation is binary type, and are performed on bits string that is placed in register:
a. Logical micro operation
b. Arithmetic micro operation
c. Both
d. None

19. ----------- is a command given to a computer to perform a specified operation on some given data:
a. An instruction b. Command
c. Code d. None of these

20. An instruction is guided by to perform work according:

a. PC b. ALU c. Both a and b d. CPU

21. Two important fields of an instruction are:

a. Opcode b. Operand
c. Only a d. Both a & b

22. Each operation has its opcode:

a. Unique b. Two
c. Three d. Four
23. which are of these examples of Intel 8086 opcodes:

a. MOV b. ADD c. SUB

d. All of these

24. --------------------- specify where to get the source and destination operands for the
operation specified by the :
a. Operand fields and opcode
b. Opcode and operand
c. Source and destination
d. CPU and memory

25. The source/destination of operands can be the or one of the general-purpose register:
a. Memory b. One
c. both d. None of these

26. Which is the method by which instructionsare selected for execution:

a. Instruction selection
b. Selection control
c. Instruction sequencing
d. All of these

27. ---------------- is the sequence n of operations performed by CPU in processing an

instruction:
a. Execute cycle
b. Fetch cycle
c. Decode
d. Instruction cycle

28. The time required to completeone instruction is called:

a. Fetch time
b. Execution time
c. Control time
d. All of these

29. ____ is the step during which anew instruction is read from the memory:
a. Decode
b. Fetch
c. Execute
d. None of these

30. ________ is the step during which the operations specified by the instruction
are executed:
a. Execute
b. Decode
c. Both a& b
d. None of these
 31. The instruction fetch operation is initiated by loading the contents of program counter into
the------ and sends request to memory:
a. Memory register and read
b. Memory register and write
c. Data register and read
d. Address register and read

32. __________ are the codes that represent alphabetic characters, punctuation marks and other
special characters:
a. Alphanumeric codes
b. ASCII codes
c. EBCDIC codes
d. All of these

33. Abbreviation ASCII stands for:

a. American standard code for information interchange
b. Abbreviation standard code for information interchange
c. Both
d. None of these

34. Group of binary bits(0&1) is known as:

a. Binary code
b. Digit code
c. Symbolic representation
d. None of these

35. A group of 4 binary bits is called:

a. Nibble
b. Byte
c. Decimal
d. Digit

36. Which is the method of parity:

a. Even parity method
b. Odd parity method
c. Both
d. None of these

37. Which are designed to interpret a specified number of instruction code:

a. Programmer
b. Processors
c. Instruction
d. Opcode

38. Which code is a string of binary digits:

a. Op code
b. Instruction code
c. Parity code
d. Operand code
39. The list of specific instruction supported by the CPU is termed as its :
a. Instruction code
b. Parity set
c. Instruction set
d. None of these

40. is divided into a number of fields and is represented as a sequence of bits:

a. instruction
b. instruction set
c. instruction code
d. parity code

41. Which unit is necessary for the execution of instruction:

a) Timing
b) Control
c) Both
d) None of these

42. Which unit provide status , timing and control signal:

a. Timing and control unit
b. Memory unit
c. Chace unit
d. None of these

43. Which unit acts as the brain of the computer which control other peripherals and interfaces:
a. Memory unit
b. Cache unit
c. Timing and control unit
d. None of these

44.Which unit works as an interface between theprocessor and all the memories on chip or off-
chip:
a. Timing unit
b. Control unit
c. Memory control unit
d. All of these

45.. --------- is given an instruction in machine language this instruction is fetched from the memory
by the CPU to execute:
a. ALU
b. CPU
c. MU
d. All of these
46. Which cycle refers to the time period during which one instruction is fetched and executed by the
CPU:
a. Fetch cycle

b. Instruction cycle
c. Decode cycle
d. Execute cycle

47. Which are stages of instruction cycle:

a. Fetch b. Decode
c. Execute
d. Derive effective address of the instruction
e. All of these

48. How many stages of instruction cycle:

a. 5
b. 6
c. 4
d. 7

49. ______________ is an external hardware event which causes the CPU to interrupt the current
instruction sequence:
a. Input interrupt b. Output interrupt
c. Both d. None of these

50.. ISR stand for:

a. Interrupt save routine
b. Interrupt service routine
c. Input stages routine
d. All of these

51. Which interrupt services save all the register and flags:
a. Save interrupt
b. Input/output interrupt
c. Service interrupt
d. All of these
52. IRET stand for:
a. Interrupt enter
b. Interrupt return
c. Interrupt delete
d. None of these

53. Which are benefit of input/output interrupt:

a. It is an external analogy to exceptions
b. The processor initiates and perform all I/O operation
c. The data is transferred into the memory through interrupt handler
d. All of these

54. Which are the causes of the interrupt:

a. In any single device
b. In processor poll devices
c. In a device whose ID number is stored on the address bus
d. All of these

55. Which are the functioning of I/O interrupt:

a. The processor organizes all the I/O operation for smooth functioning
b. After completing the I/O operation the device interrupt the processor
c. Both
d. None of these

56. ________ with which computers perform is way beyond human capabilities:
a. Speed b. Accuracy
c. Storage d. Versatility

57. ________of a computer is consistently:

a. Speed b. Accuracy
c. Storage d. Versatility
58. 0 and 1 are know as :
a. Byte b. Bit c. Digits d. Component

59. 0 and 1 abbreviation for:

a. Binary digit b. Octal digit
c. Both d. None of these

60. How many bit of nibble group:

a. 5 b. 4 c. 7 d. 8

61. How many bit of bytes:

a. 3 b. 4 c. 6 d. 8

62. Which is the most important component of a digit computer that interprets the instruction and
processes the data contained in computer programs:
a. MU b. ALU c. CPU d. PC

63. Which part work as a the brain of the computer and performs most of the calculation:
a. MU b. PC c. ALU d. CPU

64. Which is the main function of the computer:

a. Execute of programs
b. Execution of programs
c. Both
d. None of these

65. How many major component make up the CPU:

a. 4 b. 3 c. 6 d. 8

66. Which register holds the current instruction to be executed:

a. Instruction register
b. Program register
c. Control register
d. None of these
67. Which register holds the address of next instruction to be executed:
a. Instruction register
b. Program register
c. Program control register
d. None of these

68. Each instruction is also accompanied by a :

a. Microprocessor
b. Microcode
c. Both
d. None of these

69. Which are microcomputers commonly used for commercial data processing, desktop publishing
and engineering application:
a. Digital computer
b. Personal computer
c. Both
d. None of these

70. Which microprocessor has the control unit, memory unit and arithmetic and logic unit:
a. Pentium IV processor
b. Pentium V processor
c. Pentium III processor
d. None of these

71. The processing speed of a computer depends on the of the system:

a. Clock speed
b. Motorola
c. Cyrix
d. None of these

72. Which microprocessor is available with a clock speed of 1.6 GHZ:

a. Pentium III b. Pentium II
c. Pentium IV d. All of these
73. Which processor are used in the most personal computer:
a. Intel corporation’s Pentium
b. Motorola corporation’s
c. Both
d. None of these

74. A number system that uses only two digits, 0 and 1 is called the :
a. Octal number system
b. Binary number system
c. Decimal number system
d. Hexadecimal number system

75. In which computers, the binary number are represented by a set of binary storage device such as
flip flop:
a. Microcomputer
b. Personal computer
c. Digital computer
d. All of these

76. A binary number can be converted into

:
b. Octal number
c. Decimal number
d. Hexadecimal number
a. All of above

77. Which are the system of arithmetic, which are often used in digital system:
a. Binary digit
b. Decimal digit
c. Hexadecimal digit
d. Octal digit
e. All of these

78. In any system, there is an ordered set of symbols also known as :

a. Digital

b. Digit
c. Both
d. None of these

79. Which is general has two parts in number system:

a. Integer
b. Fraction
c. Both
d. None of these

80. MSD stand for:

a. Most significant digit
b. Many significant digit
c. Both a and b
d. None of these

81. LSD stand for:

a. Less significant digit
b. Least significant digit
c. Loss significant digit
d. None of these

82. Which system has a base or radix of 10:

a. Binary digit
b. Hexadecimal digit
c. Decimal digit
d. Octal digit
PCI BUS-1

This set of Computer Organization and Architecture Multiple Choice Questions & Answers
(MCQs) focuses on “PCI BUS-1”.

1. The PCI follows a set of standards primarily used in _____ PC’s.

a) Intel
b) Motorola
c) IBM
d) SUN

Answer: c
Explanation: The PCI BUS has a closer resemblance to IBM architecture.

2. The ______ is the BUS used in Macintosh PC’s.

a) NuBUS
b) EISA
c) PCI
d) None of the mentioned

Answer: a
Explanation: The NuBUS is an extension of the processor BUS in Macintosh PC’s.

3. The key feature of the PCI BUS is _________

a) Low cost connectivity
b) Plug and Play capability
c) Expansion of Bandwidth
d) None of the mentioned

Answer: b
Explanation: The PCI BUS was the first to introduce plug and play interface for I/O devices.

4. PCI stands for _______

a) Peripheral Component Interconnect
b) Peripheral Computer Internet
c) Processor Computer Interconnect
d) Processor Cable Interconnect

Answer: a
Explanation: The PCI BUS is used as an extension for the processor BUS.
5. The PCI BUS supports _____ address space/s.
a) I/O
b) Memory
c) Configuration
d) All of the mentioned

Answer: d
Explanation: The PCI BUS is mainly built to provide a wide range of connectivity for devices.
6. ______ address space gives the PCI its plug and plays capability.
a) Configuration
b) I/O
c) Memory
d) All of the mentioned

Answer: a
Explanation: The configuration address space is used to store the details of the connected device.

7. _____ provides a separate physical connection to the memory.

a) PCI BUS
b) PCI interface
c) PCI bridge
d) Switch circuit

Answer: c
Explanation: The PCI bridge is a circuit that acts as a bridge between the BUS and the memory.

8. When transferring data over the PCI BUS, the master as to hold the address until the completion
of the transfer to the slave.
a) True
b) False

Answer: b
Explanation: The address is stored by the slave in a buffer and hence it is not required by the master
to hold it.
9. The master is also called as _____ in PCI terminology.
a) Initiator
b) Commander
c) Chief
d) Starter

Answer: a
Explanation: The Master is also called as an initiator in PCI terminology as it is the one that initiates
a data transfer.
10. Signals whose names end in ____ are asserted in the low voltage state.
a) $
b) #
c) *
d) !

Answer: b
Explanation: None.
Interfacing of memory and I/O:
1. The operation,IOW# performs
A. write operation on input data
B. write operation on output data
C. read operation on input data
D. read operation on output data
Answer: B

2. If a typical static RAM cell require 6 transistors then corresponding dynamic

RAM requires
A. 1 transistor along with capacitance
B. 2 transistors along with resistance
C. 3 transistors along with diode
D. 2 transistors along with capacitance
Answer: A

3. If the size of a memory chip is 512 x 1 bits how many chips are required to
make up 1 K bytes of memory?
A. 2
B. 8
C. 16
D. 1024
Answer: C

4. If the memory chip size is 1024 x 4-bits how many chips are required to make
4K bytes of memory?
A. 4
B. 8
C. 16
D. 4096
Answer: B
5. The synchronization between microprocessor and memory is done by
A. ALE signal
B. HOLD signal
C. READY signal
D. None of these
Answer: C

6. For the most Static RAM the write pulse width should be at least
A. 10ns B. 60ns C. 300ns D. 1μs
Answer: B

7. SD RAM refers to
A. Synchronous DRAM
B. Static DRAM
C. Semi DRAM
D. Second DRAM
Answer : (A)

8. Acess time is faster for

A.ROM
B. SRAM
C. DRAM
D. EPROM
Answer: B

9. The no. of address lines required to address a memory of size 32 K is

A. 15 lines
B. 16 lines
C. 18 lines
D. 14 lines
Answer: A
Programmable Input – Output 8255:
1.All the functions of the ports of 8255 are achieved by programming the bits of an
internal register called
A. data bus control
B. read logic control
C. control word register
D. none
Answer: C

2.When the 82C55 is reset, its I/O ports are all initializes as
(A) output port using mode 0
(B) Input port using mode 1
(C) output port using mode 1
(D) Input port using mode 0
Answer: D

3.In 8255A __________ is used for input operation

A. mode 0
B. mode2
C. mode 3
D. mode1
Answer: A

4.In 8255A _________ is used for handshaking operation

A. mode 0
B. mode1
C. mode 2
D. mode3
Answer: B

5.In 8255 A ___________ is used to perform bidirectional operation

A. mode 0
B. mode1
C. mode 2
D. mode3
Answer: C

6.Data transfer between the microprocessor for peripheral takes place through
A. I/O port
B. input port
C. output port
D. multi port
Answer: A

7.In 8255A, there are _________ I/O lines

A. 24
B. 12
C. 20
D. 10
Answer: A

8.The 8255A is available with ________.

A. 20
B. 40
C. 30
D. 10
Answer: B
9.______ is used to transfer data between microprocessor and I/o process
A. 8255A
B. 8279
C. 8254A
D. 8237A
Answer: A

10. 8255A contains_________ ports each of 8 bit lines

A. 2
B. 4
C. 5
D. 3
Answer: D

11.The _________ input to 8255 is usually activated by Microprocessor in system

A. clear
B. reset
C. ports
D. address bus
Answer: B

12. The input provided by the microprocessor to the read/write control logic is
A. RESET
B. A1
C. WR#
D. All of the above
Answer: D

Multiple Choice Questions on 8086 Microprocessor

1. A microprocessor is a chip integrating all the functions of a CPU of a computer.
A. multiple B. single C. double D. triple
ANSWER: B

2. Microprocessor is a/an circuit that functions as the CPU of the compute

A. electronic B. mechanic C. integrating D. processing
ANSWER: A

3. Microprocessor is the of the computer and it perform all the computational tasks
A. main B. heart C. important D. simple
ANSWER: B

4. The purpose of the microprocessor is to control

A. memory B. switches C. processing D. tasks
ANSWER: A
5. The first digital electronic computer was built in the year
A. 1950 B. 1960 C. 1940 D. 1930
ANSWER: C

6. In 1960's texas institute invented

A. integrated circuits B. microprocessor C. vacuum tubes D. transistors
ANSWER: A

7. The intel 8086 microprocessor is a processor

A. 8 bit B. 16 bit C. 32 bit D. 4 bit
ANSWER: B

8. The microprocessor can read/write 16 bit data from or to

A. memory B. I /O device C. processor D. register
ANSWER: A
9. In 8086 microprocessor , the address bus is bit wide
A. 12 bit B. 10 bit C. 16 bit D. 20 bit
ANSWER: D

11. The 16 bit flag of 8086 microprocessor is responsible to indicate

A. the condition of result of ALU operation B. the condition of memory
C. the result of addition D. the result of subtraction
ANSWER: A

12. The CF is known as

A. carry flag B. condition flag C. common flag D. single flag
.ANSWER: A
13. The SF is called as
A. service flag B. sign flag C. single flag D. condition flag
ANSWER: B
14. The OF is called as
A. overflow flag B. overdue flag C. one flag D. over flag
ANSWER: A

1. The pin of minimum mode AD0-AD15 has address

A. 16 bit B. 20 bit C. 32 bit D. 4 bit
ANSWER: B

2. The pin of minimum mode AD0- AD15 has _ data bus

A. 4 bit B. 20 bit C. 16 bit D. 32 bit
ANSWER: C

3. The address bits are sent out on lines through

A. A16-19 B. A0-17 C. D0-D17 D. C0-C17
ANSWER: A

4. is used to write into memory

A. RD B. WR C. RD / WR D. CLK
ANSWER: B

5. The functions of Pins from 24 to 31 depend on the mode in which is operating

A. 8085 B. 8086 C. 80835 D. 80845
ANSWER: B

6. The RD, WR, M/IO is the heart of control for a mode

A. minimum B. maximum C. compatibility mode D. control mode
ANSWER: A

7. In a minimum mode there is a on the system bus

A. single B. double C. multiple D. triple
ANSWER: A

8. If MN/MX is low the 8086 operates in mode

A. Minimum B. Maximum C. both (A) and (B) D. medium
ANSWER: B

9. In max mode, control bus signal So,S1 and S2 are sent out in form
A. decoded B. encoded C. shared D. unshared
ANSWER: B

10. The bus controller device decodes the signals to produce the control bus signal
A. internal B. data C. external D. address
ANSWER: C

11. A Instruction at the end of interrupt service program takes the execution back to the
interrupted program
A. forward B. return C. data D. line
ANSWER: B
 12. The main concerns of the are to define a flexible set of commands
A. memory interface B. peripheral interface
C. both (A) and (B) D. control interface
.ANSWER: A

13. Primary function of memory interfacing is that the should be able to read from
and write into register
A. multiprocessor B. microprocessor C. dual Processor D. coprocessor
ANSWER: B

14. To perform any operations, the Mp should identify the

A. register B. memory C. interface D. system
ANSWER: A

15. The Microprocessor places address on the address bus

A. 4 bit B. 8 bit C. 16 bit D. 32 bit
ANSWER: C

16. The Microprocessor places 16 bit address on the add lines from that address by
register should be selected
A. address B. one C. two D. three
ANSWER: B

1. The of the memory chip will identify and select the register for the EPROM
A. internal decoder B. external decoder C. address decoder D. data decoder
ANSWER: A

2. Microprocessor provides signal like to indicate the read operatio

A. LOW B. MCMW C. MCMR D. MCMWR
ANSWER: C

3. To interface memory with the microprocessor, connect register the lines of the address bus
must be added to address lines of the chip.
A. single B. memory C. multiple D. triple
ANSWER: B
4.
5. The remaining address line of bus is decoded to generate chip select signal
A. data B. address C. control bus D. both (a) and (b)
ANSWER: B

6. signal is generated by combining RD and WR signals with IO/M

A. control B. memory C. register D. system
ANSWER: A

7. Memory is an integral part of a system

A. supercomputer B. microcomputer
C. mini computer D. mainframe computer
ANSWER: B
 8. has certain signal requirements write into and read from its registers
A. memory B. register C. both (a) and (b) D. control
ANSWER: A

9. An is used to fetch one address

A. internal decoder B. external decoder C. encoder D. register
ANSWER: A

10. The primary function of the is to accept data from I/P devices
A. multiprocessor B. microprocessor C. peripherals D. interfaces
ANSWER: B

11. signal prevent the microprocessor from reading the same data more than one
A. pipelining B. handshaking C. controlling D. signaling
ANSWER: B

12. Bits in IRR interrupt are

A. reset B. set C. stop D. start
ANSWER: B

13. generate interrupt signal to microprocessor and receive acknowledge

A. priority resolver B. control logic
C. interrupt request register D. interrupt register
ANSWER: B

14. The pin is used to select direct command word

A. A0 B. D7-D6 C. A12 D. AD7-AD6
ANSWER: A

15. The is used to connect more microprocessor

A. peripheral device B. cascade C. I/O devices D. control unit
ANSWER: B

16. CS connect the output of

A. encoder B. decoder C. slave program D. buffer
ANSWER: B

17. In which year, 8086 was introduced?

A. 1978 B. 1979 C. 1977 D. 1981
ANSWER: A

17. 8086 and 8088 contains transistors

A. 29000 B. 24000 C. 34000 D. 54000
ANSWER: A

18. ALE stands for

A. address latch enable B. address level enable
C. address leak enable D. address leak extension
ANSWER: A

19. What is DEN?

A. direct enable B. data entered C. data enable D. data encoding
 ANSWER: C

20. In 8086, Example for Non maskable interrupts are .

A. TRAP B. RST6.5 C. INTR D. RST6.6
ANSWER: A

21. In 8086 the overflow flag is set when .

A. the sum is more than 16 bits.
B. signed numbers go out of their range after an arithmetic operation.
C. carry and sign flags are set.
D. subtraction
ANSWER: B

22. In 8086 microprocessor the following has the highest priority among all type interrupts?
A. NMI B. DIV 0 C. TYPE 255 D. OVER FLOW
ANSWER: A

23. In 8086 microprocessor one of the following statements is not true?

A. coprocessor is interfaced in max mode. B. coprocessor is interfaced in min mode.
C. I /O can be interfaced in max / min mode. D. supports pipelining
ANSWER: B

24. Address line for TRAP is?

A. 0023H B. 0024H C. 0033H D. 0099H
ANSWER: B

25. Access time is faster for .

A. ROM B. SRAM C. DRAM D. ERAM
ANSWER: B

26. Which method bypasses the CPU for certain types of data transfer?
A. Software interrupts B. Interrupt-driven I/O
C. Polled I/O D. Direct memory access (DMA)
Ans.: D

27. Which bus is bidirectional?

A. Address bus B. Control bus
C. Data bus D. None of the above
Ans.: C

28. The first microprocessor had a(n) .

A. 1 – bit data bus B. 2 – bit data bus
C. 4 – bit data bus D. 8 – bit data bus
Ans.: C

29. Which microprocessor has multiplexed data and address lines?

A. 8086 B. 80286 C. 80386 D. Pentium
Ans.: A

30. Which is not an operand?

A. Variable B. Register C. Memory location D. Assembler
 Ans.: D

31. Which is not part of the execution unit (EU)?

A. Arithmetic logic unit (ALU) B. Clock
C. General registers D. Flags
Ans.: B

32. A 20-bit address bus can locate .

A. 1,048,576 locations B. 2,097,152 locations
C. 4,194,304 locations D. 8,388,608 locations
Ans.: A

33. Which of the following is not an arithmetic instruction?

A. INC (increment) B. CMP (compare)
C. DEC (decrement) D. ROL (rotate left)
Ans.: D

34. During a read operation the CPU fetches _.

A. a program instruction B. another address
C. data itself D. all of the above
Ans.: D

35. Which of the following is not an 8086/8088 general-purpose register?

A. Code segment (CS) B. Data segment (DS)
C. Stack segment (SS) D. Address segment (AS)
Ans.: D

36. A 20-bit address bus allows access to a memory of capacity

A. 1 MB B. 2 MB C. 4 MB D. 8 MB
Ans.: A

37. Which microprocessor accepts the program written for 8086 without any changes?
A. 8085 B. 8086 C. 8087 D. 8088
Ans.: D

38. Which group of instructions do not affect the flags?

A. Arithmetic operations B. Logic operations
C. Data transfer operations D. Branch operations
Ans.: C
39. The First Microprocessor was .
A. Intel 4004 B. 8080 C. 8085 D. 4008
ANSWER: A
40. Status register is also called as .
A. accumulator B. stack C. counter D. flags
ANSWER: D
41. Which of the following is not a basic element within the microprocessor?
A. Microcontroller B. Arithmetic logic unit (ALU)
C. Register array D. Control unit
Ans.: A