COA-MCQ 1 KNREDDY

Computer System Architecture MCQ 01 8. Which are the operation that a computer
performs on data that put in register:
a. Register transfer b. Arithmetic
1. Which operations are used for addition, c. Logical d. All of these
subtraction, increment, decrement and complement
function:
a. Bus 9. In memory transfer location address is
b. Memory transfer supplied by that puts this on address bus:
c. Arithmetic operation a. ALU b. CPU
d. All of these c. MAR d. MDR
2. Which language is termed as the symbolic
depiction used for indicating the series: 10. Operation of memory transfer are:
a. Random transfer language a. Read b. Write
b. Register transfer language c. Both d. None
c. Arithmetic transfer language
d. All of these 11. In memory read the operation puts memory
address on to a register known as :
3. The method of writing symbol to indicate a a. PC b. ALU
provided computational process is called as a: c. MAR d. All of these
a. Programming language
b. Random transfer language 12. Which operation puts memory address in
c. Register transfer language memory address register and data in DR:
d. Arithmetic transfer language a. Memory read b. Memory write
c. Both d. None
4. In which transfer the computer register are
indicated in capital letters for depicting its function: 13. Arithmetic operation are carried by such micro
a. Memory transfer b. Register transfer operation on stored numeric data available in :
c. Bus transfer d. None of these a. Register b. Data
c. Both d. None
5. The register that includes the address of the
memory unit is termed as the : 14. In arithmetic operation numbers of register and
a. MAR b. PC the circuits for addition at :
c. IR d. None of these a. ALU b. MAR
c. Both d. None
6. The register for the program counter is
signified as : 15. Which operation are implemented using a
a. MAR b. PC binary counter or combinational circuit:
c. IR d. None of these a. Register transfer b. Arithmetic
c. Logical d. All of these
7. In register transfer the instruction register as:
a. MAR b. PC 16. Which operation is binary type, and are
c. IR d. None of these performed on bits string that is placed in register:
a. Logical micro operation
b. Arithmetic micro operation
c. Both
d. None

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33. In organization of a digital system register transfer of any digital system therefore it is called:
a. Digital system b. Register
c. Data d. Register transfer level

34. The binary information of source register chosen by:

a. Demultiplexer b. Multiplexer
c. Both d. None

35. Control transfer passes the function via control :

a. Logic b. Operation
c. Circuit d. All of these

36. The memory bus is also referred as :

a. Data bus b. Address bus
29. In register transfer which system is a c. Memory bus d. All of these
sequential logic system in which flip-flops and
gates are constructed: 40. How many parts of memory bus:
a. Digital system b. Register a. 2 b. 3
c. Data d. None c. 5 d. 6

30. High level language C supports register

transfer technique for application: 41. In every transfer, selection of register by bus is
a. Executing b. Compiling decided by:
c. Both d. None a. Control signal b. No signal
c. All signal d. All of above
31. Which is the straight forward register
transfer the data from register to another register
temporarily:
a. Digital system
b. Register
c. Data
d. Register transfer operations

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42. Every bit of register has:

a. 2 common line b. 3 common line
c. 1 common line d. none of these

43. DDR2 stands for:

a. Double data rate 2
b. Data double rate 2
c. Dynamic data rate 2
d. Dynamic double rate 2

47. SDRAM stands for: memory c. Both d.

a. System dynamic random access memory None
b. Synchronous dynamic random access

48. Which operation refer bitwise manipulation of

contents of register:
a. Logical micro operation
b. Arithmetic micro operation
c. Shift micro operation
d. None of these

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Computer System Architecture MCQ 02

1. is a command given to a computer to perform a specified operation on some given data:

a. An instruction b. Command
c. Code d. None of these

2. An instruction is guided by to perform work according:

a. PC b. ALU c. Both a and b d. CPU

3. Two important fields of an instruction are:

a. Opcode b. Operand
c. Only a d. Both a & b

4. Each operation has its opcode:

a. Unique b. Two
c. Three d. Four

5. which are of these examples of Intel 8086 opcodes:

a. MOV b. ADD c. SUB

d. All of these

6. specify where to get the source and destination operands for the operation specified by the
:
a. Operand fields and opcode
b. Opcode and operand
c. Source and destination
d. CPU and memory

7. The source/destination of operands can be the or one of the general-purpose register:

a. Memory b. One
c. both d. None of these

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11. is the sequence of operations performed by CPU in processing an instruction:

a. Execute cycle
b. Fetch cycle
c. Decode
d. Instruction cycle

12. The time required to complete one instruction is called:

a. Fetch time
b. Execution time
c. Control time
d. All of these

13. is the step during which a new instruction is read from the memory:
a. Decode
b. Fetch
c. Execute
d. None of these

14. is the step during which the operations specified by the instruction are executed:
a. Execute
b. Decode
c. Both a& b
d. None of these

15.Decode is the step during which instruction is :

microprocessor defines the set for that a. Initialized
processor: b. Incremented
a. Code b. Function
c. Module d. Instruction

9. Which is the method by which instructions are selected for execution:

a. Instruction selection
b. Selection control
c. Instruction sequencing
d. All of these

10. The simplest method of controlling sequence of instruction execution is to have

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c. Decoded
d. Both b & c

17. The instruction fetch operation is initiated by loading the contents of program counter into the and
sends request to memory:
a. Memory register and read
b. Memory register and write
c. Data register and read
d. Address register and read

18. The contents of the program counter is the

each instruction explicitly specify: of the instruction to be run:
a. The address of next instruction to be run
b. Address of previous instruction
c. Both a & b
d. None of these

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a. Data
b. Address
c. Counter
d. None of these

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27.

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are the codes that represent alphabetic characters, punctuation marks and other special
characters:
a. Alphanumeric codes
b. ASCII codes
c. EBCDIC codes
d. All of these

28. Abbreviation ASCII stands for:

a. American standard code for information interchange
b. Abbreviation standard code for information interchange
c. Both
d. None of these

21. is a symbolic representation of 29. How many bit of ASCII code:

discrete elements of information:
a. Data
b. Code
c. Address
d. Control

22. Group of binary bits(0&1) is known as:

a. Binary code
b. Digit code
c. Symbolic representation
d. None of these

23. A group of 4 binary bits is called:

a. Nibble
b. Byte
c. Decimal
d. Digit

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a. 6
b. 7
c. 5
d. 8
a

25. The are assigned according to

the position occupied by digits:
a. Volume
b. Weight
c. Mass
d. All of these

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33. Which is the method of parity:

a. Even parity method
b. Odd parity method
c. Both
d. None of these

34. A code that is used to correct error is called an

:
a. Error detecting code
b. Error correcting code
c. Both
d. None of these

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59. Which unit provide status , timing and control

signal:
a. Timing and control unit
b. Memory unit
c. Chace unit
d. None of these

60. Which unit acts as the brain of the computer

52. Which are designed to interpret a specified which control other peripherals and interfaces:
number of instruction code: a. Memory unit
a. Programmer b. Cache unit
b. Processors c. Timing and control unit
c. Instruction d. None of these
d. Opcode

53. Which code is a string of binary digits: 61. Which unit works as an interface between the
a. Op code processor and all the memories on chip or off- chip:
b. Instruction code a. Timing unit
c. Parity code b. Control unit
d. Operand code c. Memory control unit
d. All of these
54. The list of specific instruction supported by the
CPU is termed as its : 62. The maximum clock frequency is :
a. Instruction code a. 45 MHZ
b. Parity set
b. 50 MHZ
c. Instruction set c. 52 MHZ
d. None of these d. 68 MHZ
55. is divided into a number of fields
63. is given an instruction in machine
and is represented as a sequence of bits:
language this instruction is fetched from the
a. instruction
memory by the CPU to execute:
b. instruction set
a. ALU
c. instruction code
b. CPU
d. parity code
c. MU
d. All of these
56. Which unit is necessary for the execution
of instruction:
64. Which cycle refers to the time period during
which one instruction is fetched and executed by
the CPU:
a. Fetch cycle
b. Instruction cycle
c. Decode cycle
d. Execute cycle
a. Timing 66. How many stages of instruction cycle:
b. Control a. 5
c. Both b. 6
d. None of these c. 4
d. 7

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67. Which are stages of instruction cycle:

a. Fetch b. Decode 71. IRET stand for:
c. Execute a. Interrupt enter
d. Derive effective address of the instruction b. Interrupt return
e. All of these c. Interrupt delete
d. None of these

72. Which are benefit of input/output interrupt:

a. It is an external analogy to exceptions
b. The processor initiates and perform all I/O
operation
68. is an external hardware event c. The data is transferred into the memory
which causes the CPU to interrupt the current through interrupt handler
instruction sequence: d. All of these
a. Input interrupt b. Output interrupt
c. Both d. None of these
73. Which are the causes of the interrupt:
69. ISR stand for: a. In any single device
a. Interrupt save routine b. In processor poll devices
b. Interrupt service routine c. In a device whose ID number is stored on the
c. Input stages routine address bus d. All of these
d. All of these
70. Which interrupt services save all the register 74. Which are the functioning of I/O interrupt:
and flags: a. The processor organizes all the I/O operation
a. Save interrupt for smooth functioning
b. Input/output interrupt b. After completing the I/O operation the device
c. Service interrupt interrupt the processor
d. All of these c. Both d. None of these
75. with which computers perform is
way beyond human capabilities:
a. Speed b. Accuracy
c. Storage d. Versatility

76. of a computer is consistently:

a. Speed b. Accuracy
c. Storage d. Versatility

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77. of information in a human 90. How many major component make up the
brain and a computer happens differently: CPU:
a. Intelligence b. Storage a. 4 b. 3 c.6 d. 8
c. Versatility d. Diligence
91. Which register holds the current
78. Which are the basic operation for computing: instruction to be executed:
a.
c. Inputting b. Storing Processing a. Instruction register
d. Outputting
Controlling e. b. Program register
f. All of these c. Control register
d. None of these
79. The control unit and arithmetic logic unit are 92. Which register holds the address of next
know as the : instruction to be executed:
a. Central program unit b. CPU a. Instruction register
c. Central primary unit d. None b. Program register
c. Program control register
80. Which unit is comparable to the central d. None of these
nervous system in the human body:
a. Output unit b. Control unit 93. Each instruction is also accompanied by
c. Input unit d. All of these a :
a. Microprocessor
81. of the primary memory of the b. Microcode
computer is limited: c. Both
a. Storage capacity b. Magnetic disk d. None of these
c. Both d. None of these
94. Which are microcomputers commonly
82. Information is handled in the computer by used for commercial data processing, desktop
: publishing and engineering application:
a. Electrical digit b. Electrical component a. Digital computer
c. Electronic bit d. None of these b. Personal computer
c. Both
83. 0 and 1 are know as : d. None of these
a. Byte b. Bit c. Digits d. Component
95. Which microprocessor has the control
84. 0 and 1 abbreviation for: unit, memory unit and arithmetic and logic unit:
a. Binary digit b. Octal digit a. Pentium IV processor
c. Both d. None of these b. Pentium V processor
c. Pentium III processor
85. How many bit of nibble group: d. None of these
a. 5 b. 4 c. 7 d. 8
96. The processing speed of a computer
86. How many bit of bytes: depends on the of the system:
a. 3 b. 4 c. 6 d. 8 a. Clock speed
b. Motorola
87. Which is the most important component of a c. Cyrix
digit computer that interprets the instruction and d. None of these
processes the data contained in computer programs:
a. MU b. ALU c. CPU d. PC 97. Which microprocessor is available with
a clock speed of 1.6 GHZ:
88. Which part work as a the brain of the computer a. Pentium III b. Pentium II
and performs most of the calculation: c. Pentium IV d. All of these
a. MU b. PC c. ALU d. CPU
98. Which processor are used in the most
89. Which is the main function of the computer: personal computer:
a. Execute of programs a. Intel corporation’s Pentium
b. Execution of programs b. Motorola corporation’s
c. Both c. Both
d. None of these d. None of these

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Computer System Architecture MCQ 03 9. By whom address of external function in the

assembly source file supplied by when
1. is the first step in the evolution of activated:
programming languages: a. Assembler
a. machine language b. Linker
b. assembly language c. Machine
c. code language d. Code
d. none of these
10. An -o option is used for:
2. Mnemonic refers to: a. Input file
a. Instructions b. External file
b. Code c. Output file
c. Symbolic codes d. None of these
d. Assembler

3. Mnemonic represent:
a. Operation codes
b. Strings
c. Address
d. None of these

4. To represent addresses in assembly language

we use:
a. String characters
b. Arrays
c. Structure
d. Enum

5. Assembler works to convert assembly

language program into machine language :
a. Before the computer can execute it
b. After the computer can execute it
c. In between execution
d. All of these

6. generation computers use assembly

language:
a. First generation
b. Third generation
c. second generation
d. fourth generation

7. Assembly language program is called:

a. Object program
b. Source program
c. Oriented program
d. All of these

8. To invoke assembler following command are

given at command line:
a. $ hello.s -o hello.o
b. $as hello.s –o o
c. $ as hello –o hello.o
d. $ as hello.s –o hello.o

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13. which type of errors are detected by the 26. Assembler is a :

assembler: a. Interpreter
a. syntax error b. Translator
b. logical error c. Exchanger
c. run time error d. None of these
d. none of these
27. A processor controls repetitious

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30. address is provided by linker to

modules linked together that starting from : 41. which of the following are types of assembler
entities:
a. Absolute and 0
b. Relative and 0 a. Absolute entities
c. Relative and 1 b. Relative entities
d. Relative and 3 c. Object program
d. All of these
31. A linker is also known as:
42. have addresses where instructions are
a. Binder stored along with address of working storage:
b. Linkage editor
c. Both a & b a. Relative entities
d. None of these b. Absolute entities
c. Both a & b
32. Loading is with the task of storage d. None of these
management of operating system and
mostly preformed after assembly: 43. Absolute entities are whom value
signify storage locations that are independent of
a. Bound resulting machine code:
b. Expanded a. Numeric constants
c. Overlaps b. String constants
d. All of these c. Fixed addresses
d. Operation codes
33. contain library program have to be e. All of these
indicated to the loader: 44. A module contains machine code with
specification on :
a. Externally defined a. Relative addresses
b. Internally defined b. Absolute addresses
c. Executable file c. Object program
d. All of these d. None of these

34. It is the task of the to locate 45. After actual locations for main storage are
externally defined symbols in programs, load them known, a adjusts relative addresses to these
in to memory by placing their of symbols actual locations:
in calling program: a. Relocating loader
b. Locating loader
a. Loader and name c. Default loader
b. Linker and values d. None of these
c. Linker and name
d. Loader and values 46. If there is a module from single source-
language only that does not contain any external
35. Linker creates a link file containing binary references, it doesn’t need a linker to load it and is
codes and also produces containing loaded :
address information on linked files:
a. Indirectly
a. Link map b. Directly
b. Map table c. Extending
c. Symbol map d. None of these
d. None of these
47. Modern assemblers for RISC based
40. how many types of entities contained by architectures make optimization of instruction
assembler to handle program: scheduling to make use of CPU efficiently:
a. 4 a. Pipeline
b. 2 b. Without pipeline
c. 3 c. Both a & b
d. 5 d. None of these

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48. which are of the following modern assemblers: 56. SPARC stands for:
a. MIPS a. Scalable programmer architecture
b. Sun SPARC b. Scalable processor architecture
c. HP PA-RISC c. Scalable point architecture
d. x86(x64) d. None of these
e. all of these 57. Full form of MIPS assembler is:
49. How many types of loop control structures in C a. Microprocessor without interlocked
language: pipeline stage
b. Microprocessor with interlocked pipeline
a. 4 stage
b. 5 c. Both a & b
c. 2 d. None of these
d. 3 58. statement block is executed atleast
once for any value of the condition:
50. Types of loop control statements are: a. For statement
b. Do-while statement
a. For loop c. While statement
b. While loop d. None of these
c. Do-while loop
d. All of these 59. statement is an unconditional
transfer of control statement:
51. <Initial value> is which initializes the a. Goto
value of variable: b. Continue
c. Switch
a. Assignment expression d. All of these
b. Condition value
c. Increment/decrement 60. In Goto statement the place to which control is
d. None of these transferred is identified by a statement :
a. Label
52. The format “%8d” is used to print b. Display
values in a line: c. Break
a. 11 d. None of these
b. 10
c. 9 61. The continue statement is used to transfer the
d. 12 control to the of a statement block in a
loop:
53. <Condition> is a expression which a. End
will have value true or false: b. Beginning
a. Relational c. Middle
b. Logical d. None of these
c. Both a & b
d. None of these 62. The statement is used to transfer
the control to the end of statement block in a loop:
54. <Increment> is the value of variable
which will be added every time: a. Continue
a. Increment b. Break
b. Decrement c. Switch
c. Expanding d. Goto
d. None of these
63. function is used to transfer the
55. is the statement block of for loop lies control to end of a program which uses one
inside block of another for loop: argument( ) and takes value is zero for
a. Nested for loop termination and non-zero for termination:
b. Nested while loop a. Exit( ),normal, abnormal
c. Nested do-while loop b. Break, normal, abnormal
d. None of these c. Both a & b
d. None of these

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64. To design a program it requires : 72. means that one of two alternative
a. Program specification sequences of instruction is chosen based on logical
b. Code specification condition:
c. Instruction specification a. Sequence
d. Problem specification b. Selection
c. Repetition
65. Testing helps to ensure of the program d. None of these
for use within a system:
a. Quality, accuracy and except 73. is sequence of instructions is
b. Quality, accuracy and acceptance executed and repeated any no. of times in loop until
c. Design, assurance and acceptance logical condition is true:
d. Quality, accuracy and development
66. An unstructured program uses a a. Iteration
approach to solve problems: b. Repetition
c. Both a & b
a. Linear d. None of these
b. Top down
c. Both a & b 74. A is a small program tested
d. None of these separately before combining with final program:
67. In a complex program, the overlaps: a. Module
b. Block
a. Branching c. selection
b. Condition d. none of these
c. Both a & b
d. None of these 75. uses various symbols to represent
function within program and is
68. How many structures structured programs are representation:
written:
a. Flowchart, pictorial
a. 3 b. Algorithm, pictorial
b. 2 c. Pictorial, flowchart
c. 1 d. None of these
d. 6
76. Avoid crossing flow lines:
69. following are structured programs written in
simple structures: a. Flowchart
b. Algorithm
a. Sequence c. Both a & b
b. Selection d. None of these
c. Iteration
d. All of these 77. A flow chart is drawn from top to bottom
and :
70. Iteration also called:
a. Right to left
a. Repetition b. Only right
b. Straight c. Left to right
c. Selection d. Only left
d. Sequence
78. Flowchart that exceed page should be
71. In instructions are followed one after properly linked using to portions of
the other in the preset order in which they appear flowchart on different pages:
within program: a. Connectors
a. Sequence b. Interconnections
b. Selection c. Connections
c. Break d. None of these
d. Iteration

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79. is useful to prepare detailed program 86. After compilation of the program ,the
documentation: operating system of computer activates:
a. Flowchart a. Loader
b. Algorithm b. Linker
c. Both a & b c. Compiler
d. None of these d. None of these
80. Pseudo means: 87. The linker has utilities needed for
within the translated program:
a. Imitation
b. Imitate a. Input
c. In imitation b. Output
d. None of these c. Processing
d. All of these
81. Preparing the pseudocode requires
time than drawing flowchart: 88. Flowchart is a representation of an
algorithm:
a. Less
b. More a. Symbolic
c. Optimum b. Diagrammatic
d. None of these c. Both a & b
d. None of these
82. There is standard for preparing
pseudocode instructions: 89. In flow chart symbols the operation
represents the direction of flow:
a. No a. Connector
b. 4 b. Looping
c. 2 c. Arrows
d. 6 d. Decision making
83. are used to translate high level language 90. Which register is memory pointer:
instructions to a machine code: a. Program counter
b. Instruction register
a. Translators c. Stack pointer
b. Interpreters d. Source index
c. Compilers
d. None of these 91. How many approaches are used to design
control unit:
84. The compiler translate a a. 2
program code with any syntax error: b. 3
c. 4
a. Can d. 5
b. Cannot
c. Without 92. Which are the following approaches used to
d. None of these design control unit:
a. Hardwired control
85. Before checking the program for errors in b. Microprogrammed control
translating code into machine language the high c. Both a & b
level language code is loaded into : d. None of these

a. Register 93. Cache memory is located between main

b. Memory memory and :
c. Data a. CPU
d. CPU b. Memory
c. Both a & b
d. None of these

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94. arrow represents the value obtained by 101. A subroutine called by another
evaluating right side expression/variable to the left subroutine is called:
side variable: a. Nested
b. For loop
a. Forth c. Break
b. Inbetween d. Continue
c. Back
d. None of these 102. The extent nesting in subroutine is
limited only by:
95. A is written as separate unit, apart a. Number of available Stack locations
from main and called whenever necessary: b. Number of available Addressing locations
a. Subroutine c. Number of available CPU locations
b. Code d. Number of available Memory locations
c. Block 103. Which are of the following instructions
d. None of these of hardware subroutines:
a. SCAL
96. uses the stack to store return address b. SXIT
of subroutine: c. Both a & b
d. None of these
a. CPU
b. Microprocessor 104. Importance in local variable and index
c. register registers in subroutine does :
d. memory a. Alter
b. Not alter
97. A subroutine is implemented with 2 associated c. Both a & b
instructions: d. None of these
a. CALL 105. Markers in subroutine cannot be
b. RETURN accepted as limits whereas this markers stands for:
c. Both a & b
d. None of these a. Top of stack
b. Bottom of stack
98. Call instruction is written in the c. Middle of stack
program: d. All of these
a. Main 106. Subroutines are placed in identical
b. Procedures section to caller so that SCAL and SXIT
c. Program overpass divison limits:
d. Memory a. Don’t
b. Does
99. Return instruction is written in to c. Cross
written to main program: d. By

a. Subroutine 107. subroutine declaration come

b. Main program after procedure announcement:
c. Both a & b a. Global b. Local
d. None of these c. Both a & b d. None of these

100. When subroutine is called contents of 108. subroutines are invoked by using
program counter is location address of their in a subroutine call statement and
instruction following call instruction is replacing formal parameters with
stored on and program execution is parameters:
transferred to address: a. Identifier and formal
a. Non executable, pointer and subroutine b. Identifier and actual
b. Executable, Stack and Main program c. Expression and arguments
c. Executable, Queue and Subroutine d. None of these
d. Executable, Stack and Subroutine

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109. Parameters can be stacked by 116. In what type of subroutine actual

just as with procedures: parameters are passed through the main program to
formal parameters in the related subroutine:
a. Asterisk(*)
b. Arrow a. Internal
c. Line b. External
d. Pipeline c. Both a & b
d. None of these
110. The subroutines are determined by
functioning of instructions: 117. By defining the register as
last in first out stack the sequence can handle
a. SCAL and SXIT nested subroutines:
b. only SCAL a. S
c. only SXIT b. J
d. none of these c. R
d. T
111. Call is subroutine call:
118. The stack can be 4-word
a. Conditional memory addressed by 2 bits from an up/down
b. Unconditional counter known as the stack pointer:
c. Both a & b a. FIFO
d. None of these b. PIPO
c. SISO
112. A flag is a that keep track of a d. LIFO
changing condition during computer run:
119. getchar :: IO char in this given function
a. Memory what is indicated by IO char:
b. Register a. when getchar is invoked it returns a
c. Controller character
d. None of these b. when getchar is executed it returns a character
c. both a & b
113. When a subroutine is the d. none of these
parameters are loaded onto the stack and SCAL is
executed: 120. If we define putchar function in putchar
:: char -> IO ( ) syntax than character input as an
a. Executed argument and returns :
b. Invoked a. Useful value
c. Ended b. Get output
d. Started c. Get no output
d. None of these
114. Subroutine is called :
121. The front panel display provides lights as
a. In Same program green LED represent and red LED represent
b. In external program for device programmer who writes
c. Both a & b input/output basic:
d. None of these a. Busy and Error
b. Error and Busy
115. If internal subroutine is called global c. Busy and Busy
data is used to pass values defining parameters d. Error and Error
between program and defined :
122. The input data for processing uses the
a. Main and subroutine standard input device which by default is a
b. Local and subroutine :
c. Global and subroutine a. Mouse
d. Global and main b. Scanner
c. Keyboard
d. Monitor

COMPUTER ORGANIZATION AND ARCHITECTURE

COA-MCQ 24 KNREDDY

123. The processed data is sent for output to 130. program converts machine
standard device which by default is instructions into control signals:
computer screen: a. Control memory program
b. Control store program
a. Input c. Both a & b
b. Output d. Only memory
c. Both a & b 131. who coined the term micro program in
d. None of these 1951:

124. Each instruction is executed by set of a. T.V. Wilkes

micro operations termed as: b. M.V. Wilkes
c. S.V. Wilkes
a. Micro instructions d. D.V. Wilkes
b. Mini instructions
c. Both a & b 132. what is full form of EDSAC:
d. None of these a. Electronic delay source accumulator
calculator
125. For each micro operation the control unit b. Electronic delay storage automatic code
generates set of signals: c. Electronic destination source automatic
calculator
a. Control d. Electronic delay storage automatic
b. Address calculator
c. Data 133. Who led to development of read –only
d. None of these magnetic core matrix for use in control unit of
small computer at IBM’s laboratory:
126. Sequence of microinstructions is termed
as micro program or : a. John Fairclough’s
b. Johny fairclough
a. Hardware c. Mr. Redcliff
b. Software d. M.V. Wilkes
c. Firmware
d. None of these 134. From1961-1964 John fairclough’s
research played an important role to pursue full
127. The micro program is an range of compatible computers as system:
written in microcode and stored in
firmware which is also referred as : a. System/360
a. Interpreter and control memory b. System/460
b. Translator and control store c. System/560
c. Translator and control memory d. System/780
d. Interpreter and Translator
128. Compared to hardware, firmware is 135. Each microinstructions cycle is made
to design micro programmed of 2 parts:
organization:
a. Fetch
a. Difficult b. Execute
b. Easier c. Code
c. Both a& b d. Both a & b
d. None of these
136. One of use of microprogramming to
129. Compared to software, firmware is implement of processor in Intel 80x86
to write: and Motorola 680x0 processors whose instruction
set are evolved from 360 original:
a. Easier a. Control structure
b. Difficult b. Without control
c. Mediator c. Control unit
d. Optimum d. Only control

COMPUTER ORGANIZATION AND ARCHITECTURE

COA-MCQ 25 KNREDDY

137. The function of these microinstructions 145. A computer having writable control
is to issue the micro orders to : memory is known as :
a. CPU a. Static micro programmable
b. Memory b. Dynamic micro programmable
c. Register c. Both a & b
d. Accumulator d. None of these
146. The control memory contains a set of
138. Micro-orders generate the words where each word is:
address of operand and execute instruction and
prepare for fetching next instruction from the main a. Microinstruction
memory: b. Program
a. Physical c. Sets
b. Effective d. All of these
c. Logical
d. all of above 147. During program execution content of
main memory undergo changes and, but control
139. Which of the following 2 task are memory has microprogram:
performed to execute an instruction by MCU:
a. Microinstruction execution a. Static
b. Microinstruction sequencing b. Dynamic
c. Both a & b d. None of these c. Compile time
d. Fixed
140. What is the purpose of microinstruction
executions: 148. What happens if computer is started :
a. Generate a control signal a. It executes “CPU” microprogram which is
b. Generate a control signal to compile sequence of microinstructions stored in ROM
c. Generate a control signal to execute b. It executes “code” microprogram which is
d. All of these sequence of microinstructions stored in ROM
c. It executes “boot” microprogram which is
141. Which microinstruction provide next sequence of microinstructions stored in ROM
instruction from control memory: d. It executes “strap loader” microprogram
a. Microinstruction execution which is sequence of microinstructions stored in
b. Microinstruction Buffer ROM
c. Microinstruction decoder
d. Microinstruction Sequencing 149. Control memory is part of that
has addressable storage registers and used as
142. Which are the following components of temporary storage for data:
microprogramed units to implement control
process: a. ROM
a. Instruction register b. RAM
b. Microinstruction address generation c. CPU
c. Control store microprogram memory d. Memory
d. Microinstruction Buffer
e. Microinstruction decoder 150. How many modes the address in control
f. All of these memory are divided:
143. Microcodes are stored as firmware in a. 2
: b. 3
a. Memory chips b. Registers c. 5
c. accumulators d. none of these d. 7
144. A control memory is stored in 151. which of the following is interrupt mode:
some area of memory:
a. Control instruction a. Task mode
b. Memory instruction b. Executive mode
c. Register instruction c. Both a & b
d. None of these d. None of these

COMPUTER ORGANIZATION AND ARCHITECTURE

COA-MCQ 26 KNREDDY

152. Mode of addresses in control memory 160. On what method search in cache
are: memory used by the system:
a. Executive mode
b. Task mode a. Cache directing
c. Both a & b b. Cache mapping
d. None of these c. Cache controlling
d. Cache invalidation
153. Addresses in control memory is made
by for each register group: 161. process starts when a cpu with
a. Address select logic cache refers to a memory:
b. Data select logic
c. Control select logic a. Main memory
d. All of these b. External memory
c. Cache
154. There are how many register groups in d. All of these
control memory:
a. 3 162. When cache process starts hit and miss
b. 5 rate defines in cache directory:
c. 6
d. 8 a. during search reads
b. during search writes
155. What type of circuit is used by control c. during replace writes
memory to interconnect registers: d. during finding writes
a. Data routing circuit
b. Address routing circuit 163. In cache memory hit rate indicates:
c. Control routing circuit a. Data from requested address is not available
d. None of the these b. Data from requested address is available
c. Control from requested address is available
156. Which memory is used to copy d. Address from requested address is not
instructions or data currently used by CPU: available

a. Main memory 164. In cache memory miss rate indicates:

b. Secondary memory a. Availability of requested data
c. Cache memory b. Availability of requested address
d. None of these c. Non-Availability of requested data
d. Non-Availability of requested address
157. Copy of instruction in cache memory is
known as: 165. Which 3 areas are used by cache process:
a. Search, updating, invalidation
a. Execution cache b. Write, updating, invalidation
b. Data cache c. Search, read, updating
c. Instruction cache d. Invalidation, updating, requesting
d. All of these 166. Updating writes to cache data and also to
:
158. Copy of data in cache memory is called:
a. Data cache a. Directories
b. Execution cache b. Memory
c. Address cache c. Registers
d. Control cache d. Folders

159. What are 2 advantages of cache memory: 167. Invalidation writes only to and
a. Reduction of average access time for CPU erases previously residing address in memory:
memory a. Folders
b. Reduction of bandwidth of available memory b. Memory
of CPU c. Directory
c. Both a & b d. Files
d. None of these

COMPUTER ORGANIZATION AND ARCHITECTURE

COA-MCQ 27 KNREDDY

168. machine instruction creates 176. Control ROM is the control memory that
branching to some specified location in main holds:
memory if result of last ALU operation is Zero or
Zero flag is set: a. Control words
a. Branch on One b. Memory words
b. Branch on Three c. Multiplexers
c. Branch on Nine d. Decoders
d. Branch on Zero
177. Opcode is the machine instruction
169. Full form of CAR: obtained from decoding instruction stored in:
a. Control address register
b. Content address register a. Stack pointer
c. Condition accumulator resource b. Address pointer
d. Code address register c. Instruction register
d. Incrementer
170. Two types of microinstructions are:
a. Branching 178. Branch logic determines which should be
b. Non-branching adopted to select the next value among
c. Both a & b possibilities:
d. None of these a. CAR
b. GAR
171. Which are 3 ways to determine address c. HAR
of next micro instruction to be executed: d. TAR
a. Next sequential address
b. Branching 179. generates CAR+1 as
c. Interrupt testing possibility of next CAR value:
d. All of these a. Decrementer
b. Incrementer
172. Branching can be : c. Postfix
a. Conditional d. Prefix
b. Unconditional
c. Both a & b 180. used to hold return address for
d. None of these operations of subroutine call branch:
a. TBR
173. In which branching condition is tested b. HDR
which is determined by status bit of ALU: c. SDR
a. Unconditional d. SBR
b. Conditional
c. Both a & b 181. Which of following 2 types of computer
d. None of these system considered by micro programmed unit:
a. Micro level computers
174. which branch is achieved by fixing b. Machine level computers
status bit that output of multiplexer is always one: c. Both a & b
a. Unconditional d. None of these
b. Conditional
c. Looping 182. Following are the components of micro
d. All of these programmed control unit:
a. Subroutine register
175. Which register is used to store addresses b. Control address register
of control memory from where instruction is c. Memory Of 128 words with 20 bits per words
fetched: d. All of these
a. MAR
b. BAR 183. Various machine level components are:
c. CAR a. Address register b. Program counter
d. DAR c. Data register d. Accumulator register
e. Memory of 2K,16 bits/word RAM
f. Multiplexers g. All of these

COMPUTER ORGANIZATION AND ARCHITECTURE

COA-MCQ 28 KNREDDY

184. Data transfers are done using: 193. If flag is set then control unit
a. Multiplexer switching issues control signals that causes program counter
b. Demultiplexer switching to be incremented by 1:
c. Adder switching
d. Subtractor switching a. Zero
b. One
185. PC can be loaded from : c. Three
a. BR d. Eight
b. CR
c. AR 194. Which control unit is implemented as
d. TR combinational circuit in the hardware:
a. Microprogrammed control unit
186. Which functions are performed by CU: b. Hardwired control unit
a. Data exchange b/w CPU and memory or I/O c. Blockprogrammed control unit
modules d. Macroprogrammed control unit
b. External operations 195. Microprograms are usually stored in:
c. Internal operations inside CPU a. ROM
d. Both a & c b. RAM
c. SAM
187. Which are internal operations inside d. SAN
CPU:
a. Data transfer b/w registers 196. Among them which is the faster control
b. Instructing ALU to operate data unit:
c. Regulation of other internal operations a. Hardwired
d. All of these b. Microprogrammed
c. Both a & b
188. How many paths taken by movement of d. None of these
data in CU:
a. 3 197. For CISC architecture
b. 4 controllers are better:
c. 5 a. Microprogrammed
d. 2 b. Hardwired
c. Betterwired
189. 2 data paths in CU are: d. None of these
a. Internal data paths
b. External data paths 198. Full form of FSM is:
c. Both a & b a. Finite state machine
d. None of these b. Fix state machine
c. Fun source metal
190. is the data paths link CPU d. All of these
registers with memory or I/O modules:
a. External data paths 199. Rules of FSM are encoded in:
b. Internal data paths a. ROM
c. Boreal data paths b. Random logic
d. Exchange data paths c. Programmable logic array
d. All of these
191. is data paths there is movement
of data from one register to another or b/w ALU 200. In RISC architecture access to registers
and a register: is made as a block and register file in a particular
a. External b. Boreal register can be selected by using:
c. Internal d. Exchange a. Multiplexer
b. Decoder
192. Which is the input of control unit: c. Subtractor
a. Master clock signal d. Adder
b. Instruction register c. Flags
d. Control signals from bus
e. All of these

COMPUTER ORGANIZATION AND ARCHITECTURE

COA-MCQ 29 KNREDDY

201. Outputs of instruction/data path in CU 212. dependence over op-code in C:

are: a. Load register
a. Reg R/W b. Load/Reg-Reg b. Load Reg/Reg
c. ALU function select d. Load control c. Only Load
e. Read control f. IR Latch d. None of these
g. JUMP/Branch/Next PC h. All of these
213. Full form of PLA in CU:
202. One last bit of control output is for a. Progrmmable Logic Array
control of state: b. Programs Load Array
a. Minor b. Major c. Programmable Logic Accumulator
c. Mixer d. None of these d. all of these

203. Following are 4 major states for ‘load’ 214. Which are tasks for execution of CU or
are: MCU:
a. Fetch b. Decode c. Memory a. Microinstruction execution
d. Write back e. All of these b. Microinstruction sequencing
c. Both a & b d. None of these
204. Jump has 3 major states are:
a. Fetch b.Decode c.Completed.All of these 215. Branching is implemented by depending
on output of:
205. state keeps track of position a. CD b. RG c. CC d. CR
related to execution of an instruction:
a. Major b. Minor c. Both a & b 216. Who determine under what conditions
d. None of these the branching will occur and when:
a. By combination of CD and BT
206. An instruction always starts with b. By combination of CD and BR
state : c. By combination of CD and CR
d. By combination of TD and BR
a. 1 b. 2 c. 3 d. 0
217. The character U is used to indicate:
207. Decoding of an instruction in RISC a. Undefined transfers
architecture means decision on working of control b. Unfair transfers
unit for: c. Unconditional transfers
a. Remainder of instructions d. All of these
b. Divisor of instructions
c. Dividend of instructions d. None 218. Which field is used to requests for
branching:
208. Which control is used during starting of a. DR b. CR
instruction cycle: c. TR d. BR
a. Write b. Read c. R/W
d. None of these 219. which field is used to determine what
type of transfer occurs:
209. function select takes op code in a. CR b. SR
IR translating to function of ALU and it may be c. BR d. MR
compact binary code or one line per ALU:
a. ALU b. CPU c.Memory d. Cache 220. Source statements consist of 5fields in
microinstruction source code are:
210. is dependent on instruction a. Lable
type in CU: b. Micro-ops
a. Jump b. Branch c. CD-spec
c. NextPC d. All of these d. BR-spec
e. Address
211. dependent on instruction and f. All of these
major state and also comes in starting of data fetch
state as well as write back stage in CU:
a. Register read b. Register write
c. Register R/W d. All of these

COMPUTER ORGANIZATION AND ARCHITECTURE

COA-MCQ 30 KNREDDY

Computer System Architecture MCQ 04

1. Which is a type of microprocessor that is
designed with limited number of instructions: 9. How many source register propagate through
a. CPU the multiplexers:
b. RISC
c. ALU
d. MUX a. 1
b. 2
2. Which unit is a pipeline system helps in c. 3
speeding up processing over a non pipeline system: d. 4
a. CPU
b. RISC
c. ALU 10. How many bits of OPR select one of the
d. MUX operations in the ALU:
3. The group of binary bits assigned to perform
a specified operation is known as: a. 2
a. Stack register b. 3
b. Control word c. 4
c. Both d. 5
d. None

4. How many binary selection inputs in the 11. five bits of OPR select one of the operation in
control word: the in control register:
a. 1
b. 7
c. 14 a. CPU
d. 28 b. RISC
c. ALU
d. MUX
5. In control word three fields contain how many
bits:
a. 1 12. The OPR field has how many bits:
b. 2
c. 3
d. 4 a. 2
b. 3
c. 4
6. Three fields contains three bits each so one d. 5
filed has how many bits in control word:
a. 2
b. 4 13. In stack organization the insertion operation is
c. 5 known as :
d. 6
a. Pop
7. How is selects the register that receives the b. Push
information from the output bus: c. Both
a. Decoder d. None
b. Encoder
c. MUX
d. All of these 14. In stack organization the deletion operation is
known as :
8. A bus organization for seven register: a. Pop
a. ALU b. Push
b. RISC c. Both
c. CPU
d. None
d. MUX

COMPUTER ORGANIZATION AND ARCHITECTURE

COA-MCQ 31 KNREDDY

15. A stack in a digital computer is a part of 21. In register stack items are removed from the
the : stack by using the operation:
a. ALU
b. CPU a. Push
c. Memory unit b. Pop
d. None of these c. Both
d. None
16. In stack organization address register is known
as the: 22. Which register holds the item that is to be
written into the stack or read out of the stack:
a. Memory stack
b. Stack pointer
c. Push operation a. SR
d. Pop operation b. IR
c. RR
d. DR
17. In register stack a stack can be organized by a
number of register:
23. In register stack the top item is read from the
stack into:
a. Infinite number
b. Finite number
c. Both a. SR
d. None b. IR
c. RR
d. DR
18. Which operation are done by increment or
decrement the stack pointer:
24. In conversion to reverse polish notation the
and operations are performed at the end:
a. Push
b. Pop
c. Both a. Add and subtract
d. None b. Subtract and multiplication
c. Multiplication and subtract
d. All of these
19. In register stack a stack can be a finite number
of :
25. RPN stands for:
a. Control word
b. Memory word a. Reverse polish notation
c. Transfer word b. Read polish notation
d. All of these c. Random polish notation
d. None of these
20. The stack pointer contains the address of the
word that is currently on : 26. Instruction formats contains the memory
address of the :
a. Top of the stack a. Memory data
b. Down of the stack b. Main memory
c. Top and Down both c. CPU
d. None d. ALU

COMPUTER ORGANIZATION AND ARCHITECTURE

COA-MCQ 32 KNREDDY

27. In instruction formats instruction is represent 33. 3-Address format can be represented as :
by a of bits: a. dst <-[src1][src2]
b. dst ->[src1][src2]
a. Sequence c. dst <->[src1][src2]
b. Parallel d. All of these
c. Both 34. 2- Address format can be represented as:
d. None a. dst ->[dst]*[src]
b. dst<-[dst]*[src]
28. In instruction formats the information c. dst<->[dst]*[src]
required by the for execution: d. All of these
a. ALU 35. In 1-address format how many address is used
b. CPU both as source as well as destination:
c. RISC
d. DATA a. 1
b. 2
c. 3
29. The operation is specified by a binary code d. 4
known as the :

36. The stack pointer is maintained in a :

a. Operand code
b. Opcode a. Data
c. Source code b. Register
d. All of these c. Address
d. None of these
30. Which are contains one or more register that
may be referenced by machine instruction: 37. mode of addressing is a form of implied
addressing:
a. Stack
a. Input b. Array
b. Output c. Queue
c. CPU d. Binary
d. ALU

38. Stack uses RPN to solve expression:

31. Memory –mapped is used this is just
another memory address: a. Logical
b. Arithmetic
c. Both
a. Input d. None
b. Output
c. Both 39. In the RPN scheme the numbers and operators
d. None are listed :

a. One after another

32. Which operation use one operand or unary b. One before another
operations: c. Another after one
d. Another before one

a. Arithmetic 40. In addressing modes instruction has primarily

b. Logical how many components:
c. Both a. 1
d. None b. 2
c. 3
d. 4

COMPUTER ORGANIZATION AND ARCHITECTURE

COA-MCQ 33 KNREDDY

41. EA stands for: 47. In the base –register addressing

the register reference may be :
a. Effective add
b. Effective absolute
c. Effective address a. Implicit
d. End address b. Explicit
c. Both
d. None
42. In which addressing the operand is actually
present in instruction:
48. In post –indexing the indexing is
performed
a. Immediate addressing
b. Direct addressing
c. Register addressing a. Before the indirection
d. None of these b. After the indirection
c. Same time indirection
d. All of these
43. In which addressing the simplest addressing
mode where an operand is fetched from memory
is : 49. In post-indexing the contents of the address
field are used to access a
memory location containing a address:
a. Immediate addressing
b. Direct addressing
c. Register addressing a. Immediate addressing
d. None of these b. Direct addressing
c. Register addressing
d. None of these
44. which addressing is a way of direct addressing:

50. In pre –indexing the indexing is

a. Immediate addressing performed
b. Direct addressing
c. Register addressing
d. None of these a. Before the indirection
b. After the indirection
c. Same time indirection
45. In which mode the main d. All of these
memory location holds the EA of the operand:

51. The final addressing mode that we consider

a. Immediate addressing is :
b. Direct addressing a. Immediate addressing
c. Register addressing b. Direct addressing
d. Indirect addressing c. Register addressing
d. Stack addressing
46. Which addressing is an extremely influential 52. In data transfer manipulation designing
way of addressing: as instruction set for a system is a complex :
a. Art
b. System
a. Displacement addressing c. Computer
b. Immediate addressing d. None of these
c. Direct addressing
d. Register addressing

COMPUTER ORGANIZATION AND ARCHITECTURE

COA-MCQ 34 KNREDDY

53. Which addressing is an extremely influential

way of addressing:
60. A simple differs widely from a Turing
a. Immediate addressing machine:
b. Direct addressing
c. Register addressing
d. Displacement addressing a. CISC
b. RISC
54. Which addressing offset can be the content of c. CPU
PC and also can be negative: d. ALU
a. Relative addressing
b. Immediate addressing
c. Direct addressing 61. How many types of basically Data
d. Register addressing manipulation:

55. The length of instruction set depends on:

a. Data size a. 1
b. Memory size b. 2
c. Both c. 3
d. None d. 4

56. In length instruction some programs wants a 62. Which is data manipulation types are:
complex instruction set containing a. Arithmetic instruction
more instruction, more addressing modes and b. Shift instruction
greater address rang, as in case of : c. Logical and bit manipulation instructions
d. All of these
a. RISC
b. CISC 63. Arithmetic instruction are used to perform
c. Both operation on:
d. None a. Numerical data
b. Non-numerical data
c. Both
57. In length instruction other programs on the d. None
other hand, want a small and fixed-
size instruction set that contains only a limited 64. How many basic arithmetic operation:
number of opcodes, as in case of : a. 1
b. 2
a. RISC c. 3
b. CISC d. 4
c. Both
d. None
65. which are arithmetic operation are:
58. The instruction set can have variable- a. Addition
length instruction format primarily due to: b. Subtraction
a. Varying number of operands c. Multiplication
b. Varying length of opcodes in some CPU d. Division
c. Both e. All of these
d. None f. None of these
59. An instruction code must specify the address of
the : 66. In which instruction are used to perform
Boolean operation on non-numerical data:
a. Opecode a. Logical and bit manipulation
b. Operand b. Shift manipulation
c. Both c. Circular manipulation
d. None d. None of these

COMPUTER ORGANIZATION AND ARCHITECTURE

COA-MCQ 35 KNREDDY

67. Which operation is used to shift the content of 74. Which is always considered as short jumps:
an operand to one or more bits to provide necessary
variation: a. Conditional jump
a. Logical and bit manipulation b. Short jump
b. Shift manipulation c. Near jump
c. Circular manipulation d. Far jump
d. None of these

68. is just like a circular array: 75. Who change the address in the program
a. Data counter and cause the flow of control to be altered:
b. Register
c. ALU a. Shift manipulation
d. CPU b. Circular manipulation
c. Program control instruction
d. All of these
69. Which control refers to the track of the address
of instructions:
76. Which is the common program control
a. Data control instructions are:
b. Register control
c. Program control a. Branch
d. None of these b. Jump
c. Call a subroutine
d. Return
70. In program control the instruction is set for the e. All of these
statement in a: f. None of these
a. Parallel
b. Sequence 77. Which is a type of microprocessor that is
c. Both designed with limited number of instructions:
d. None a. CISC
b. RISC
c. Both
71. How many types of unconditional jumps used d. None
in program control are follows:
78. SMP Stands for:
a. 1 a. System multiprocessor
b. 2 b. Symmetric multiprocessor
c. 3 c. Both
d. 4 d. None

79. UMA stands for:

72. Which are unconditional jumps used in a. Uniform memory access
program control are follows: b. Unit memory access
c. Both
a. Short jump d. None
b. Near jump
c. Far jump 80. NUMA stands for:
d. All of these a. Number Uniform memory access
b. Not Uniform memory access
c. Non Uniform memory access
73. Which instruction is used in program control d. All of these
and used to decrement CX and conditional jump:
81. SIMD stands for:
a. Loop a. System instruction multiple data
b. Shift manipulation b. Single instruction multiple data
c. Circular manipulation c. Symmetric instruction multiple data
d. None of these d. Scale instruction multiple data

COMPUTER ORGANIZATION AND ARCHITECTURE

COA-MCQ 36 KNREDDY

82. MIMD stands for:

a. Multiple input multiple data 91. Which is used to speed-up the processing:
b. Memory input multiple data
c. Multiple instruction multiple data
d. Memory instruction multiple data a. Pipeline
b. Vector processing
83. HLL stands for: c. Both
a. High level languages d. None
b. High level line
c. High level logic 92. Which processor is a peripheral device
d. High level limit attached to a computer so that the performance of a
computer can be improved for numerical
computations:
84. Which is a method of decomposing a
sequential process into sub operations: a. Attached array processor
a. Pipeline b. CISC b. SIMD array processor
c. RISC d. Database c. Both
d. None
85. How many types of array processor:
a. 1 b. 2 93. Which processor has a single instruction
c. 3 d. 4 multiple data stream organization that manipulates
the common instruction by means of multiple
86. Which are the types of array processor: functional units:
a. Attached array processor a. Attached array processor
b. SIMD array processor b. SIMD array processor
c. Both d. None c. Both
d. None
87. Which are the application of vector processing:
a. Weather forecasting
b. Artificial intelligence 94. Which carry is similar to rotate without carry
c. Experts system d. Images processing operations:
e. Seismology f. Gene mapping
g. Aerodynamics h. All of these a. Rotate carry
i. None of these b. Rotate through carry
c. Both
88. Which types of jump keeps a 2_byte d. None
instruction that holds the range from- 128to127
bytes in the memory location: 95. In the case of a left arithmetic shift , zeros are
a. Far jump b. Near jump Shifted to the :
c. Short jump d. All of these

89. Which types of register holds a single vector a. Left

containing at least two read ports and one write b. Right
ports: c. Up
a. Data system d. Down
b. Data base
c. Memory
d. Vector register 96. In the case of a right arithmetic shift the sign
bit values are shifted to the :
90. Parallel computing means doing several takes a. Left
simultaneously thus improving the performance of b. Right
the : c. Up
a. Data system d. Down
b. Computer system
c. Memory
d. Vector register

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COA-MCQ 37 KNREDDY

Computer System Architecture MCQ 05

1. A number system that uses only two digits, 0 9. Which ar

and 1 is called the : which are often used in digital system:
a. Octal number system a. Binary digit
b. Binary number system b. Decimal digit
c. Decimal number system c. Hexadecimal digit
d. Hexadecimal number system d. Octal digit
e. All of these
2. In which computers, the binary number are
represented by a set of binary storage device such 10. In any system,
as flip flop: there is an ordered set of symbols
a. Microcomputer also known as :
b. Personal computer a. Digital
c. Digital computer b. Digit
d. All of these c. Both
d. None of these
3. A binary number can be converted into
: 11. Which is general has two parts in number
a. Binary number system:
b. Octal number a. Integer
c. Decimal number b. Fraction
d. Hexadecimal number c. Both
d. None of these
4. Which system is used to refer amount of
things: 12. MSD stand for:
a. Number system
b. Number words a. Most significant digit
c. Number symbols b. Many significant digit
d. All of these c. Both a and b
d. None of these
5. are made with some part of body,
usually the hands: 13. LSD stand for:
a. Less significant digit
a. Number words b. Least significant digit
b. Number symbols c. Loss significant digit
c. Number gestures d. None of these
d. All of these
14. The and of a number is
6. are marked or written down: defined as the number of different digits which can
a. Number system occur in eachposition in the system:
b.
a. Numbernumerals
Arabic words a.
Base Radix
c.
b. Numeralssymbols
Number b.
Both
d.
c. Number
Both gestures c. of these
None
d. None of these d.
7. A number symbol is called a :
8. 0,1,2 ,3 ,4,5,6 ,7,8 and 9 numerals are called: 16.
a. Arabic numerals a. Which system has a base or radix of 10:
b. String numerals b. Binary digit
c. Digit numerals c. Hexadecimal digit
d. None of these d. Decimal digit
Octal digit

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COA-MCQ 38 KNREDDY

25. Which system is used in digital computers

17. Each of the ten decimal digits : because all electrical and electronic circuits can be
a. 1 through 10 made to respond to the states concept:
b. 0 through 9
c. 2 through 11 a. Hexadecimal number
d. All of these b. Binary number
c. Octal number
18. The binary number system is also called a d. Decimal number
:
a. Base one system 26. Which addition is performed in the same
b. Base two system manner as decimal addition:
c. Base system
d. Binary system a. Binary
b. Decimal
19. The two symbols 0 and 1 are known as: c. Both
a. Bytes d. None of these
b. Bits
c. Digit 27. in all digital systems actually performs
d. All of these addition that can handle only two number at a time:

20. In which counting, single digit are used for a. Register

none and one: b. circuit
a. Decimal counting c. digital
b. Octal counting d. All of these
c. Hexadecimal counting
d. Binary counting 28. Which machine can perform addition operation
in less than 1 ms:
21. In which numeral every position has a value 2
times the value f the position to its right: a. Digital machine
a. Decimal b. Electronic machine
b. Octal c. Both
c. Hexadecimal d. None of these
d. Binary
29. is the inverse operation of addition:
22. A binary number with 4 bits is called
a : a. Addition
a. Bit b. Multiply
b. Bytes c. Subtraction
c. Nibble d. Divide
d. None of these
30. of a number from another can be
23. A binary number with 8 bits is called as accomplished by adding the complement of the
a : subtrahend to the minuend:
a. Bytes
b. Bits a. Subtraction
c. Nibble b. Multiply
d. All of these c. Divide
d. All of these
24. In which digit the value increases in power of
two starting with 0 to left of the binary point and 31. Complement the subtrahend by converting all
decreases to the right of the binary point starting and all :
with power -1:
a. Hexadecimal a. 1’s to 0’s
b. Decimal b. 0’s to 1’s
c. Binary c. Both
d. Octal d. None of these

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COA-MCQ 39 KNREDDY

32. A 0 in the sign bit represents a

and a 1 in the sign bit represents a
:
a. Positive number
b. Negative number
c. Both
d. None of these

33. Which are the types of binary codes number:

a. Sign magnitude
b. 1’s complement code
c. 2’s complement code
d. All of these

34. How many types of addition in the 2’s

complement system:
a. 3
b. 4
c. 5
d. 6

35. Which are the types of addition in the 2’s

complement system:
a. Both number positive
b. A Positive number and a smaller negative
number
c. A negative number and a smaller positive
number
d. Both number negative
e. All of these

36. Which are the types of important ideas to

notice about these odometer readings:
a. The MSB is the sign bit :0 for a +sign and 1
for a – sign
b. The negative number represent the 2’s
complement of the positive number
c. Both d. All of these

37. Which is an algorithm or techniques used to

multiply two numbers:
a. Addition algorithm
b. Subtraction algorithm
c. Multiplication algorithm
d. All of these

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COA-MCQ 40 KNREDDY
Computer System Architecture MCQ 06
8. Which disk read the data by reflecting pulses
1. Which is an important data transfer technique : of laser beams on the surface:
a. CPU
b. DMA a. Magnetic disk
c. CAD b. Soft disk
d. None of these c. Floppy disk
d. Optical disk
2. Which device can be thought of as
transducers which can sense physical effects and 9. Data access time of optical disk varies from
convert them into machine-tractable data: 200 to 350minutes with transfer rate of :
a. 130KB/s to 400KB/s
a. Storage devices b. 130KB/s to 500KB/s
b. Peripheral devices c. 150KB/s to 600KB/s
c. Both d. 150KB/s to 800KB/s
d. None
10. NAND type flash memory data storage devices
3. Which devices are usually designed on the integrated with a interface:
complex electromechanical principle: a. ATM
b. LAN
a. Storage devices c. USB
b. Peripheral devices d. DBMS
c. Input devices
d. All of these 11. Which disk is based on the same principle as
the optical disk:
4. Which disk is one of the important I/O a. Optical disk
devices and its most commonly used as permanent b. Magnetic disk
storage devices in any processor: c. Magneto-optical disk
d. All of these
a. Hard disk
b. Optical disk
c. Magneto disk
d. Magneto Optical disk 12. Which are following pointing devices:
a. Light pen
5. In storage devices PC have hard disk having b. Joystick
capacities in the range of : c. Mouse
d. All of these
a. 12GB to 15GB
b. 15GB to 20GB 13. Full form of LED:
c. 20GB to 80GB a. Light emitting diode
d. 80GB to 85GB b. Light encounter destination
c. Live emitting diode
6. Which disk is a 3.5-inch diskette with a d. None of these
capacity of 1.44MB:
14. In mouse we use pair of LED:
a. Soft disk a. Optical
b. Floppy disk b. Digital
c. Both c. Analog
d. None d. All of these

7. Which has a large storage capacity of 2 15. is device that is designed for gaming
to8GB: purposes and based on principle of electricity:
a. Joy
a. Magnetic tape b. Stick
b. Magnetic disk c. Joystick
c. Soft disk d. None of these
d. Floppy disk

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COA-MCQ 41 KNREDDY
16. Joystick uses shaft potentiometers for:
a. X-Y DIRECTION 25. technique is used in
b. Only X direction evaluating objective answer sheets:
c. Only Y direction
d. All of these a. Optical Mark Reader
b. Optical Marker Reader
17. Full form of ADC: c. Optical Marker Reading
a. Analog to digital converter d. All of these
b. Digital to analog converter
c. Accumulator digital converter 26. technique help in banking sector:
d. All of these
a. OCR
18. A system that enables computer to recognize b. OMR
human voice called: c. MICR
a. Voice system d. None of these
b. Voice input system
c. Input system 27. camera records image, converts it into
d. None of these digital format via ADC and stores it on a frame
buffer:

a. Video
b. Without video
c. Audio
d. None of these

28. Sensors are type of devices:

a. Interactive
b. Non-interactive
c. Interaction
d. Intermediate

29. Output devices commonly referred as:

a. Terminals
b. Host
c. Receivers
d. Senders

24. Optical scanner devices are:

a. MICR c. OCR
b. OMR d. All of these
a. 12-12 inch
32. A monitor consists of : b. 12-21 inch
a. ARU c. 21-12 inch
b. BRT d. 21-11 inch
c. CRT
d. ARU 35. Range of color depends on:
a. Number of bits code lines with each pixel
33. LCD stands for: b. Number of bits associated with each pixel
a. Liquid crystal display c. Number of instructions associated with each
b. Liquid catalog display pixel
c. Liquid crystal data d. Number of code associated with each pixel
d. Liquid code display

34. The size of monitor ranges from:

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COA-MCQ 42 KNREDDY
36. Which parameter defines number of times 57. By which signal flow of traffic between
electron beam scans screen in a second: internal and external devices is done:
a. Refresh rate a. Only control signal
b. Data transfer rate b. Only timing signal
c. Pitch rate c. Control and timing signal
d. All of these d. None of these

37. Refresh rate refresh screen up to: 58. In devices 2 status reporting signals are:
a. 30 Hz per frame
b. 33 Hz per frame a. BUSY
c. 44 Hz per frame b. READY
d. 20 Hz per frame c. Both a & b
d. None of these

59. I/O module must recognize a address

51. interface is an entity that controls data for each peripheral it controls:
transfer from external device, main memory and or
CPU registers: a. Long
b. Same
a. I/O interface c. Unique
b. CPU interface d. Bigger
c. Input interface
d. Output interface 60. Each interaction b/w CPU and I/O module
involves:
52. The operating mode of I/O devices is
for different device: a. Bus arbitration
b. Bus revolution
a. Same c. Data bus
b. Different
c. Optimum
d. Medium

53. To resolve problems of I/O devices there is a

special hardware component between CPU
and to supervise and synchronize all input d. Control signals
output transfers:
61. Which are 4 types of commands received by
a. Software an interface:
b. Hardware a. Control, status, data output, data input
c. Peripheral b. Only data input
d. None of these c. Control, flag, data output, address arbitration
d. Data input, data output, status bit, decoder
54. I/O modules are designed with aims to:
a. Achieve device independence 62. Two ways in which computer buses can
b. Handle errors communicate with memory in case of I/O devices
c. Speed up transfer of data by using:
d. Handle deadlocks a. Separate buses for memory and I/O device
e. Enable multi-user systems to use dedicated b. Common bus for memory and I/O device
device c. both a & b
f. All of these d. none of these

63. There are 2 ways in which addressing can be

done in memory and I/O device:
a. Isolated I/O
b. Memory-mapped I/O
c. Both a & b
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COA-MCQ 43 KNREDDY
d. None of these

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COA-MCQ 44 KNREDDY

64. Advantages of isolated I/O are: 72. All the operations in a digital system are
a. Commonly usable synchronized by a clock that is generated by:
b. Small number of I/O instructions a. Clock
c. Both a & b b. Pulse
d. None of these c. Pulse generator
d. Bus
65. In addressing technique separate
address space is used for both memory and I/O
device: 73. is a single control line that informs
a. Memory-mapped I/O destination unit that a valid is available on the bus:
b. Isolated I/O a. Strobe
c. Both a & b b. Handshaking
d. None of these c. Synchronous
d. Asynchronous
66. is a single address space for storing
both memory and I/O devices: 74. What is disadvantage of
a. Memory-mapped I/O strobe scheme:
b. Isolated I/O a. No surety that destination received data
c. Separate I/O before source removes it
d. Optimum I/O b. Destination unit transfer without knowing
whether source placed data on data bus
67. Following are the disadvantages of memory- c. Can’t said
mapped I/O are: d. Both a & b
a. Valuable memory address space used up
b. I/O module register treated as memory 75. In technique has 1 or more control
addresses signal for acknowledgement that is used for
c. Same machine intersection used to access intimation:
both memory and I/O device a. Handshaking
d. All of these b. Strobe
c. Both a & b
68. Who determine the address of I/O interface: d. None of these
a. Register select
b. Chip select 76. The keyboard has a asynchronous
c. Both a & b transfer mode:
d. None of these a. Parallel
b. Serial
69. 2 control lines in I/O interface is: c. Optimum
a. RD, WR d. None
b. RD,DATA
c. WR, DATA 77. In transfer each bit is sent one after the
d. RD, MEMORY another in a sequence of event and requires just one
line:
70. In I/O interface RS1 and RS0 are used for a. Serial b. Parallel
selecting: c. Both a & b d. None of these
a. Memory
b. Register 78. Modes of transfer b/w computer and I/O device
c. CPU are:
d. Buffer a. Programmed I/O
b. Interrupt-initiated I/O
71. If CPU and I/O interface share a common bus c. DMA
than transfer of data b/w 2 units is said to be: d. Dedicated processor such as IOP and DCP
a. Synchronous e. All of these
b. Asynchronous
c. Clock dependent
d. Decoder independent

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COA-MCQ 45 KNREDDY

82. User programs interact with I/O devices

79. is a dedicated processor that combines through:
interface unit and DMA as one unit:
a. Input-Output Processor a. Operating system
b. Only input processor b. Hardware
c. Only output processor c. Cpu
d. None of these d. Microprocessor

83. Which table handle store address of interrupt

handling subroutine:
80. 3 types of exceptions are:
a. Interrupts a. Interrupt vector table
b. Traps b. Vector table
c. System calls c. Symbol link table
d. All of these d. None of these
81. Which exception is also called software 84. interrupt establishes a priority over
interrupt: the various sources to determine which request
a. Interrupt should be entertained first:
b. System calls
c. Traps a. Priority interrupt
d. All of these b. Polling
c. Daisy chaining
d. None of these

85. VAD stands for:

a. Vector address
b. Symbol address
c. Link address
d. None of these

86. than two CPUs assembled in single system unit:

a. One or More
b. Two or More
c. One or One
d. Two or Two

87. Which refers the execution of various software process concurrently:

a. Multiprocessor
b. Serial communication
c. DCP
d. IOP

88. Which is used for this and known as high speed buffer exist with almost each process?

a. Primary
b. RAM
c. Cache
d. None of these

89. Multiprocessor uses large caches but limited process that shares
a. Memory bus
b. Single memory bus
c. Double memory bus
d. None of these

COMPUTER ORGANIZATION AND ARCHITECTURE