ATPG QUESTION ANSWER

Name: Meet Zankat

1. What is the difference between PODEM and D algorithm?

➢ PODEM proves to be more efficient as compared to a D-ALG because it limits
its search space only to Primary Inputs of the circuits. D-ALG on the other hand
has a search space comprising of all the internal nodes of the circuit along with
the Primary inputs.
➢ The first objective of PODEM algorithm is to sensitize the fault. After the fault
is sensitized, the objectives are changed in ordered to propagate the fault to a
Primary Output. Depending on the current objective, we do the back tracing
used to determine the value of one of the PIs. For every PI assigned, logic
simulation is performed.
➢ This process of assigning values to PIs is repeated till PIs form a test vector to
propagate that fault to PO.

2. Types of capture procedures in SPF and its meaning?

➢
3. what is the reason for low test coverage?
➢ By the ATPG untestable fault the effect on coverage also extends to all the logic
gates that have an input tied and whatever upstream faults are blocked by that
constraint. Faults downstream from the tied logic have limited control, which
further affects our coverage.
➢ A high number of NC and NO faults, which are both Not Detected (ND) faults,
indicates the problem lies with abort conditions.so for that you have to increase
the atpg abort limit by using command.

4. AU fault in detail?
➢ AU Black Box - These are faults that are untestable due to a black box, which
includes faults that need to be propagated through a black box to reach an
observation point, as well as faults whose control or observation requires values
from the output(s) of a black box.
 ➢ AU Pin Constrain - These are faults that are uncontrollable or that cannot be
propagated to an observation point, in the presence of a constraint value. That
is, because the tool cannot toggle the pin, the tool cannot test the fanout.

➢ AU Undriven - These are faults that cannot be tested due to undriven input
pins. For the purpose of this analysis, undriven input pins include inputs driven
by X values. Faults are occur on undriven pins and on pins that are untestable
due to other pins being undriven.

➢ AU Sequential Depth - These are faults associated with non-scan cells that
require multiple clock cycles to propagate to an observe point. One possible
solution is to increase the sequential depth using the command.

➢ AU Multicycle Path - These are faults that can be tested only through a
multicycle path, which means that the fault cannot propagate between the launch
and capture point within a single clock cycle.

5. what is the use of transition delay fault?

➢ Technologies contain some types of defects that are delay sensitive and it can no
longer be detected with traditional stuck-at test. Today’s integrated circuits are
seeing an escalating clock rate, shrinking dimensions, increasing chip density, etc.
Consequently, there arises a class of defects that would affect the functionality
of the design if the chip is run at a high speed. In other words, the design is
functionally correct when it is operated at a slow clock. This type of defect is
referred to as a delay defect.
➢ High impedance shorts, resistive vias and bridges, in-line resistance, and crosstalk
between signals are some of these types of defects that are commonly seen in
today's nanometer designs. Since many of these defects cause faulty timing
behavior, they can be effectively caught only by applying the tests at system
speeds. This has led to the required use of delay-based fault models in Automated
Test Pattern Generators (ATPG) like Transition fault model in ATPG to target
these defect types.
 6. How pattern count will be less in LOS?
➢ So as compared to LOC the pattern count is less in LOS.
➢ Because in LOS we control our all operation by using scan path. but in LOC for
launching the second vector we use the functional input, which is coming from
some combinational logic. So for set that functional input to proper value we
have to set some extra pattern. But in case of LOS for launch we use Scan signal.
Which shows in figure below.

Launch
from PI
Launch from
SI

7. LOS - what will be lunch frequency?

➢ Basically in LOS we do launch and capture at same frequency which is
functional(High) frequency. because if we do launch on high frequency then and
then only we can find the str or stf fault in that proper noad.
8. Why can't we do whole scan on functional frequency?
➢ There are mainly three reson because of that we can not do the ATPG at
functional(High) frequency.
➢ First one is if we want to do the ATPG at high frequency then we need the high
frequency ATE tester. And for that we also need to set our SE signal to the high
frequency and this thing is very costly that’s why we not use high frequency.
➢ Second reason is when we use the high frequency on ATPG so our toggling
speed of clk and data will also increase and because of that our power dissipation
is there.
➢ Third reson is when we use the high frequency our all circuit will work on atpg
at high frequency and because of that it is possible that our circuit will heat more
and more ir drop will be there, and because of that there are the chances that
our circuit will burn out.

9. LOES ?
➢ LOES – Launch on Extra shift is delay fault test technique used to solve
problems of LOS methodology. In LOES methodology, transition is launched
by extra fast shift clock. In case of scan chain having N bit scan length, N slow
shift clock cycle require to load entire scan chain and (N+1)th fast shift clock is
used to launch the transition.

➢ Then fast functional clock happens to capture response after scan enable signal
goes low. So, in LOES, extra shift and capture clocks are at-speed clocks.
Essentially, loading unloading processes of LOES are similar to LOC whereas
launching process is same as LOS because transition is launched through shift
path.
10. Advantage and disadvantage loc and los?
➢ LOS :
• Advantages :
→ Basic advantage is in los our pattern count. In los we need a less pattern
count as compare to loc.
→ In los we get high coverage because in los we launch the data from SI.
And we have the proper controbilty of the scan path.
• Disadvantages :
→ In los we have to give the Launch pulse on a high frequency. and after
the imidiatly we have to make SE to low, for that we need to set some
high frequency SE signal wich is very costly.

➢ LOC :
• Advantages :
→ In loc we launch our data on capture time so our launch pulse and
capture pulse is working on high frequency. and before the launch we set
SE to low. So there is no need of high frequency SE signal.
• Disadvantages :
→ Basic disadvantage in loc is we use the functionl path to launch our
data. And for that we set our cominational logic to a proper logic value
for that we need some more pattern to set that proper combinational logic.
→ In loc there will be less coverage as compare to the los beause we use
combinational logic to get the launch pulse.because of that we have less
controalibity.
11. What is ATPG effectiveness?
➢ ATPG effectiveness measures the ATPG tool’s ability to either create a test for
a fault or prove that a test cannot be created for the fault under the restrictions
placed on the tool.
➢ ND (not detected fault) is not count in this formula because ATPG is not sure
for that fault to generate the pattern or not sure for not generate the pattern. If
we increase the abort limit it is possible that ATPG can detected that fault.

➢ Formula: ATPG Effectiveness: DT + AU + PT + UD x 100

ALL FAULT

12. what is CTL file? and what is having?

➢ CTL is an extension of STIL that creates a standard format to describe SOC test
information.
➢ For each test mode, CTL provides information about structures available,
characteristics of the terminals of the design, connectivity that is relevant to test
applications, and test patterns. With test information for a core provided in CTL,
you can reuse the test patterns that came with the core, and perform all the
necessary DFT, ATPG, and fault simulation operations on the SOC.

13. Why we cannot use transition 1st?

➢ Yes, we can do the transition first as per my knowledge. Because in transition
fault we try to find that our which circuit nod takes more time to transit from
high to low and low to high. And in stuck at we find that which nod is stuck at
0 or stuck at 1. So, in basically if we detect the transition fault then all the stuck
at fault is cover. So we can do the transition first.
14. path delay concept?
➢ A path is a sequence of connected gates from a circuit primary input to a primary
output.
➢ A path delay fault is said to have occurred if the delay of a path is more than the
specified clock period of the circuit. Path delay fault tests are more likely to detect
small delay defects.

➢ In this Path A-P-Q-R-D is tested for rising transition at pin A. Small delay defects
distributed along the path will be tested if the cumulative delay exceeds
specification.