ATPG ANSWER

Name : Meet Zankat

1.Why can't we do scan insertion in memory?

➔ Memories is a very large part of VLSI circuits. The purpose of memory systems design is to store
massive amounts of data.
➔ To test the memories functionally or via ATPG (Automatic Test Pattern Generation) requires very
large external pattern sets for acceptable test coverage due to the size and density of the cell array-
and its associated faults.
➔ Conventional DFT methods do not provide a complete solution to the requirement of testing
memory faults and its self-repair capabilities.

3. Understanding of SPF file?

➢ Here there are 6 main blocks in full scan SPF file which are mention below.
• Signals
• Signal groups
• Scan structure
• Timing
• Procedures
• MacroDefs

So,

➢ Signals

It is the first section of SPF containing definition of all the signals with their type(In,
Out, InOut etc).

➢ Signal Grouping

In this section, the signals which were defined in the first part is classified based
in different group based on its type.

The grouping signals further used to provide constraint value at different procedures.

➢ Below shown are some signal groupings:

all_in, all_out, all_ports, all_bidi, _pi, _po, _si, _so.
➢ Scan Structure

This section includes the scan chain information like scan chain name, Scan_in, scan_out
and scan_enable pin and also the clock used by that particular chain.

➢ Timing

Waveform table is defined in this section which includes the description of the different
values provided to different signals like clock period definition, reset value, test mode
value etc.

Waveform table is defined for all the different procedures which are required for different
use:

➢ Default_WFT
➢ Multiclock_capture_WFT
➢ Allclock_capture_WFT
➢ Allclock_launch_WFT
➢ Allclock_launch_capture_WFT

➢ Procedure

Procedures are defined for the capture cycle of stuck-at and at-speed faults like
Multiclock_capture, allclock_capture, allclock_launch, allclock_launch_capture
procedures.

Based on which fault model you are using, the capture procedure will be automatically
selected.

➢ MacroDefs
This division includes the test setup part through which we can initialize the instruction
and data bit.
Also, the test setup is required to provide the values to the signals before the pattern
generation starts for the scan mode to bring chip in its known state like functional
mode, test mode.

4. Difference between post DRC and ATPG DRC.

During the DFT insertion stage, we check for the DRC rules such as:
 1. Clocks are controlled
2. Asynchronous set/reset are controlled
3. Clock gating cells are enabled
4. bidirectional pins are set to in/out during shift

So after in ATPG DRC, I think to do the ATPG we also change the tool. So in ATPG tool we do the
DRC for like ATPG related violation. Like timing operation,and it also check our scan chain input if
any scan chain contain X value or same value then atpg drc through that violation.

5. Difference between LOS&LOC. How it works ? Please explain with example.

LOS : Specified by the last_shift option, ATPG launches a logic value in the last scan load cycle
when the scan enable is active, that is, in scan-shift mode. It exercises target transition faults and
then captures new logic values in a system clock cycle when the scan enable is inactive, that is, in
capture mode.

LOC : In launch-off-capture (LOC) method the transition is launched and captured through
the functional pin (D) of any flip-flop in the scan chain. Since, the launch pattern V2
depends on the functional response of the initialization vector V1.like in below figure.
6. Example of Fault category ?

a. DT – Detected :
The Faults which are detected during the ATPG process are categories under DT.
Example like stuck at 0 fault, stuck at 1 fault.

b. PT - Possibly Detected
The Possible detected, faults includes all the faults that fault simulation identifies as
possible detected.

c. UD – Undetectable
This fault class includes the undetected faults that cannot be proven untestable or
atpg_untestable.
Like one input od and gate is connected to ‘0’. And second input is stck at 0. So this kind
of fault we can not detected.

d. AU - ATPG Untestable
This fault class includes all the faults for which test generator unable to find the pattern
to create a test. Testable faults become ATPG untestable faults because of constraints or
limitations, placed on the ATPG tool such as pin constraint or an insufficient sequential
depth. This fault may be detectable, if we remove some constraint, or change some
limitations on the test generator.

e. ND - Not Detected