Introduction to Peripheral

Interfacing-1
 PERIPHERAL INTERFACING
• Microprocessor based system design involves interfacing of the processor with
one or more peripheral devices for the purpose of communication with various
input and output devices connected to it.

• During the early days of the microprocessor revolution, these techniques

required complex hardware consisting of Medium scale integration devices
makes the design highly complex and time consuming.

• INTEL have developed a large number of general and special purpose

peripheral devices, most of them being single chip circuits. They are also
programmable devices.

• Hence these peripheral devices are found to be of tremendous use to a system

designer.
 TYPES OF PERIPHERALS DEVICES

• General purpose peripherals and

• Special purpose peripherals

 General purpose peripherals devices
• Perform a task but may be used for interfacing a variety
of I/O devices to microprocessor.

• The general purpose devices are given below:

• Simple I/O -- (Non-programmable)
• Programmable peripheral Interface (PPI) – (8255)
• Programmable Interrupt Controller – (8259)
• Programmable DMA Controller – (8237/8257)
• Programmable Communication Interface – (8251)
• Programmable Interval Timer – (8253/8254)
 Special purpose peripherals devices
• may be used for interfacing a microprocessor to a specific type of
I/O device.

• These peripherals are more complex and more expensive than

general purpose peripherals.

• The special function peripherals are

• Programmable CRT Controller
• Programmable Floppy Disc Controller
• Programmable Hard Disc Controller
• Programmable Keyboard and display interface.

• The functioning of these devices varies depending on the type of I/O

device they are controlling.
 Programmable peripheral Interface (PPI) – (8255)

• 8255 is a widely used, programmable, parallel I/O

device.

• The PPI has three programmable I/O ports viz.,

Port A, Port B and Port C each of 8 bit width.

• Port C can be treated as two ports – Port C upper

(PC -4) and Port lower (PC – 0) and these two can
7 3

be independently programmed as INPUT or

OUTPUT ports.
 Features of 8255
• It is a general purpose programmable I/O device which is compatible
with all INTEL processors and also most other processors.

• It provides 24 I/O pins which may be individually programmed in two

groups. The two groups of I/O pins are named as Group A and Group
B.

• It is available in 40 pin DIP.

• 8255 is mainly programmed in two modes (a) I/O mode and (b) bit
set/reset mode (BSR) mode. The I/O mode is further divided into
three modes: Mode 0, Mode 1, and Mode 2.
Block Diagram of 8255
Group A Control and Group B Control
• Group A control block controls - PortA and PC7-PC4.
• Group B control block controls - Port B and PC3- PC0

Data Bus buffer :

• 8 bit, 3-state bidirectional used to interface the internal data bus of 8255 to the
external system data bus.
• Output data from the MPU to the ports or control register and the input data to
the MPU from the ports or status register are all pushed through the buffer.
• It is controlled by the read/write control logic.

Control Logic
• Manage all internal and external transfer of data and control words.
• RD’, WR’, A1, A0 and RESET are inputs provided by MPU
• It issues commands to the individual group control blocks (Group A Control
and Group B Control)
PIN Configuration of 8255
 PIN Description
D0-D7 (Data Bus):
• Bidirectional data bus lines connected to the system
data bus and used to transfer data/control word to/from
the microprocessor.

• PA0-PA7(PortA): These 8-bit bidirectional I/O pins act

as either input or output lines depending upon control
word loaded into control word register.

• PB0-PB7(Port B): These 8-bitbidirectional I/Opins

which can be used same way like Port A.
 CONTD
• PC0- PC7(port C):
• These 8-bit bidirectional I/O pins are divided into two
groups PCL (PC0- PC3) and PCU (PC4- PC7).
• PCU also can be used for generation of handshake lines in
mode 1 or mode 2

• RD’ (Read):
• Active low signal indicate reads data in the ports or the
status word through data buffer.

• WR’ (Write): Active low signal writes data in the ports or

the control register through data Buffer
 CONTD
• CS’ (Chip Select):
• It is an active low input signal used to enable
8255 to respond RD’ and WR’ signals.

• RESET: It is an active high input used to reset

8255. When reset input is high, the control
register is cleared and all the ports are set to the
input mode.
 CONTD
A0&A1: These address input signals along with RD’,
WR’ inputs control the selection of control / status word
registers or one of three ports.
 Modes of operation of 8255
• Bit Set-Reset Mode (BSR) – used to set or
reset its individual port bits.

• I/O mode – 8255 ports works as

programmable I/O ports
Mode 0: Simple I/O mode
Mode 1 : I/O with Handshaking mode
 Mode 2: Bidirectional data transfer mode
I/O Mode
Mode 0 : Basic Input/output
• Provides simple input and output operations for each of the three ports.

• There are two 8-bitports (A and B) and two 4-bit ports [C (lower)] and
[C (upper)].

• Any port can be an input port or an output port.

• Ports do not have handshake or interrupt capabiltity
 EX: Mode 1
• When CPU wants to send data to slow peripheral device like printer,
it will send handshaking signal to printer to tell whether it is ready
or not to transfer the data.
• When printer will be ready, it will send one acknowledgement to
CPU then there will be transfer of data through data bus.
 Mode 2 : Strobed Bidirectional Bus

• In this mode only port A works, and port B can

work either in mode 0 or mode 1.

• Port A is used as bi-directional port with

simultaneous input and output capability.

• 6 bits port C are used as handshake signals.

• It also has interrupt handling capacity.

 Steps required to to communicate with peripherals
through 8255

• Determine the addresses of Port A, B, C and

Control register according to Chip Select Logic
and the Address lines A0 and A1.

• Write a control word in control register.

• Write I/O intructions to communicate with

peripherals through port A, B, C.
 PROGRAMMABLE INTERVAL TIMER
8253/8254
A timer is a specialized type of clock which is
used to measure time intervals.
A counter is a device that stores (and
sometimes displays) the number of times a
particular event or process occurred, with
respect to a clock signal. It is used to count the
events happening outside the microcontroller.
What is 8254/8253?

• The Intel 8254/8253 is a programmable

counter/timer device designed to solve the common
timing control problems in microprocessor system
design.
• 8254 is the high speed version of the 8253.
• When 8254/8253 used as timing and delay
generation peripheral, microprocessor becomes free
from tasks related to counting process and can
execute program in memory, while timer device
perform counting tasks.
• Minimizes the software overhead on Microprocessor
Application

Real time clock

Event-counter
Digital one-shot
Programmable rate generator
Square wave generator
Binary rate multiplier
Complex waveform generator
Complex motor controller
 Features
It includes three 16-bit counters that can work
independently in 6 different modes.
It is packaged in a 24-pin DIP(Dual in-line
package) and requires +5V power supply.
It can count either in binary or BCD.
It’s counters can operate at a maximum
frequency of 10 MHz for 8254 and 2MHZ for
8253.
8253 uses N-MOS technology and 8254 uses H-
MOS technology.
Counters 0, 1 and 2:

• Three counters available in 8254/8253 are

independent of each other in operation.
Each counter has two input CLK and GATE
and one output OUT.

• All are 16 bit presettable down counters,

able to operate either in BCD or
Hexadecimal mode.
Control Word Register:

• Contain information that can be used for

writing or reading the count value to or from
respective count register using IN and OUT
instructions.

• This register selected when A0, A1 =1, and

accept 8-bit control word written by
Microprocessor and stores it for controlling the
operation of specific counter.

• It can be only written and cannot be read

Pin functions
A0, A1: The address inputs select one of the four internal registers within the 8254.

A1 A0 Function
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word

CS : A low on Chip select enables the 8254 for programming and for reading or
writing a counter.
Vcc: Power connects to the +5V power supply.

GND: Ground connects to the system ground bus.

GATE : The gate input controls the operation of the counter in some modes of
operation.

GATE 0 Gate input of counter 0

GATE 1 Gate input of counter 1

GATE 2 Gate input of counter 2

D0-D7: Bidirectional three state data bus lines connected to system data bus.

CLK : The clock input is the timing source for each of the internal counters.
CLK0 Clock input of counter 0
CLK1 Clock input of counter 1
CLK2 Clock input of counter 2
OUT: A counter output is where the waveform
generated by the counter is available.
OUT 0 Output of counter 0
OUT 1 Output of counter 1
OUT 2 Output of counter 2
Programming the 8254 /8253 (Control Word Format)
8254/8253 Write operation
The programming procedure for the 8254 is very flexible. Only two conversion
need to be remember.
1) For each Counter, the Control Word must be written before the initial
count is written.
2)The initial count must follow the count format specified in the Control Word
(least significant byte only, most significant byte only, or least significant byte
and then most significant byte).
With a clock and an appropriate gate signal to one of the counters, the above
steps should start the counter and provide appropriate output according to the
control word.
 Modes of Operation

Mode 0: Interrupt on terminal count.

Mode 1: Hardware Retriggerable One-Shot.

Mode 2: Rate Generator.

Mode 3: Square Wave Mode.

Mode 4: Software Triggered Mode.

Mode 5: Hardware Triggered Mode.

 Mode 0: Interrupt on terminal count

 Mode 0 used for generation of accurate time delay under software control.
 After the Control Word is written, OUT is initially low, and will remain low until the
Counter reaches zero. OUT then goes high and remains high until a new count or a
new Mode 0 Control Word is written into the Counter.
 High output used to interrupt the processor, by setting terminal count
 Mode 0: Interrupt on terminal count. (Continued)

 GATE =1 enables counting; GATE = 0 disables counting.

 If G becomes a logic 0 in the middle of the count, the counter will remain stop
until G again becomes a logic 1.
 If a new count is written to the Counter, it will be loaded on the next
CLK pulse and counting will continue from the new count.
 At the first falling edge of clock after first rising edge of WR(LSB), counter starts
counting.
 Mode 1: Hardware Retriggerable One-Shot.

 Causes the counter to function as a retriggerable, monostable

multivibrator (one-shot).
 OUT is initially (after loading CW) high. Also remain high when count value
is written into counter.
 When gate is triggered, OUT goes low and will remain low until the
Counter reaches zero. On completion of count OUT goes high again.
 Width of the output pulse depends upon count value.
 Mode 2: RATE GENERATOR

 It is a divide by N counter and used to generate real-time clock interrupt.

 If count N is loaded then, output will remain high for (N-1) clock pulses.
 After (N-1) clock pulses, out will low for 1 clock pulse and becomes high
again.
 Count N is reloaded and again out becomes high for (N-1) clock pulse and low
for one clock pulse.
 Mode 2: RATE GENERATOR (Continued)
 This cycle is repeated until the counter is programmed with a new count or until G
pin is placed at a logic 0 level.
 The G input must be logic 1 for this mode to generate a continuous series of
pulses.
 Mode 3: Square Wave Mode .

 Used as square wave generator and generates a continuous square wave at the
out connection.
 Mode 3 is similar to Mode 2 except for the duty cycle of OUT.
 If the count (N) is even, the output is high for one half (N/2) of the count and
low for next half (N/2) of the count.
 If the count (N) is odd, the output is high for (N+1)/2 clock pulses and low for
(N-1)/2 clock pulses.
 Gate should be maintained at logic 1 always.
 Mode 4: Software Triggered strobe

 Allows the counter to produce a single pulse at the output

 If count of N is loaded, counting starts, OUT will be high for N clock cycles and
low for one clock cycle when count reaches 0.

 The low pulse can be used as strobe while interfacing the microprocessor with
other peripherals.
 The cycle does not begin until the counter is loaded again.
 Gate is always high.
 Mode 5: Hardware Triggered strobe

 A hardware triggered strobe that function as mode 4, except that it

is started by a trigger pulse on the G pin instead of by software.
 When the GATE pulse is triggered from low to high the count begins.
At the end of the count, OUT goes low for one clock period.

 This mode is also called HARDWARE TRIGGERED STROBE

(RETRIGGERABLE)
What instructions are needed to program Counter 0
for BCD counting in mode 4? Initial count is 4788H.
Solution :
Control Word = 00 11 100 1 = 39H
Counter 0 LSB & MSB Mode 4 BCD
MOV AL,39H
OUT CWR,AL
MOV AL,88
OUT Counter0,AL ; Counter0 =8-bit address of
counter0
MOV AL,47
OUT Counter0,AL
What instructions are needed to program Counter 2
for binary counting in mode1, with an initial count
of A0H?
Solution
Control Word = 10 01 001 0 (92H)
Program
MOV AL, 92H
OUT CWR,AL ; CWR= Address of Control Register
MOV AL,0A0H
OUT Counter2,AL ; Counter2 = 8-bit address of
counter2
Programmable Interrupt
Controller - 8259
 Why 8259?
• To interface I/O devices to the microprocessor.

• The 8086 has only two interrupt inputs, NMI and INTR. If we use
NMI for a power failure interrupt, this leaves only one interrupt
input for all other applications.

• To overcome these disadvantages, the programmable interrupt

controller that is capable of handling number of interrupts is
used.

• 8259 can take care of all the interrupts simultaneously along

with their priorities and types.

• Intel’s 8259 was compatible with only 8-bit microprocessors but

the advanced version of it, 8259A is compatible with 8 as well
as 16-bit microprocessors.
 FEATURES OF 8259
• INTEL 8259 is a single chip programmable interrupt controller
which is compatible with 8085, 8086 and 8088 processors.

• It is a 28 pin DIP IC with N-Mos technology and requires a single

+5V DC supply.

• Ability to accept level triggered or edge triggered inputs.

• It handles up to eight vectored priority interrupts for the CPU and

cascadable for upto 64 vectored priority interrupts without the
need of any additional circuitry.

• when two 8259s are cascaded through cascade lines the first
8259 will act as master and the second 8259 will act as a slave.
Connection of 8259A with 8086
microprocessor (Single Mode)
 Connection of 8259A with 8086
microprocessor (Cascade Mode)

MASTER SLAVES

64 Interrupts
The 8259A PIC adds eight vectored priority encoded interrupts to the
microprocessor. This controller can be expanded without additional
hardware, to accept upto 64 interrupt requests. This require a master
8259A and eight 8259A slaves.
Architecture of 8259A
 Functional descriptions
IN Service Register (ISR)
• The IN service registers keeps tracks of which interrupt
inputs are currently being serviced.

• For each input that is currently being serviced the

corresponding bit will be set in the in service register.
 Interrupt Request Register (IRR)
• IRR stores all the interrupt inputs that are requesting service.

• Basically, it keeps track of which interrupt inputs are asking for

service.

• If an interrupt input is unmasked, and has an interrupt signal on

it, then the corresponding bit in the IRR will be set.
 INTERRUPT MASK REGISTER(IMR)

• The IMR stores the bits which mask the interrupt lines.
The IMR operates on the IRR.

• Masking of higher priority input will not affect the

interrupt request lines of lower priority. To unmask any
interrupt the corresponding bit is set ‘0’.
 PRIORITY RESOLVER

• This logic block determines the priorities of the bits

set in the IRR.

• The highest priority is selected and strobed into the

corresponding bit of the ISR during INTA’ pulse.
 DATA BUS BUFFER

• This 3- state, bidirectional 8-bit buffer is used to interface

the 8259A to the system data bus.

• Control words and status information are transferred

through the data bus buffer.
 INTERRUPT CONTROL LOGIC

• This unit has two pins. INT (Interrupt) as an output pin

and (interrupt acknowledge) INTA’ as an input pin.

• The INT is connected to the interrupt pin of the

microprocessor unit. Whenever an interrupt is noticed by
the CPU, it generates signal.
 READ/WRITE CONTROL LOGIC
• The function of this block is to accept OUTPUT commands
from the CPU.

• It contains the initialization command word (ICW)

register and operation command word (OCW) register
which store the various control formats for device
operation.

• This function block also allows the status of 8259A to be

transferred to the data bus.
 CASCADE BUFFER/COMPARATOR

• This function blocks stores the IDs of all 8259’s used in the
system. The associated 3-I/O pins (CAS0-CAS2) are outputs
when 8259A is used a master.

• The same pin act as inputs when 8259A is used as a slave.

As a master, the 8259A sends the ID of the interrupting
slave device onto the cas2-cas0.

• The slave thus selected will send its pre-programmed

subroutine address onto the data bus during the next one
or two consecutive INTA’ Pulse.
Pin diagram
 ICW3

 ICW3 (Master Device): Only used when ICW1 indicates that the system is
operated in cascade mode. ICW3 (for master device) indicates where the slave
is connected to the master. Suppose, we have two slaves connected to a master
using IR0 and IR1. The master is programmed with an ICW3 of 03H.

 ICW3 (Slave Device): ICW3 (for slave device) indicates where the slave is
connected to the master. Suppose, we have two slaves connected to a master
using IR0 and IR1. One slave is programmed with an ICW3 of 01H and other
with an ICW3 of 02H.
 ICW4

 The bit D0 must be logic 1 to select operation with the 8086 microprocessor.

 SFNM (Special Fully-Nested Mode):

 If SFNM=1, then it selects the special fully-nested mode of operation for the
8259A. At that time, this allows the highest-priority interrupt request from a
slave to be recognized by the master while is processing another interrupt
from a slave.

 Normally (if SFNM=0), only one interrupt request is processed at a time and
others are ignored until the process is complete.
 ICW4-CONTD
 BUF and M/S’:

 Buffered and master slave are used together to select buffered operation
or non buffered operation for the 8259A as master or a slave.

 AEOI (Automatic end of interrupt):

 Selects automation or normal end of interrupt.

 The EOI commands of OCW2 are used only if the AEOI mode is selected
by ICW4.

 If AEOI is selected, the interrupt automatically resets the interrupt

request bit.
 This is the preferred mode of operation for the 8259A and reduces the
length of the interrupt service procedure.
 OCW2

 Is programmed only when the AEOI mode is not selected for

the 8259A.
 In this case, this OCW selects how the 8259A responds to an
interrupt
 OCW2-CONTD
 The modes are listed as follow-

Non specific End-of-Interrupt:(Fully Nested mode)

 This is an OUT instruction by the CPU to 8259A.
 A command sent by the interrupt service procedure to signal the
end of the interrupt.
 When this command is sent to the 8259A, it resets the highest
priority ISR bit.
 This allows the interrupt to take action again or a lower priority
interrupt to take effect.

Specific EOI Command:

 A command that allows a specific interrupt request to be reset.

 The exact position is determined with bits L2-L0 of OCW2.

 OCW2-CONTD
Rotate on Nonspecific EOI Command

 A command that functions exactly like the Nonspecific End-of-

Interrupt command, except that it rotates the interrupt
priorities after resetting the interrupt status register bit.

 The level reset by this command becomes the lowest-priority

interrupt.

 For example, if IR4 was just received by this command, it

becomes the lowest-priority interrupt input and IR5 becomes
the highest priority.
 OCW2-CONTD
Rotate on automatic EOI:
Rotate on automatic EOI mode(Set)
 Once this command is sent to PIC, it will automatically cause the PIC to
perform a rotate on non-specific EOI command during INTA bus cycles.
This command must only be sent to the 8259A once if this mode is
desired.
Rotate on automatic EOI mode(Clear)
 To disable the rotate on automatic EOI mode, this clear command should
sent to 8259A.

Rotate on specific EOI:

Functions as the specific EOI, except that it selects rotating priority.

Set priority
Allows the programmer to set the lowest priority interrupt input using the
L2- L0 bits, thus fixing all other priority.
 OCW3

 Selects the register to be read, the operation of the special mask register
and the poll command.
Reading register
 Both the interrupt request register (IRR) and in-service register (ISR)
are read by programming OCW3.

 [Note- Interrupt mask register (IMR) is read through OCW1, to read

the IMR , A0=1, to read IRR or ISR, A0 = 0].

 Bit position D0 and D1 of OCW3 select which register (IRR or ISR) is

read.
Poll Mode:
If polling is selected, the P-bit must be set
and then output to the 8259A. The next read
operation would read the poll word.
THANK YOU