IRFP4768PbF

Application HEXFET® Power MOSFET

 High Efficiency Synchronous Rectification in SMPS   VDSS 250V
D
 Uninterruptible Power Supply
RDS(on) typ. 14.5m
High Speed Power Switching
 Hard Switched and High Frequency Circuits G max 17.5m
ID 93A
S

D
Benefits
 Improved Gate, Avalanche and Dynamic dV/dt Ruggedness
 Fully Characterized Capacitance and Avalanche SOA
 Enhanced body diode dV/dt and dI/dt Capability
DS
 Lead-Free, RoHS Compliant G

TO-247AC

G D S
Gate Drain Source

Standard Pack
Base part number Package Type Orderable Part Number
Form Quantity
IRFP4768PbF TO-247AC Tube 25 IRFP4768PbF

Parameter Max. Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 93
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 66 A
IDM Pulsed Drain Current  370
PD @TC = 25°C Maximum Power Dissipation 520 W
Linear Derating Factor 3.4 W/°C
VGS Gate-to-Source Voltage ± 20 V
dv/dt Peak Diode Recovery dv/dt 24 V/ns
TJ Operating Junction and
-55 to + 175  
TSTG Storage Temperature Range
°C  
Soldering Temperature, for 10 seconds
300
(1.6mm from case)
Mounting Torque, 6-32 or M3 Screw 10 lbf·in (1.1 N·m)  

Avalanche Characteristics 
EAS (Thermally limited) Single Pulse Avalanche Energy  770 mJ
IAR Avalanche Current  A
See Fig. 14, 15, 22a, 22b  
EAR Repetitive Avalanche Energy  mJ
Thermal Resistance  
Parameter Typ. Max. Units
RJC Junction-to-Case  ––– 0.29
RCS Case-to-Sink, Flat Greased Surface 0.24 ––– °C/W
RJA Junction-to-Ambient  ––– 40

1 2016-12-12
  
IRFP4768PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 250 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.20 ––– V/°C Reference to 25°C, ID = 5mA 
RDS(on) Static Drain-to-Source On-Resistance ––– 14.5 17.5 m VGS = 10V, ID = 56A 
VGS(th) Gate Threshold Voltage 3.0 ––– 5.0 V VDS = VGS, ID = 250µA
––– ––– 20 VDS = 250 V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 250V,VGS = 0V,TJ =125°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
IGSS   nA  
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
RG Gate Resistance ––– 0.71 ––– 
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
gfs Forward Transconductance 100 ––– ––– S VDS = 50V, ID =56A
Qg Total Gate Charge ––– 180 270 ID = 56A
Qgs Gate-to-Source Charge ––– 52 ––– VDS = 125V
nC  
Qgd Gate-to-Drain Charge ––– 72 ––– VGS = 10V 
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 108 –––
td(on) Turn-On Delay Time ––– 36 ––– VDD = 163V
tr Rise Time ––– 160 ––– ID = 56A
ns
td(off) Turn-Off Delay Time ––– 57 ––– RG= 1.0
tf Fall Time ––– 110 ––– VGS = 10V 
Ciss Input Capacitance ––– 10880 ––– VGS = 0V
Coss Output Capacitance ––– 700 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 210 ––– pF   ƒ = 1.0MHz, See Fig. 5
Coss eff.(ER) Effective Output Capacitance (Energy Related) ––– 510 ––– VGS = 0V, VDS = 0V to 200V
Coss eff.(TR) Output Capacitance (Time Related) ––– 830 ––– VGS = 0V, VDS = 0V to 200V
Diode Characteristics  
Parameter Min. Typ. Max. Units Conditions
Continuous Source Current MOSFET symbol D

IS ––– ––– 93
(Body Diode) showing the
A G
Pulsed Source Current integral reverse
ISM ––– ––– 370
(Body Diode) p-n junction diode.
S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C,IS = 56A,VGS = 0V 

––– 180 ––– TJ = 25°C VDD = 200V
trr Reverse Recovery Time ns
––– 200 ––– TJ = 125°C IF = 56A,
––– 1480 ––– TJ = 25°C di/dt = 100A/µs 
Qrr Reverse Recovery Charge nC
––– 2260 ––– TJ = 125°C  
IRRM Reverse Recovery Current ––– 16 ––– A TJ = 25°C 
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by max. junction temperature.
 Limited by TJmax starting TJ = 25°C, L = 0.50mH, RG = 25, IAS = 56A, VGS =10V. Part not recommended for
use above this value.
 ISD 56A, di/dt 950A/µs, VDD V(BR)DSS, TJ  175°C.
 Pulse width 400µs; duty cycle  2%.
 Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
 Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
 Ris measured at TJ approximately 90°C
 RJCvalue shown is at time zero.

2 2016-12-12
 
IRFP4768PbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
100

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)
7.0V 7.0V
6.0V 6.0V
5.5V 5.5V
4.8V 100 4.8V
BOTTOM 4.5V BOTTOM 4.5V
10

1
10
4.5V
0.1
60µs PULSE WIDTH 60µs PULSE WIDTH
4.5V Tj = 25°C Tj = 175°C
0.01 1
0.1 1 10 100 1000 0.1 1 10 100 1000
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 2. Typical Output Characteristics

Fig 1. Typical Output Characteristics

1000 3.5
ID = 56A

R DS(on) , Drain-to-Source On Resistance

3.0 VGS = 10V
ID, Drain-to-Source Current (A)

100 (Normalized)
2.5

2.0
T J = 175°C T J = 25°C
10
1.5

1.0
1

VDS = 50V 0.5

60µs PULSE WIDTH
0.1 0.0
3 4 5 6 7 8 -60 -40 -20 0 20 40 60 80 100 120 140160 180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

14.0
100000 ID= 56A
VGS = 0V, f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED 12.0 VDS = 200V
VGS, Gate-to-Source Voltage (V)

Crss = C gd VDS = 125V

Coss = Cds + Cgd
10.0 VDS = 50V
C iss
C, Capacitance (pF)

10000
8.0
C oss
6.0
Crss
1000 4.0

2.0

0.0
100
0 30 60 90 120 150 180 210 240
1 10 100 1000
QG, Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage

3 2016-12-12
 
IRFP4768PbF
1000 1000
OPERATION IN THIS AREA
ISD, Reverse Drain Current (A) LIMITED BY R DS (on)

ID, Drain-to-Source Current (A)

100 100µsec
T J = 175°C
100
1msec
T J = 25°C
10
10msec

10
DC
1
Tc = 25°C
VGS = 0V Tj = 175°C
Single Pulse
0.1 1
0.0 0.5 1.0 1.5 1 10 100 1000
VSD , Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area

V(BR)DSS , Drain-to-Source Breakdown Voltage (V)

100 320
Id = 5mA

80
300
ID, Drain Current (A)

60
280

40

260
20

240
0 -60 -40 -20 0 20 40 60 80 100 120 140160 180
25 50 75 100 125 150 175
T J , Temperature ( °C )
TC , Case Temperature (°C)

Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Drain-to–Source Breakdown Voltage
20.0
3200
ID
EAS , Single Pulse Avalanche Energy (mJ)

18.0
2800 TOP 12A
16.0
17A
14.0 2400 BOTTOM 56A
12.0
Energy (µJ)

2000
10.0
1600
8.0
1200
6.0

4.0 800

2.0 400
0.0
-50 0 50 100 150 200 250 300 0
25 50 75 100 125 150 175
VDS, Drain-to-Source Voltage (V) Starting T J , Junction Temperature (°C)

Fig 11. Typical Coss Stored Energy Fig 12. Maximum Avalanche Energy vs. Drain Current

4 2016-12-12
 
IRFP4768PbF
1

Thermal Response ( Z thJC ) °C/W

D = 0.50
0.1
0.20
0.10
0.05 R1 R2 R3 Ri (°C/W) I (sec)
0.01 J
R1 R2 R3

0.02 J
C
C 0.0634 0.000278
1 2 3
0.01 1 2 3
0.1109 0.005836
Ci= iRi
Ci= iRi
0.001 0.1148 0.053606
Notes:
SINGLE PULSE 1. Duty Factor D = t1/t2
( THERMAL RESPONSE ) 2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1 1
t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000

Duty Cycle = Single Pulse

Allowed avalanche Current vs avalanche
100 pulsewidth, tav, assuming Tj = 150°C and
Avalanche Current (A)

Tstart =25°C (Single Pulse)

0.01

10 0.05
0.10

1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming  j = 25°C and
Tstart = 150°C.
0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)

Fig 14. Typical Avalanche Current vs. Pulse

800
TOP Single Pulse Notes on Repetitive Avalanche Curves , Figures 14, 15:
BOTTOM 1.0% Duty Cycle (For further info, see AN-1005 at www.irf.com)
700
1. Avalanche failures assumption:
ID = 56A
EAR , Avalanche Energy (mJ)

Purely a thermal phenomenon and failure occurs at a temperature far

600 in excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded.
500 3. Equation below based on circuit and waveforms shown in Figures 22a,22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
400 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
300 6. Iav = Allowable avalanche current.
7. T=Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
200
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
100 ZthJC(D, tav) = Transient thermal resistance, see Figures 13)

0 PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC

25 50 75 100 125 150 175
Starting T J , Junction Temperature (°C) Iav = 2T/ [1.3·BV·Zth]

EAS (AR) = PD (ave)·tav

Fig 15. Maximum Avalanche Energy vs. Temperature

5 2016-12-12
 
IRFP4768PbF
6.0 70
IF = 37A
VGS(th) , Gate threshold Voltage (V)

5.0 60 V R = 200V
TJ = 25°C
TJ = 125°C
4.0 50

IRRM (A)
3.0 ID = 250µA 40
ID = 1.0mA
2.0 ID = 1.0A 30

1.0 20

0.0 10
-75 -50 -25 0 25 50 75 100 125 150 175 0 200 400 600 800 1000
T J , Temperature ( °C ) diF /dt (A/µs)

Fig 16. Threshold Voltage vs. Temperature Fig 17. Typical Recovery Current vs. dif/dt
90 6000
IF = 56A IF = 37A
80 V R = 200V V R = 200V
5000
TJ = 25°C TJ = 25°C
70
TJ = 125°C TJ = 125°C
60 4000
QRR (nC)
IRRM (A)

50
3000
40

30
2000
20

10 1000
0 200 400 600 800 1000 0 200 400 600 800 1000

diF /dt (A/µs) diF /dt (A/µs)

Fig 18. Typical Recovery Current vs. dif/dt Fig 19. Typical Stored Charge vs. dif/dt

8000
IF = 56A
7000 V R = 200V
TJ = 25°C
6000 TJ = 125°C
QRR (nC)

5000

4000

3000

2000

1000
0 200 400 600 800 1000
diF /dt (A/µs)

Fig 20. Typical Stored Charge vs. dif/dt

6 2016-12-12
 
IRFP4768PbF

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs

V(BR)DSS

15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
20V
tp 0.01 I AS

Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms

Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Id
Vds

Vgs

L
VCC
DUT
0 Vgs(th)
1K

Qgs1 Qgs2 Qgd Qgodr

Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform

7 2016-12-12
 
IRFP4768PbF

TO-247AC Package Outline

Dimensions are shown in millimeters (inches)

TO-247AC Part Marking Information

Notes: This part marking information applies to devices produced after 02/26/2001

EXAMPLE: THIS IS AN IRFPE30

WITH ASSEMBLY PART NUMBER
LOT CODE 5657 INTERNATIONAL
ASSEMBLED ON WW 35, 2001 RECTIFIER IRFPE30

IN THE ASSEMBLY LINE "H" LOGO 135H

56 57
DATE CODE
ASSEMBLY YEAR 1 = 2001
Note: "P" in assembly line position
indicates "Lead-Free" LOT CODE WEEK 35
LINE H

TO-247AC package is not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

8 2016-12-12
  
IRFP4768PbF

Qualification Information 
Industrial
Qualification Level   (per JEDEC JESD47F) †

Moisture Sensitivity Level TO-247AC N/A

RoHS Compliant Yes

† Applicable version of JEDEC standard at the time of product release.

Revision History
Date Comments
 Changed datasheet with Infineon logo-all pages
12/12/2016  Corrected error on figure 9 on page 4.
 Added disclaimer on last page.

Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.

IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third
party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of
the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a
failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.

9 2016-12-12