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    Coa Assignment-II VHDL

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    I.A.P. JABH RIDET
    This document outlines an assignment for a computer organization and architecture laboratory course. It instructs students to write VHDL programs to implement various digital circuits, including multiplexers, demultiplexers, encoders, comparators, parity generators and checkers, and flip flops. Students are asked to write the programs on A4 pages and include simulation results for each individual program.

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    Coa Assignment-II VHDL

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    I.A.P. JABH RIDET
    13 views1 page
    This document outlines an assignment for a computer organization and architecture laboratory course. It instructs students to write VHDL programs to implement various digital circuits, including multiplexers, demultiplexers, encoders, comparators, parity generators and checkers, and flip flops. Students are asked to write the programs on A4 pages and include simulation results for each individual program.

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    Coa Assignment-II Vhdl

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    This document outlines an assignment for a computer organization and architecture laboratory course. It instructs students to write VHDL programs to implement various digital circuits, including multiplexers, demultiplexers, encoders, comparators, parity generators and checkers, and flip flops. Students are asked to write the programs on A4 pages and include simulation results for each individual program.

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    © All Rights Reserved
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    13 views1 page

    Coa Assignment-II VHDL

    Uploaded by

    I.A.P. JABH RIDET
    This document outlines an assignment for a computer organization and architecture laboratory course. It instructs students to write VHDL programs to implement various digital circuits, including multiplexers, demultiplexers, encoders, comparators, parity generators and checkers, and flip flops. Students are asked to write the programs on A4 pages and include simulation results for each individual program.

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    Computer Organization & Architecture Laboratory

    Subject Code: PCC-CS492


    ASSIGNMENT – II

    1. Write the VHDL programs to implement multiplexers: 2:1, 4:1, 8:1, 16:1 (using when / if-
    else / vector / testbench).
    2. Write the VHDL programs to implement de-multiplexers: 1:2, 1:4, 1:8, 1:16 (using when /
    if-else / vector / testbench).
    3. Write the VHDL programs to implement encoder circuits: 8:3, 4:2 and priority encoder
    4. Write the VHDL programs to implement binary comparator circuit.
    5. Write the VHDL programs to implement magnitude comparator circuit.
    6. Write the VHDL programs to implement parity generator and parity checker.
    7. Write the VHDL programs to implement flip flop units: SR, JK, D, T.
    Note: Write the program in A4 page and draw the simulation result for every individual
    program. Submit the assignment in channel file.

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