DESIGN OF HIGH PERFORMANCE 1-BIT

HYBRID ADDER (VLSI)

A MINI PROJECT WORK

Submitted in partial fulfillment of the requirements for the award of the
degree of
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
By
Likhitha Kacham 18H61A0428
Vasanth Mekala 18H61A0436
Srujan Patlolla 18H61A0444

Under the Guidance of

Amritha Sajja
Department of ECE

Department of Electronics and Communication Engineering

ANURAG GROUP OF INSTITUTIONS
AUTONOMOUS
SCHOOL OF ENGINEERING
(Affiliated to Jawaharlal Nehru Technological University, Hyderabad)
Venkatapur(V), Ghatkesar(M), Medchal-Malkajgiri Dist-500088
2021-2022

ANURAG GROUP OF INSTITUTIONS

 AUTONOMOUS
SCHOOL OF ENGINEERING
(Affiliated to Jawaharlal Nehru Technological University, Hyderabad
Venkatapur(V),Ghatkesar(M), Medchal-Malkajgiri Dist-500088

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

CERTIFICATE
This is to certify that the project report entitled Design of high performance 1-bit
Hybrid Adder (VLSI) being submitted by

Likhitha Kacham 18H61A0428

Vasanth Mekala 18H61A0436
Srujan Patlolla 18H61A0444

in partial fulfillment for the award of the Degree of Bachelor of Technology in

Electronics & Communication Engineering to the Jawaharlal Nehru Technological
University, Hyderabad is a record of bonafide work carried out under my guidance
and supervision. The results embodied in this project report have not been submitted
to any other University or Institute for the award of any Degree or Diploma.

Amritha Sajja Dr.S.Sathees Kumaran

Head of the Department
DEPT OF ECE

External Examiner

ACKNOWLEDGEMENT
 This project is an acknowledgement to the inspiration, drive and technical assistance
contributed by many individuals. This project would have never seen light of this day without the
help and guidance we have received. We would like to express our gratitude to all the people
behind the screen who helped us to transform an idea into a real application.

It’s our privilege and pleasure to express our profound sense of gratitude to Amritha Sajja,
Guide Department of ECE for her guidance throughout this dissertation work.

We express our sincere gratitude to Dr.S.Sathees Kumaran, Head of Department,

Electronics and Communication Engineering for his precious suggestions for the successful
completion of this project. He is also a great source of inspiration to our work.
We would like to express our deep sense of gratitude to Director, Anurag Group of Institutions
for his tremendous support, encouragement and inspiration. Lastly, we thank almighty, our
parents, friends for their constant encouragement without which this assignment would not be
possible. We would like to thank all the other staff members, both teaching and non- teaching,
which have extended their timely help and eased my work.

BY
LIKHITHA KACHAM 18H61A0428
VASANTH MEKALA 18H61A0436
SRUJAN PATLOLLA 18H61A0444

DECLARATION
We hereby declare that the result embodied in this project report entitled “Design of
high performance 1-bit Hybrid Adder(VLSI)” is carried out by us during the year
2021-2022 for the partial fulfillment of the award of Bachelor of Technology in
Electronics and Communication Engineering, from ANURAG GROUP OF
INSTITUTION. We have not submitted this project report to any other Universities /
Institute for the award of any degree.

BY

Likhitha Kacham 18H61A0428

Vasanth Mekala 18H61A0436
Srujan Patlolla 18H61A0444

ABSTRACT
Technology evolution increased the demand for high performance and energy
efficient circuits.To meet the design criteria for the modern period, circuit designers
are often facing a dilemma to make trade-offs among area, delay and power
consumption.Along with number of devices used in the circuit should be less and
circuit should occupy less area, consume less power is the major challenge for the
designers.

Basic circuit used in most of the circuit designs is an ADDER. In digital addition,Full
Adder works as the most important elementary block.The improved version of the full
adder design brings overall improvement in the arithmetic units.

This project is an 18-transistor full adder cell based on the full swing hybrid
logic.Hybrid Adder is designed using metal oxide semiconductors(CMOS),Pass
Transistors,Transistor gates.This circuit is designed using Cadence tool with 90nm
technology.Further the proposed adder results of propagation delay is compared with
existing Adder circuits.

Major aim to design this circuit is to enhance the performance of the circuit by
decreasing its propagation delay.

CHAPTER 1
 INTRODUCTION

1.1 Introduction:

With transistor scaling and technology evolution, the exploration of high-performance

and energy efficient circuits continues unabated.The search for energy and area
efficient circuits has been further enhanced due to the ubiquitous use of portable
devices.

To meet the design criteria of modern high-performance microprocessors, circuit

designers often fall in a dilemma to make trade-offs among area,delay and power
consumption.As a result,logic realization with the least number of devices and low
area with optimal delay and power has become a major challenge.

The addition operation plays the major role because several complex operations are
dependent on addition.In digital addition,full adder works as the most important
elementary building block.Despite having several existing full adder designs, the urge
for new designs continues to address the increasing throughput requirements.

Each circuit has its own specialization like; a circuit can increase the performance and
other can decrease the usage of area etc.A hybrid Adder which consists of different
elements which altogether works as an adder is preferred than initial adder circuit
design to make the adder reach the requirements.

1.2 AIM OF THE PROJECT:

This project is to design Hybrid Adder using pass transistors, complementary metal
oxide semi conductors(CMOS) and transmission gates. This circuit is implemented
using cadence software. Cadence tool provides great platform to design the circuit and
also to simulate the circuit for the waveform. It also has the feature to calculate
power, delay and other parameters.

The circuit designed in this project used to increase the performance of the adder by
decreasing its delay. Also few parameters of the adder are compared with already
existing Hybrid Adders.

CHAPTER 2
 LITERATURE SURVEY
On the basis of output voltage, full adder circuits are classified into two categories:
Full swing and non full swing. Full swing circuits have output voltage levels equal to
Vdd or gnd without involving threshold voltage drop issue. Non full swing circuits
considers threshold voltage and suffers from threshold voltage drop.

On the basis of logic style, full adder circuits are classified into two categories:
Single logic and hybrid logic. Single logic circuits uses only one logic style whereas
hybrid logic circuits uses at least two logic styles. Pass transistor based single logic
full adder is the oldest circuit of all. But the drawback in this design is its suffers
threshold voltage drop. To overcome this complementary symmetry CMOS(CCMOS)
is designed. But in CCMOS large number of transistors are used which leads to high
area utilization and it consists of high input impedance which results in slower
working of the circuit.

So instead of using single logic circuits, now designers are interested to design the
hybrid circuits of full adder. Main aim to design hybrid logic circuit is to optimize the
above mentioned drawbacks and to bring better performance. Full adder designed
using the combination of CCMOS and Pass Transistors enhanced the signal strength
but it also resulted in speed issue.

The project-LOW-POWER HYBRID 1-BIT FULL ADDER by Parameshwara M.C.,

Srinivasaiah Hc.Major aim of this project is to introduce a Hybrid Adder for low
power consumption applications with high performance. Drawbacks in this circuit
are-The Full Adder uses four transistors to generate the XNOR signal. Later, the XOR
signal was obtained through an inverter. Finally, two separate circuits were developed
for sum and output carry signals that employed XOR‐XNOR signals as inputs. Since
the XOR signal faces one inverter delay more than the XNOR signal, the sum and
carry circuit needs to wait for the computation of the XOR signal which makes the
output signal generation slower.

The project Low-Power High-Speed Hybrid 1-bit Full Adder Circuit by

Partha Bhattacharyya.The main aim of this project is to design Hybrid Adder which
consumes less power and increase speed and decrease the transistor count.It
succeeded to decrease the average power but has a drawback is this circuit produces
high propagation delay.

To overcome all the above issues, full adder structure is formed using XOR-XNOR
circuit simultaneously. But usage of this circuits should be well enough to avoid
signal delay, slower generation of signal. To reduce delays, parallel connection of
XOR-XNOR connection is suitable. But this circuit involves more usage of transistors
which may result in high input impedance.

In order to avoid all these, the circuit we designed consists of transmission gates and
pass transistors. This circuit is constructed in a way to perform XOR and XNOR
operations. This circuit involves at least one full swing path which results to avoid
voltage degradation phenomenon. Circuit also involves parallel combination to reduce
the delay and this circuit does not involve any feedback connection which results in
reduction of delay.

CHAPTER 3
 SOFTWARE AND HARDWARE REQUIREMENTS

3.1 CADENCE TOOL:

3.1.1 INTRODUCTION:

Cadence is an Electronic Design Automation (EDA) environment that integrates

several design tools in a single design suite. This tool involves the process in which it
will use the Cadence tools to design CMOS integrated circuits. It is used to go
through mastering schematic entry, layout, simulation, post layout simulation and
layout versus schematics. Each process will consist in designing and simulating
different microelectronic building blocks that you will reuse in the project.

3.1.2 Setting your environment for running Cadence remotely:

This section will guide through all the steps to run Cadence remotely over SSH
through a Linux terminal.The following steps are:

Step 1: Start a Linux session in the computer Lab PLT-0105 and logon to your Linux
account using your U. Laval IDUL/NIP.

Step 2: Open a new terminal window. Select Applications-> System Tools -> terminal

Step 3: In the terminal window, type

bash-4.0$ ssh -X cmc-node-1.gel.ulaval.ca -l your_username

and press the Enter key. If you get the following message: “Are you sure you want to
continue connecting (yes/no)?” type yes and then press the Enter key.

Step 4: Enter your password and press the Enter key. You should now be connected to
cmcnode-1 over SSH.

Step 5: Create a working directory by typing the following commands into the
terminal:

bash-4.0$ mkdir Labs

bash-4.0$ cd Labs

bash-4.0$ mkdir Lab1

bash-4.0$ cd Lab1

and press the Enter key.

Step 6: For Launching Cadence, type “startCds” in the terminal window and press the
Enter key. From the cmc_kits_view pop-up window, choose the180-nm technology or
90nm technology or any other technology kit and click run.

The Command Interpreter Window (CIW) is opening. The CIW gives an access to
the multiple tools of the Cadence suite.

3.1.3 The Library manager :

A library is a collection of cells, such as NOT, AND, NAND, etc. These cells contain
several views, including “schematic”, “layout”, “extracted” and “symbol”.

Open the Library manager: In the CIW window, go to tools -> library manager. The
library manager window opens, has shown in Fig. 3. The left column is listing the
available libraries for the current kit. The “analogLib” and the “cmosp18” libraries
contain all the necessary components to complete this Lab. The center column is
listing the available cells for each library. A cell is a specific building block i.e. a
circuit that belongs to a specific library. The right column is listing the several
available views of each cell (extracted, layout, schematic, etc.).

 Extracted view: contains a representation of the netlist that has been extracted
from a layout view. 

 Layout view: contains the mask representations of the silicon devices and wiring.


 Schematic view: contains the schematic representation of a cell. 

 Symbol view: contains a symbolic representation of a cell to be instantiated in a

top-level schematic view. 

 Behavioural view: contains a HDL description of the cell.

Create a new library:

After having opened the Library manager, do the following steps to create your new
library:

Step 1: In the Library manager, go to file -> new library. Then, type in the name of
the new library, for example Label1, and click OK.

Step 2: Select “attach to an existing techfile”, and click OK.

Step 3: In the new pop-up window, select “cmosp18” as the technology file, and then
click OK.

The library Label1 is now listed in the Library manager.

3.1.4 Schematic design and simulation:

This is to know,how to create a simple schematic with the Schematic editor and how
to simulate a digital circuit using Spectre. It also explains how to simulate the
characteristics of a CMOS circuit and how to obtain its parameters. In order to work
efficiently with the Schematic editor, there are few direct keys for the most frequently
used commands as shown in table.

Create a new schematic:

Following are the steps to create a new schematic cell view:
Step 1: In the Library manager, select your new Library (Label1), then go to File ->
new -> cell view.
Step 2: In the pop-up window, type in a new cell name, like cmos_image_schem,
make sure to select composer-schematic (selected by default), and click Ok.
Step 3: A schematic editor window appears .

Draw a new schematic:

Following are the steps to create the new schematic:
Step 1: For adding any component in the new schematic, type "i" with the schematic
window opened.
A new pop-up window appears.
Step 2: Click Browse. The Library manager pops up. Select the “Generic13” library.
Select the respective cell, and choose the symbol view.
Step 3: Go back into the schematic window and place the component with a left click
of the mouse.
Step 4: Select this cell in the schematic, and press “q”. In the “instance properties”
window, change Wire size to required width and keep L to 180nm or 90nm according
to the requirements (Fig.5 left), then press Esc to deselect the components.
Step 5: Repeat steps 1-3 to add remaining elements. Select this element in the
schematic, and press “q”. In the “instance properties” window, change W to required
width and keep L to 180nm or 90nm to meet the requirements then press Esc to
deselect the element.
Step 6: Add DC voltage sources to the schematic and wire them up. First, press “i”
and click Browse in the “add new instance” window. In the “Generic”or any
respective library select the “vdc” cell and its symbol view. In the “property” window,
type in “1.8 V” an example for the parameter “dc voltage”. Add required number of
voltage sources in the schematic. Press Esc to deselect any component from the
schematic. Click “w” and start wiring up the circuit. For drawing wires, click on each
terminal (red square) and move the mouse to the other desired terminal.
Step 7: Add a tie down to the common node . Type “i” or use and add select the
“tiedown” cell, symbol view, from the respective Library.
Step 8: Add a net name between the elements or components. To do so, select the
icon in the left menu and type “Vo“ in the “name“ field. Click “Hide“, and place the
net in the schematic. Add the net "Vi" between the gates of the transistors and the
input source using the same procedure.

Step 9: Make sure that your schematic is identical and press “x” to save your work, or
alternatively, select design -> save and check.

3.1.5 Perform a DC simulation :

Step 1: With the schematic window of the test bench opened, go to tool -> analog
environment. The Analog design environment (ADE) window pops up. The
important sections of this tool are described in Table .

Step 2: Choose a model file in order to simulate the circuit with the right parameters.
In the Analog design environment window, go to the Setup menu, select “model
library”, and type in
CMC/kits/cmosp18.5.2/models/spectre/spectre445_mixed/mm018.csc
Step 3: Type in “tt” in the section box and click the add button. Then, click OK
before closing the windows.
Step 4: Go to session -> options and choose AWD for waveform tool. Analog
waveform display (AWD) is a waveform display tool that is included with the spectre
simulator in order to print simulation results.
Step 5: Go to the Analyses menu, select Analyses -> choose. In the Choosing
Analyses window, click dc at Analysis and select save DC operating point. Click OK.
Step 6: Click the traffic green light button to run the simulation. Messages will appear
in the CIW window indicating that the simulation has completed successfully .

3.1.6 Creating the symbol view from the schematic view:

To make a symbol from a schematic view, select design -> create cellview -> from
cellview in the Virtuoso schematic editor with your schematic of the circuit opened.
Click Ok after the “cellview from cellview” dialog box appears. Rearrange pins in the
“symbol generation options” dialog box as follow and click Ok.
Pin position of the schematic
A symbol of the circuit will be created.
 CHAPTER 4
METHODOLOGY
4.1 INTRODUCTION:
Hybrid Adder circuit consists of 18 transistors connected in an order to get the output
as a full adder. Also the simulation waveform is generated to calculate the delay and
to get better understanding of sum and carry circuits.

BLOCK DIAGRAM OF A FULL ADDER:

4.2 THE CIRCUIT DESIGN:

The rough circuit design of the proposed Hybrid Adder is the fig(1).
MODULE-1:
Initially an input circuit “A” is designed and made as first circuit. A circuit adjacent to
the circuit “A” is designed and that circuit is “B”. In the similar fashion circuit “C” is
designed. All these circuits are placed in the same row and are fed with the voltage
source.
MODULE-2:
Output of these circuits “A”, “B” and “C” are connected to the sum circuit and the
respective results are observed using simulation waveform. Also the proper care is
taken to avoid the much overlapping of wires during connections in the circuit for the
better visual of the circuit and to be easily understood just by having glance on it.
MODULE-3:
Output of these circuits “A”, “B” and “C” are connected to the carry circuit and the
respective results are observed using simulation waveform. Also the proper care is
taken to avoid the much overlapping of wires during connections in the circuit for the
better visual of the circuit and to be easily understood just by having glance on it.
Simulation is performed to calculate delay of the circuit and also to have a proper
visual of the respective input and output sub-circuits.
 CHAPTER-5

RESULTS AND DISCUSSION

The major aim of this hybrid full adder circuit is to decrease the propagation delay of
the circuit. The actual design of the circuit using Cadence tool is as follows:

Initial circuit is the input “A” circuit.

The second circuit is the input “B” circuit.

Input “C” circuit is the third circuit.

Below initial circuit is the “Sum” circuit.

Followed by circuit is the “Carry” circuit.

The simulation waveforms of the “sum” and “carry” circuits are as follows :
Delay simulation waveform is as follows:

Delay comparison with few existing circuits:

Project titles Propagation Delay

1.
65.7ps
Hasan,M.,et al,:Design of a scalable
low power 1-bit hybrid full adder
for fast computation.

2.
252.3ps
Partha.Bhattacharyya-Performance
Analysis of a Low-Power High-
Speed Hybrid 1-bit Full Adder
Circuit.

3.Proposed project-DESIGN OF 43.06ps

HIGH PERFORMANCE 1-BIT
HYBRID ADDER
 CHAPTER 6

CONCLUSION AND FUTURE SCOPE

Hybrid Adder using 18 transistors which are of pass transistors, transmission gates
and cmos transistors is successfully designed using cadence tool. The respective sum
and carry waves are also simulated using cadence tool. Propagation delay is also
calculated and the result is compared with few existing designs and the results are
tabulated.

FUTURE SCOPE:

This Hybrid circuit can be used in any logic circuit which mostly concentrates on less
propagation delay which results in high performance of the circuit.
 REFERENCES

1.Parameshwara, M.C., Srinivasaiah, H.C.: Low‐power hybrid 1‐bit fulladder circuit

for energy efficient arithmetic applications. J. Circ. Syst.Comput. 26(1), 1–15 (2017).

2.Bhattacharyya, P., et al.: Performance analysis of a low‐power high‐speed hybrid 1‐

bit full adder circuit. IEEE Trans. Very Large Scale Integr. Syst.23(10), 2001–2008
(2015).

3.Hasan, M., et al.: Comprehensive study of 1‐bit full adder cells: review,performance
comparison and scalability analysis. SN Applied Sciences.3(6), 644 (2021).

4.Kandpal, J., et al.: High‐speed hybrid‐logic full adder using high‐performance 10‐T
XOR–XNOR cell. IEEE Trans. Very Large ScaleIntegr. Syst. 28(6), 1413–1422
(2020).

5.Sharma, A., Sohal, A., Kaur, H.J.: Sleepy CMOS‐sleepy stack (SC‐SS): a novel
high speed, area and power efcient technique for VLSI circuit design. J. Circ.
Syst.Comput. 28(12) (2019).

6.Hasan, M., et al.: Gate diffusion input technique based full swing and scalable 1‐bit
hybrid full adder for high performance applications. Eng.Sci. Technol. An Int. J.
23(6), 1364–1373 (2020).