PIC18F97J60 FAMILY
64/80/100-Pin High-Performance, 1-Mbit Flash
Microcontrollers with Ethernet
Ethernet Features:
• IEEE 802.3 compatible Ethernet Controller
• Integrated MAC and 10Base-T PHY
• 8-Kbyte Transmit/Receive Packet Dual Port Buffer
SRAM
• Receiver and Collision Squelch Circuit
• Supports one 10Base-T Port with Automatic Polarity
Detection and Correction
• Programmable Automatic Retransmit on Collision
• Programmable Padding and CRC Generation
• Programmable Automatic Rejection of Erroneous
Packets
• Activity Outputs for 2 LED Indicators
• Buffer:
- Configurable transmit/receive buffer size
- Hardware-managed circular receive FIFO
- Byte-wide random and sequential access
- Internal DMA for fast memory copying
- Hardware-assisted IP checksum calculation
• MAC:
- Support for Unicast, Multicast and Broadcast
packets
- Programmable pattern matching of up to
64 bytes within packet at user-defined offset
- Programmable wake-up on multiple packet
formats
- Loopback mode
• PHY:
- Wave shaping output filter
- Loopback mode
Flexible Oscillator Structure:
• Selectable system clock derived from single 25 MHz
external source:
- 10 clock speeds from 2.78 to 41.67 MHz
• Internal 31 kHz oscillator
• Secondary oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if oscillator stops
• Two-Speed Oscillator Start-up
External Memory Bus
(100-pin devices only):
• Address capability of up to 2 Mbytes
• 8-bit or 16-bit interface
• 12-bit, 16-bit and 20-bit Addressing modes
© 2005 Microchip Technology Inc. Advance Information
Peripheral Highlights:
• High current sink/source 25 mA/25 mA
• Five Timer modules (Timer0 to Timer4)
• Four external interrupt pins
• Two Capture/Compare/PWM (CCP) modules
• Three Enhanced Capture/Compare/PWM (ECCP)
modules:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-Shutdown and Auto-Restart
• Up to two Master Synchronous Serial Port (MSSP)
modules supporting SPI™ (all 4 modes) and I2C™
Master and Slave modes
• Two Enhanced USART modules:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-Wake-up on Start bit
- Auto-Baud Detect
• 10-bit, up to 16-channel Analog-to-Digital Converter
module (A/D):
- Auto-acquisition capability
- Conversion available during Sleep
• Dual analog comparators with input multiplexing
• Parallel Slave Port (PSP) module
(100-pin devices only)
Special Microcontroller Features:
• 5.5V Tolerant Inputs (digital-only pins)
• Low-power, high-speed CMOS Flash technology:
- Self-reprogrammable under software control
• C compiler optimized architecture for re-entrant code
• Power Management Features:
- Run: CPU on, peripheral on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-Supply 3.3V In-Circuit Serial Programming™
(ICSP™) via two pins
• In-Circuit Debug (ICD) with 3 breakpoints via
two pins
• Operating voltage range of 2.0V to 3.6V (3.14V to
3.45V using Ethernet module)
• On-chip 2.5V regulator
DS39641C-page 1
PIC18F97J60 FAMILY

Comparators

Memory Bus
MSSP
Flash SRAM Ethernet

EUSART

External
10-bit
Program Data TX/RX CCP/ Timers
Device I/O A/D Master PSP
Memory Memory Buffer ECCP SPI™ 8/16 bit
(ch) I2C™
(bytes) (bytes) (bytes)

PIC18F66J60 64 K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N

PIC18F66J65 96 K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N
PIC18F67J60 128 K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N
PIC18F86J60 64 K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N
PIC18F86J65 96 K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N
PIC18F87J60 128 K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N
PIC18F96J60 64 K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y
PIC18F96J65 96 K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y
PIC18F97J60 128 K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y

Pin Diagrams

64-Pin TQFP
RD1/ECCP3/P3A
RD2/CCP4/P3D
RD0/P1B

TPOUT+
RE3/P3C

RE5/P1C
RE2/P2B

RE4/P3B

TPOUT-
VDDPLL

VDDTX
RBIAS
VSSPLL

VSSTX
VSS
VDD

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

RE1/P2C 1 48 VDDRX
RE0/P2D 2 47 TPIN+
RB0/INT0 3 46 TPIN-
RB1/INT1 4 45 VSSRX
RB2/INT2 5 44 RB4/KBI0
RB3/INT3 6 43 RB5/KBI1
MCLR 7 PIC18F66J60 42 RB6/KBI2/PGC
RG4/CCP5/P1D 8 PIC18F66J65 41 VSS
VSS 9 40 OSC2/CLKO
PIC18F67J60
VDDCORE/VCAP 10 39 OSC1/CLKI
RF7/SS 11 38 VDD
RF6/AN11 12 37 RB7/KBI3/PGD
RF5/AN10/CVREF 13 36 RC5/SDO
RF4/AN9 14 35 RC4/SDI/SDA
RF3/AN8 15 34 RC3/SCK/SCL
RF2/AN7/C1OUT 16 33 RC2/ECCP1/P1A

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ENVREG
RF1/AN6/C2OUT

RA2/AN2/VREF-

RC7/RX1/DT1
RA5/AN4

RC6/TX1/CK1
RA3/AN3/VREF+

RC0/T1OSO/T13CKI
RC1/T1OSI/ECCP2/P2A
AVDD

RA1/LEDB/AN1
RA0/LEDA/AN0

VDD

RA4/T0CKI
AVSS

VSS

Pinouts are preliminary and subject to change.

DS39641C-page 2 Advance Information © 2005 Microchip Technology Inc.

 PIC18F97J60 FAMILY
Pin Diagrams (Cont’d.)

80-Pin TQFP

RE7/ECCP2(1)/P2A(1)
RE3/P3C(2)

RE5/P1C(2)
RE4/P3B(2)

RE6/P1B(2)

TPOUT+
RE2/P2B

TPOUT-
VDDPLL

VDDTX
RBIAS
VSSPLL

VSSTX
RD0

RD1
RD2
RH0
RH1

VDD
VSS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

RH2 1 60 VDDRX
RH3 2 59 TPIN+
RE1/P2C 3 58 TPIN-
RE0/P2D 4 57 VSSRX
RB0/INT0 5 56 RG0/ECCP3/P3A
RB1/INT1 6 55 RG1/TX2/CK2
RB2/INT2 7 54 RB4/KBI0
RB3/INT3 8 53 RB5/KBI1
MCLR 9
PIC18F86J60 52 RB6/KBI2/PGC
RG4/CCP5/P1D 10 PIC18F86J65 51 VSS
VSS 11 50 OSC2/CLKO
PIC18F87J60
VDDCORE/VCAP 12 49 OSC1/CLKI
RF7/SS 13 48 VDD
RF6/AN11 14 47 RB7/KBI3/PGD
RF5/AN10/CVREF 15 46 RC5/SDO
RF4/AN9 16 45 RC4/SDI/SDA
RF3/AN8 17 44 RC3/SCK/SCL
RF2/AN7/C1OUT 18 43 RC2/ECCP1/P1A
RH7/AN15/P1B(2) 19 42 RG2/RX2/DT2
RH6/AN14/P1C(2) 20 41 RG3/CCP4/P3D

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
ENVREG
RF1/AN6/C2OUT

RJ4
RJ5
RA2/AN2/VREF-

RC7/RX1/DT1
RA5/AN4

RC1/T1OSI/ECCP2(1)/P2A(1)

RC6/TX1/CK1
RA3/AN3/VREF+

RC0/T1OSO/T13CKI
RH5/AN13/P3B(2)
RH4/AN12/P3C(2)

AVDD

RA1/LEDB/AN1
RA0/LEDA/AN0

VDD

RA4/T0CKI
AVSS

VSS

Pinouts are preliminary and subject to change.

Note 1: The ECCP2/P2A pin placement depends on the CCP2MX configuration bit settings.
2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX configuration bit setting.

© 2005 Microchip Technology Inc. Advance Information DS39641C-page 3

PIC18F97J60 FAMILY
Pin Diagrams (Cont’d.)

100-Pin TQFP

RD6/AD6/PSP6/SCK2/SCL2
RE7/AD15/ECCP2(1)/P2A(1)

RD5/AD5/PSP5/SDI2/SDA2
RD4/AD4/PSP4/SDO2

RD7/AD7/PSP7/SS2
RE2/AD10/CS/P2B

RE5/AD13/P1C(2)
RE4/AD12/P3B(2)

RE6/AD14/P1B(2)
RE3/AD11/P3C(2)

RD0/AD0/PSP0
RD1/AD1/PSP1
RD2/AD2/PSP2
RD3/AD3/PSP3
RH1/A17
RH0/A16

TPOUT+
TPOUT-
VDDPLL
VSSPLL

RBIAS

VDDTX
VSSTX
VDD
VSS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
RH2/A18 1 75 VDDRX
RH3/A19 2 74 TPIN+
RE1/AD9/WR/P2C 3 73 TPIN-
RE0/AD8/RD/P2D 4 72 VSSRX
RB0/INT0 5 71 RG0/ECCP3/P3A
RB1/INT1 6 70 RG1/TX2/CK2
RB2/INT2 7 69 RB4/KBI0
RB3/INT3/ECCP2(1)/P2A(1) 8 68 RB5/KBI1
VSS 9 67 RB6/KBI2/PGC
RG6 10 66 RJ2/WRL
RG5 11 65 VSS
RF0/AN5
PIC18F96J60
12 64 OSC2/CLKO
MCLR 13
PIC18F96J65 63 OSC1/CLKI
RG4/CCP5/P1D 14 PIC18F96J70 62 VDD
VSS 15 61 RJ3/WRH
VDDCORE/VCAP 16 60 VSS
VDD 17 59 VDD
RF7/SS1 18 58 RJ6/LB
RF6/AN11 19 57 RB7/KBI3/PGD
RF5/AN10/CVREF 20 RC5/SDO1
56
RF4/AN9 21 RC4/SDI1/SDA1
55
RF3/AN8 22 RC3/SCK1/SCL1
54
RF2/AN7/C1OUT 23 RC2/ECCP1/P1A
53
RH7/AN15/P1B(2) 24 RG2/RX2/DT2
52
RH6/AN14/P1C(2) 25 RG3/CCP4/P3D
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RA2/AN2/VREF-
ENVREG

RA1/LEDB/AN1
RA0/LEDA/AN0

RG7

RA5/AN4

RC6/TX1/CK1
RC7/RX1/DT1
RA4/T0CKI

RJ4/BA0
RC0/T1OSO/T13CKI
RA3/AN3/VREF+

RJ0/ALE
AVSS

VSS

RJ7/UB
VSS

RJ5/CE

RJ1/OE
RF1/AN6/C2OUT
RH5/AN13/P3B(2)
RH4/AN12/P3C(2)

RC1/T1OSI/ECCP2(1)/P2A(1)
AVDD

VDD

Pinouts are preliminary and subject to change.

Note 1: The ECCP2/P2A pin placement depends on the CCP2MX configuration bit and Processor mode settings.
2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX configuration bit setting.

DS39641C-page 4 Advance Information © 2005 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

© 2005 Microchip Technology Inc. Advance Information DS39641C-page 5

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10/20/04

DS39641C-page 6 Advance Information © 2005 Microchip Technology Inc.