11003 Caminito Alvarez Ph:518-915-8725

San Diego, CA-92126 NARESH ANDUGULAPATHI nareshavvn@gmail.com

SUMMARY
Proactive & result oriented engineer with 10 years of solid Design Verification experience and 5+ years of leading DV
projects from planning to silicon.
WORK EXPERIENCE:
Staff Engineer, Camera Sub System, Qualcomm Inc., San Diego, CA October 2018-present
• 5+ months of managerial experience (direct reports) August 2021-Present
▪ Leading a 6-member team for Design verification of Image processing and Bayer processing pipelines.
▪ Led a 4-member team for Design verification of 4rth generation Image processing core. Collaborate with
teams across 3 different geographic locations.
▪ Led 3-member team for Design verification of second-generation Camera Data Mover module
▪ Solid understanding of hierarchical re-use, OOP, UVM and automation helped in developing the TB and SV
model.
▪ Exceptionally good understanding of CAMERA HW use case flows and image processing pipelines
▪ Great Verification planning skills. Quality work even during tight schedules. Mentor junior engineers.
▪ DV flow and process improvements that helped reduce the execution schedules significantly.
Senior Engineer, Camera Sub System, Qualcomm Inc., San Diego, CA Jan 2016-October 2018
▪ Led 4-member team for Design verification of Third Generation Image processing core in CameraSS
▪ Attended automotive FS & reliability tutorials at DAC-18, had vendor interactions, participated in tool eval
meetings at Qualcomm, part of 2-member team responsible for planning FS verification strategy for the team.
▪ DAC-18: Learnt about few innovative solutions for DV challenges, brought those solutions to the team and
implemented them with vendor support. DAC-18
▪ Design Verification of couple of unit level designs (chroma up sampling, crop/clamp) in Camera subsystem
using UVM/SV TB July 2017-Dec 2017
▪ Part of 2-member team that does Power aware verification of entire Camera Subsystem. Significantly
complex system with around 9 power domains, 5 different supply rails (analog & digital), clock controllers,
PHYs, power domain crossing fifos, memories, etc. Dec 2016-July 2017
▪ IPE core is a complex image processing pipeline that has 52 instances of 32 unique functional blocks (units).
It is a memory-to-memory core that has industry standard interfaces like AHB and AXI. Jan 2016-Dec 2016
▪ The UVM test bench is architected in a way where all components (scoreboard, sequences, coverage) of unit
level environments can be reused at IPE core level.
Senior Engineer, Power DV, Qualcomm Inc., San Diego, CA October 2014-December 2015
• Led a 3-member team for DV of a second-generation Qualcomm Limits Management IP.
• Developed a verification plan that involved detailed execution schedule, resource requirements, risks and
dependencies, feature level test plans, tool dependencies, etc.
• Technical expertise in Block level DV using industry standard methodologies like UVM/OVM.
• Expert in test plan development, feature/unit level model development, coverage, System Verilog assertions.
• Experienced in working with CAD vendors to resolve tool related issues/challenges. For example: Cadence
CtoS generated RTL debug and coverage closure challenges, Synopsys Power Aware verification issues, etc.
• Experienced in pulling off high quality IPs within super tight schedule constraints.
Engineer, Power DV, Qualcomm Inc., San Diego, CA September 2013-October 2014
• As a part of power DV team, I was involved in design verification and power aware verification of various
power management blocks.
• Allowed zero silicon escapes in first generation Qualcomm Limits Management IP that was executed on a
very tight schedule.
• I was also involved in verification of low power features at SOC level, especially power aware verification.
Graphics Hardware Engineer, Intel Corporation, Folsom, CA August 2011-August 2013
As a part of Display Validation Capabilities team, I developed and owned various validation platforms and
components
▪ Developed Unit and Cluster Level OVM/UVM Test bench environments for various 2D display graphics
units. Experience of developing and using Scoreboards, Simulators, RAL
▪ Experienced in building REUSABLE test bench components (BFMs and DPI-C++ checkers)
▪ Ramped up quickly and gained a very good understanding of 2D DISPLAY PIPE, validation flow, tools and
did some support validation for few RTL units
▪ Perl scripting to do some automation
TECHNICAL SKILLS:

• Languages: Experienced in Verilog, System Verilog, C and C++

• Verification Methodologies: UVM, OVM, Power Aware Verification
• Scripting Languages: Perl
• Applications and Tools:
▪ Simulators: Synopsys VCS, Mentor Graphics Modelsim (MTI), Cadence IUS
▪ Waveform Viewers: VPD(DVE), FSDBs (VERDI)
• Operating Systems: UNIX, LINUX, WINDOWS
• Strong programming, debug and troubleshooting skills.
• Other tools: Microsoft project planner, Laboratory Experiments with Oscilloscopes and Logic analyzers

EDUCATION:

North Carolina State University, North Carolina, USA May 2011

Master of Science in Computer Engineering,

Jawaharlal Nehru Technological University, Andhra Pradesh, India May 2009

Bachelor of Technology in Electrical &Electronics Engineering,
RELEVANT COURSES:

ASIC Verification, Digital ASIC Design, Advanced Digital Electronics, VLSI System Design, Computer
Architecture, Digital signal processing, Embedded System Design, Computer Networks.
COURSE PROJECTS:

• Functional Verification of pipelined LC-3 Microcontroller Team Project

Developed a reusable and explicitly layered test bench, in object-oriented environment for the functional
verification of the data and control path of a PIPELINED LC-3 microcontroller with a comprehensive
instruction set. The verification is oriented towards achieving high functional coverage.
Language: System Verilog, Tool: Mentor Graphics Questasim

• Cache and Memory hierarchy design

Designed a flexible cache and memory hierarchy simulator and used it to study the performance of memory
hierarchies using the SPEC benchmarks. Language: C

• Branch Predictors
Constructed a branch predictor simulator for the analysis of branch misprediction rate of a pipelined processor
with bimodal, gshare and hybrid branch prediction techniques. Language: C

• Dynamic Instruction Scheduling

Designed a simulator for an out-of-order superscalar processor based on Tomasulo’s algorithm.
Measured the average no. of instructions completed per cycle (IPC) for peak fetch/dispatch/issue
rates. Language: C

LEADERSHIP EXPERIENCE AND ACTIVITIES:

• Team Lead- Multiple projects Qualcomm

• 8 Qualstar awards (execution, innovation, problem solving) Qualcomm
• Treasurer, IEEE students’ chapter SNIST, India SNIST-2009