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Instructions
AAA
AAD Clock
AAM
AAS
7:46 PM
Jun 27, 51155 (Mon)
ADC
ADD
CMP Copyright
DAA
The Instruction Set Dictionary is subject to copyright protection and may be used
DAS
only for private study by persons who are enrolled in this course. Any other use of
DEC
these materials must be with the express, written permission of any of the course
DIV
instructors from Goa campus
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/[3/9/2019 8:39:50 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT

Program
Execution
Transfer
Instructions
CALL
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
…

PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap
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Arithmetic Instructions - Microprocessors@BITS
Home
Arithmetic Arithmetic Instructions
Instructions
AAA
This page gives info about the various arithmetic instructions available in the Intel
AAD
x86 ISA.
AAM
AAS Subpage Listing
ADC AAA
ADD AAD
CMP AAM
DAA AAS
DAS ADC
DEC
ADD
DIV
CMP
IDIV
DAA
IMUL
DAS
INC
DEC
MUL
NEG DIV
SBB IDIV
SUB IMUL
XADD INC
Bit Manipulation MUL
Instructions NEG
BSWAP
SBB
Logical AND
SUB
Logical NOT
XADD
Logical OR
Logical XOR
Subpages (19):
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
RCL
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
RCR
ROL
Comments
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions[3/9/2019 8:40:20 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

AAA - Microprocessors@BITS
Home Arithmetic Instructions ‎ > ‎

Arithmetic
Instructions AAA
AAA
AAD
ASCII adjust after addition. Addition of two one digit ASCII
AAM
coded number will not be ASCII. To convert the result to
AAS
ASCII, we use AAA after ADD instruction. The result in AX,
ADC
when added to 3030H, gives us ASCII coded sum.
ADD
CMP
USAGE: AAA
DAA
DAS
FLAGS: AF CF (OF,PF,SF,ZF undefined)
DEC
DIV
CLOCKS AND SIZE:
IDIV
IMUL Operands Clock Cycles Size in bytes
INC 8086 80286 80386 80486
MUL none 8 3 4 3 1
NEG
SBB EXAMPLE:
SUB
XADD MOV AL,31H;mov ASCII 1 in AL
Bit Manipulation ADD AL,39H;The ASCII result should be 10 but we get 6AH in AL
Instructions AAA;Adjusts the result and AX now contains 0100H
BSWAP ADD AX,3030H;AX now contains ASCII result 10
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
Comments
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aaa[3/9/2019 8:40:48 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

AAD - Microprocessors@BITS

Arithmetic
Instructions AAD
AAA
AAD AAD stands for ASCII Adjust before Division (or BCD-to-Binary Convert before
AAM
Division). AAD converts two unpacked BCD digits in AH and AL to the equivalent binary
AAS
number in AL. This adjustment must be made before dividing the two unpacked BCD digits
ADC
in AX by an unpacked BCD byte. After the division, AL will contain the unpacked BCD
ADD
quotient and AH will contain the unpacked BCD remainder.
CMP
DAA
Usage AAD
DAS
DEC
Flags PF, SF, ZF
DIV
IDIV
Clocks and Size
IMUL Operands Clocks Size in Bytes
INC 8086 286 386 486
MUL none 60 14 19 14 2
NEG
SBB Example
SUB Divide 67 by 9
XADD
Bit Manipulation MOV AX, 0607H
Instructions MOV CH, 09H
BSWAP
Logical AND AAD ;AX = 0043 = 43H = 67
Logical NOT
Logical OR DIV CH ;Divide AX by unpacked BCD in CH, result: AL = 07 unpacked BCD, AH
Logical XOR = 04 unpacked BCD
RCL
RCR
Comments
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aad[3/9/2019 8:41:24 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

AAM - Microprocessors@BITS

Arithmetic
Instructions AAM
AAA
AAD The AAM mnemonic stands for ASCII adjust for Multiplication or BCD Adjust after
AAM
Multiply. This instruction is used in the process of multiplying two ASCII digits. The
AAS
process begins with masking the upper 4 bits of each digit, leaving an unpacked BCD in
ADC
each byte. These unpacked BCD digits are then multiplied and the AAM instruction is
ADD
subsequently used to adjust the product to two unpacked BCD digits in AX.
CMP
DAA
AAM works only after the multiplication of two unpacked BCD bytes, and it works only on
DAS
an operand in AL.
DEC
DIV
Usage AAM
IDIV
IMUL
Flags PF,SF,ZF
INC
MUL
Clocks and Size
NEG Operands Clocks Size in Bytes
SBB 8086 286 386 486
SUB none 83 16 17 15 2
XADD
Bit Manipulation Example
Instructions Multiply 9 and 5
BSWAP
Logical AND MOV AL, 00000101
Logical NOT MOV BH, 00001001
Logical OR MUL BH ;Result stored in AX
Logical XOR ;AX = 00000000 00101101 = 2DH = 45 in decimals
RCL AAM ;AX = 00000100 00000101 = 0405H = 45 in unpacked BCD
RCR ;If ASCII values are required an OR operation with 3030H can follow this step.
ROL
ROR
Comments
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aam[3/9/2019 8:41:50 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

AAS - Microprocessors@BITS

Arithmetic
Instructions AAS
AAA
AAD ASCII ADJUST FOR SUBTRACTION:
AAM
AAS DESCRIPTION:Corrects result of a previous unpacked ASCII
ADC subtraction in AX.
ADD
USAGE: AAS
CMP
FLAGS:AF CF (OF,PF,SF,ZF undefined)
DAA
DAS
CLOCKS AND SIZES:
DEC
DIV Operands Clock Cycles Size in bytes
IDIV 8086 80286 80386 80486
IMUL none 8 3 4 3 1
INC
MUL EXAMPLE:
NEG
SBB MOV AX,39H ; Load ASCII 9
SUB SUB AL,31H ; Subtract ASCII 1
XADD AAS ; Adjust difference
Bit Manipulation ADD AX,3030H ; Answer in ASCII
Instructions
BSWAP
Logical AND
Comments
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/aas[3/9/2019 8:42:19 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

ADC - Microprocessors@BITS

Arithmetic
Instructions ADC
AAA
AAD It carries out the addition of source and destination, storing
AAM the result in the destination.
AAS If CF is set, a 1 is added to the destination.
ADC
ADD
USAGE: ADC dest,src
CMP
dest-mem/reg
DAA
src -mem/reg/imm
DAS
DEC Note: The only types of addition not allowed are memory to memory and segment
DIV register.
IDIV
IMUL FLAGS: AF CF OF PF SF ZF
INC
MUL
NEG CLOCKS AND SIZE:
SBB
SUB
Operands Clock Cycles Size in bytes
XADD
8086 80286 80386 80486
Bit Manipulation reg,reg 3 2 2 1 2
Instructions mem,reg 16+EA 7 6 3 2-4
BSWAP reg,mem 9+EA 7 7 2 2-4
Logical AND mem,immed 17+EA 7 7 3 3-4
reg,immed 4 3 2 1 3-6
Logical NOT
accum,immed 4 3 2 1 2-3
Logical OR
Logical XOR
RCL
EXAMPLES:
RCR
ROL
ADC AL,BL; AL=AL+BL+carry
ROR
ADC CL,44h;CL=CL+44h+carry
SAR
ADC [BX],AL;AL adds byte contents of the data segment memory
SHL/SAL
location addressed by BX
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/adc[3/9/2019 8:42:48 PM]

with the sum stored in the same memory location.

SHRD/SHLD
Carry is also added to destination if CF is set.
Data Transfer
ADC BX,[SI+2];The word contents of the data segment memory
CMPXCHG
location addressed by SI+2
LAHF
add to BX with the sum stored in BX.Carry is also
LAR
added to destination if CF is set.
LDS/LES
ADC BX,TEMP[DI];The word contents of the data segment memory
LEA
location addressed by TEMP+DI
MOV
add to BX with the sum stored in BX. Carry is also
MOVS
added to destination if CF is set.
MOVSX [386+]
MOVZX
SAHF Comments
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

ADD - Microprocessors@BITS

Arithmetic
Instructions ADD
AAA
AAD It carries out the addition of source and destination, storing
AAM the result in the destination.
AAS
ADC USAGE: ADD dest,src
ADD dest-mem/reg
CMP
src -mem/reg/imm
DAA
DAS Note: The only types of addition not allowed are memory to memory and segment
DEC register.
DIV
IDIV FLAGS: AF CF OF PF SF ZF
IMUL
INC
MUL CLOCKS AND SIZE:
NEG
SBB
SUB
8086 80286 80386 80486
XADD reg,reg 3 2 2 1 2
Bit Manipulation mem,reg 16+EA 7 6 3 2-4
Instructions reg,mem 9+EA 7 7 2 2-4
BSWAP mem,immed 17+EA 7 7 3 3-4
reg,immed 4 3 2 1 3-6
Logical AND
Logical NOT
Logical OR
Logical XOR
EXAMPLES:
RCL
RCR
ADD AL,BL; AL=AL+BL
ROL
ADD CL,44h;CL=CL+44h
ROR
ADD [BX],AL;AL adds byte contents of the data segment memory
SAR
location addressed by BX
SHL/SAL
with the sum stored in the same memory location
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/add[3/9/2019 8:43:18 PM]

ADD BX,[SI+2];The word contents of the data segment memory

SHRD/SHLD
location addressed by SI+2
Data Transfer
add to BX with the sum stored in BX
CMPXCHG
ADD BX,TEMP[DI];The word contents of the data segment memory
LAHF
location addressed by TEMP+DI
LAR
add to BX with the sum stored in BX
LDS/LES
ADD BYTEPTR[DI],3;A 3 adds to the byte contents of the data
LEA
segment memory location addressed
MOV
by DI with the sum stored in the same location
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT Comments
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

CMP - Microprocessors@BITS

Arithmetic
Instructions CMP
AAA
AAD COMPARE
AAM
AAS DESCRIPTION:Subtracts source from destination and updates the fl
ADC not save result. Flags can subsequently be checked for conditio
ADD USAGE: CMP dest,src
CMP
dest-mem/reg/immed
DAA src-mem/reg/immed
DAS
FLAGS:AF CF OF PF SF ZF
DEC
CLOCKS AND SIZES:
DIV
IDIV Operands Clock Cycles Size in bytes
8086 80286 80386 80486
IMUL
reg,reg 3 2 2 1 2
INC
mem,reg 9+EA 7 5 2 2-4
MUL reg,mem 9+EA 6 6 2 2-4
NEG mem,immed 10+EA 6 5 2 3-6
SBB reg,immed 4 3 2 1 3-4
SUB accum,immed 4 3 2 1 2-3
XADD
EXAMPLES:
Bit Manipulation
Instructions
BSWAP CMP CL,BL : CL-BL and flags updated
Logical AND CMP AX,2000H: AX-2000H and flags updated
Logical NOT CMP [DI],CH: CH is subtracted from the byte contents of the
Logical OR data segment addressed by DI and flags updated.
Logical XOR CMP AH,[1234H] : The byte contents of data memory location
RCL 1234h is subtracted from AH and flags updated.
RCR
ROL
ROR Comments
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/cmp[3/9/2019 8:43:56 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

DAA - Microprocessors@BITS

Arithmetic
Instructions DAA
AAA
AAD Decimal adjust after addition. This instruction follows ADD or
AAM ADC to adjust the result into BCD result.
AAS This instruction works only with the AL registers and so must
ADC occur 8 bits at a time.
ADD
CMP USAGE: DAA
DAA
DAS
DEC
DIV
EXAMPLE
IDIV
IMUL
MOV DX,1234H ; load 1234H BCD
INC
MOV BX,3099H ;load 3099H BCD
MUL
MOV AL,BL ;only AL register can be used for DAA
NEG
ADD AL,DL ;
SBB
DAA ;result is BCD adjusted
SUB
MOV CL,AL ;mov result into CL
XADD
MOV AL,BH ;
Bit Manipulation
ADC AL,DH ;
Instructions
DAA ;result is BCD adjusted
BSWAP
mov CH,AL ;now CX contains the sum in BCD format as 4333
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL Comments
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/daa[3/9/2019 8:44:24 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

DAS - Microprocessors@BITS

Arithmetic
Instructions DAS
AAA
AAD DECIMAL ADJUST AFTER SUBTRACTION
AAM
AAS DESCRIPTION:This instruction follows the SUB or SBB
ADC instruction to adjust the difference to a BCD result.DAS works
ADD only with AL register, hence subtraction must occur 8 bits at
CMP a time.
DAA
DAS USAGE:DAS
DEC
DIV
IDIV
IMUL
EXAMPLE:
INC
MUL
MOV DX, 1234H ; load 1234 BCD
NEG
MOV BX, 3099H ; load 3099 BCD
SBB
MOV AL,BL
SUB
SUB AL,DL ; subtract DL from BL
XADD
DAS ; decimal adjust
Bit Manipulation MOV CL,AL ; answer in CL
Instructions
MOV AL,BH
BSWAP
SBB AL,DH ; subtract CH with borrow
Logical AND
DAS ; decimal adjust
Logical NOT
MOV CH,AL ; answer in CH
Logical OR
Logical XOR
RCL Comments
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/das[3/9/2019 8:44:53 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

DEC - Microprocessors@BITS

Arithmetic
Instructions DEC
AAA
AAD DESCRIPTION: Decrement subtracts 1 from a register or a memory
AAM location. DEC instruction subtracts 1 from any register or
AAS memory location, except segment register.
ADC
ADD USAGE: DEC dest
CMP dest-mem/reg
DAA

DAS FLAGS: AF OF PF SF ZF
DEC
DIV
CLOCKS AND SIZES:
IDIV
IMUL
EXAMPLES:
INC
MUL
DEC BL; BL=BL-1
NEG
DEC BYTEPTR[BX];Subtracts 1 from the byte contents of data
SBB
segment memory location addressed by BX
SUB
XADD
Bit Manipulation Comments
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/dec[3/9/2019 8:45:22 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

DIV - Microprocessors@BITS

Arithmetic
Instructions DIV
AAA
AAD The DIV instruction is used to divide an unsigned word (doubleword) by a byte (word).
AAM
AAS For word-byte division, the word must be in the AX register; the divisor can be in a reg or a
ADC mem location. After the division, AL contains the quotient and AH contains the remainder.
ADD Division by zero or a quotient larger than can fit into AL (FFH) raises a Type 0 Interrupt.
CMP
DAA For a doubleword-word division, the most significant word must be in the DX register and the
DAS least significant word in the AX register. Post-division, AX contains the quotient and DX the
DEC remainder.
DIV
IDIV
Division of a byte by a byte is done by putting the dividend byte in AL and filling AH with
IMUL
zeros. A similar analogy can be applied to word-word division.
INC
MUL
If the divisor does not divide the dividend exactly, the quotient is truncated, not round
NEG
SBB
Usage DIV Source
SUB
XADD
Flags None
Bit Manipulation
Instructions
Clocks and Size
BSWAP
Operands Clocks Size in Bytes
Logical AND 8086 286 386 486
Logical NOT reg8 80-90 14 14 16 2
Logical OR reg16 144-162 22 22 24 2
Logical XOR reg32 - - 38 40 2

mem8 86-96 (+EA) 17 17 16 2 - 4
RCL
mem16 150-168 (+EA) 25 25 24 2 - 4
RCR mem32 - - 41 40 2 - 4
ROL
ROR Example
SAR
SHL/SAL DIV BL ;Divide a word in AX with a byte in BL. Quotient in AL, remainder in AH
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/div[3/9/2019 8:45:50 PM]

SHRD/SHLD
Data Transfer Comments
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

IDIV - Microprocessors@BITS

Arithmetic
Instructions IDIV
AAA
AAD This instruction is used to divide a signed word (doubleword) by a signed byte (word).
AAM
The locations of quotients, remainders, dividends and divisors are the same as in the DIV
AAS instruction; the sign of the remainder is the same as that of the dividend.
ADC
ADD Division by zero and quotient values > 128 or <-127 result in a Type 0 Interrupt. (The range
CMP for 186+ is -128 to +127).
DAA
DAS For byte-byte (word-word) divisions, AH (DX) must be sign extended with the same sign as
DEC the AL (AX) byte (word).
DIV
IDIV
Usage IDIV Source
IMUL
INC
Flags Undefined
MUL
NEG
Clocks and Size
SBB Operands Clocks Size in Bytes
SUB 8086 286 386 486
XADD reg8 101-112 17 19 19 2
Bit Manipulation reg16 165-184 25 27 27 2
Instructions reg32 - - 43 43 2
mem8 107-118 (+EA) 20 22 20 2 - 4
BSWAP
mem16 171-190 (+EA) 38 30 28 2 - 4
Logical AND mem32 - - 46 44 2 - 4
Logical NOT
Logical OR Example
Logical XOR IDIV BP ;Signed doubleword in DX and AX divided by signed word in BP
RCL
RCR
ROL Comments
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/idiv[3/9/2019 8:46:16 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

IMUL - Microprocessors@BITS

Arithmetic
Instructions IMUL
AAA
AAD This insruction multilplies a signed byte (word) from a source with a signed byte (word) in
AAM AL (AX).
AAS
ADC All details of IMUL are exactly the same as that of MUL, except that if all bits of the
ADD destination are not used by the result, the result is sign extended. The OF and the CF are
CMP both set to 1 if the upper byte (word) of a 16-bit (32-bit) prodct contains part of the product.
DAA
DAS
Usage IMUL Source
DEC
DIV
Flags OF, CF
IDIV
IMUL
Clocks and Size
INC Operands Clocks Size in Bytes
MUL 8086 286 386 486
NEG reg8 80-98 13 9 - 14 13-18 2
SBB reg16 128-154 21 9 - 22 13-26 2

reg32 - - 9-38 12-42 2
SUB
mem8 86-104 16 12 - 17 13-18 2-4
XADD mem16 134-160 24 12 - 25 13-26 2-4
Bit Manipulation mem32 - 12 - 41 13-42 2-4
Instructions reg16,reg16 - - 9 - 22 13-26 3-5
BSWAP reg32,reg32 - - 9-38 13-42 3-5
Logical AND reg16,mem16 - - 12 - 25 13-26 3-5

reg16,immed - 21 9 - 22 13-26 3
Logical NOT
reg32,immed - 21 9-38 13-42 3-6
Logical OR reg16,reg16,immed - 2 9 - 22 13-26 3-6
Logical XOR reg32,reg32,immed - 21 9-38 13-42 3-6
RCL reg16,mem16,immed - 24 12 - 25 13-26 3-6
RCR reg32,mem32,immed - 24 12-41 13-42 3-6
ROL
ROR Example
SAR
SHL/SAL IMUL AX ;AX times AX, result in DX and AX
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/imul[3/9/2019 8:46:45 PM]

SHRD/SHLD Comments
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

INC - Microprocessors@BITS

Arithmetic
Instructions INC
AAA
AAD Increment addition adds 1 to a register or a memory location.
AAM INC instruction adds 1 to any register or memory location,
AAS except segment register.
ADC
ADD USAGE: INC dest
CMP dest-mem/reg
DAA

DAS FLAGS: AF OF PF SF ZF
DEC
DIV
IDIV CLOCKS AND SIZE:
IMUL
INC Operands Clock Cycles Size in bytes
MUL 8086 80286 80386 80486
NEG reg8 3 2 2 1 2
SBB reg16 3 2 2 1 1
reg32 3 2 2 1 1
SUB
mem 15+EA 7 6 3 2-4
XADD
Bit Manipulation
EXAMPLES:
Instructions
INC BL; BL=BL+1
BSWAP
INC BYTEPTR[BX];Adds 1 to the byte contents of data segment
Logical AND
memory location addressed by BX
Logical NOT
Logical OR
Logical XOR
RCL Comments
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/inc[3/9/2019 8:47:14 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

MUL - Microprocessors@BITS

Arithmetic
Instructions MUL
AAA
AAD This instruction multiplies an unsigned byte (word) from some source with an unsigned
AAM byte (word) in the AL (AX) register.
AAS The source can be a register or a memory location addressed by any of the 24 standard
ADC modes of addressing.
ADD
CMP When doing byte-multiplication, the result is stored in a 16-bit location AX since the result
DAA can be as large as 16 bits. Word-multiplication results in the most significant word being
DAS placed in the DX register and the least significant word placed in the AX register.
DEC
DIV If the most significant byte (word) of a 16-bit (32-bit) result is zero, both CF and OF will be
IDIV zero.
IMUL
INC
Usage MUL Source
MUL
NEG
Flags OF,CF
SBB
SUB
Clocks and Size
XADD Operands Clocks Size in Bytes
Bit Manipulation 8086 286 386 486
Instructions reg8 70-77 13 9 - 14 13-18 2
BSWAP reg16 118-133 21 9 - 14 13-26 2
Logical AND reg32 - - 9-38 13-42 2-4

mem8 76-83 (+ EA) 16 12 - 17 13-18 2-4
Logical NOT
mem16 124-139 (+EA) 24 13-26 12 - 25 2-4
Logical OR mem32 - - 12 - 21 13-42 2 - 4
Logical XOR
RCL Example
RCR
ROL MUL CX ; AX times CX, result high word in DX and low word in AX
ROR
SAR
SHL/SAL Comments
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/mul[3/9/2019 8:47:43 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

NEG - Microprocessors@BITS

Arithmetic
Instructions NEG
AAA
AAD TWO COMPLEMENTS' NEGATION
AAM
AAS DESCRIPTION:Subtracts the destination from 0 and saves the 2s co
ADC "dest" back into "dest".
ADD USAGE:NEG dest
CMP
dest-mem/reg
DAA
DAS FLAGS:AF CF OF PF SF ZF
DEC CLOCKS AND SIZES:

IDIV 8086 80286 80386 80486
IMUL reg 3 2 2 1 2
INC mem 16+EA 7 6 3 2-4
MUL
NEG EXAMPLES:
SBB
SUB NEG AX : AX is two's complemented
XADD NEG BYTE PTR[BX] : The byte contents of the data segment
Bit Manipulation memory location addressed by BX are two's complemented.

Instructions
BSWAP
Logical AND
Logical NOT
Logical OR Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/neg[3/9/2019 8:48:09 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

SBB - Microprocessors@BITS

Arithmetic
Instructions SBB
AAA
AAD SUBTRACT WITH BORROW/CARRY
AAM
AAS DESCRIPTION:Subtracts the source from the destination, and subtr
ADC the Carry Flag is set.Results are returned in "dest".
ADD USAGE: SBB dest,src
CMP
dest-mem/reg/immed
DAA src-mem/reg/immed
DEC
CLOCKS AND SIZE:
DIV
IDIV
8086 80286 80386 80486
IMUL
reg,reg 3 2 2 1 2
INC mem 16+EA 7 6 3 2-4
NEG mem,immed 17+EA 7 7 3 3-6
SBB reg,immed 4 3 2 1 3-4

SUB
XADD
Bit Manipulation
Instructions
BSWAP EXAMPLES:
Logical AND SBB AX,BX : AX=AX-BX-carry

Logical NOT SBB CL,2 : CL=CL-2-carry
SBB [DI],AL: Both AL and carry subtract from the data segment
Logical OR memory location addressed by DI
SBB BYTE PTR[DI],3: Both 3 and carry are subtracted from the
Logical XOR memory byte data addressed by DI.
RCL
RCR
Comments
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/sbb[3/9/2019 8:48:35 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

SUB - Microprocessors@BITS

Arithmetic
Instructions SUB
AAA
AAD This instruction subtracts the source from the destination and
AAM stores the result back into the destination
AAS USAGE: SUB dest,src

dest-mem/reg
ADC src mem/reg/imm
ADD
CMP Note: The only types of subtraction not allowed are memory to memory and
DAA segment register.
DEC CLOCKS AND SIZE:
IDIV 8086 80286 80386 80486
IMUL reg,reg 3 2 2 1 2
INC mem 16+EA 7 6 3 2-4
reg,mem 9+EA 7 7 2 2-4
MUL
mem,immed 17+EA 7 7 3 3-6
NEG
reg,immed 4 3 2 1 3-4
SBB accum,immed 4 3 2 1 2-3
SUB
XADD EXAMPLES:
Bit Manipulation
Instructions SUB AL,BL; AL=AL-BL
BSWAP SUB CL,44h;CL=CL-44h
Logical AND SUB [BX],AL;Subtracts AL from byte contents of the data
Logical NOT segment memory location addressed by BX
Logical OR with the differnce stored in the same memory
Logical XOR location
RCL SUB BX,[SI+2];The word contents of the data segment memory
RCR location addressed by SI+2
ROL are subtracted from BX with the difference stored
ROR in BX
SAR ADD BX,TEMP[DI];The word contents of the data segment memory
SHL/SAL location addressed by TEMP+DI
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/sub[3/9/2019 8:49:05 PM]

are subtracted from BX with the difference stored

SHRD/SHLD in BX
Data Transfer
CMPXCHG
LAHF Comments
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

XADD - Microprocessors@BITS

Arithmetic
Instructions XADD
AAA
AAD EXCHANGE AND ADD (486+ )
AAM
AAS DESCRIPTION: The XADD instruction adds the source to the
ADC destination and stores the sum in the destination, as with any
ADD addition. The difference is that after the addition takes
CMP place, the original value of the destination is copied into
DAA source operand.
DAS
DEC USAGE: XADD dest, src
DIV
IDIV FLAGS: AF CF OF PF SF ZF
IMUL
INC CLOCKS AND SIZES:
MUL
NEG 8086 80286 80386 80486
SBB reg,reg 3 2
SUB mem,reg 4 2-4
XADD
Bit Manipulation EXAMPLE:
Instructions
BSWAP If BL=12H and DL=02H,
Logical AND XADD BL,DL
Logical NOT
Logical OR Now BL= 14H and DL= 12H
Logical XOR
RCL
RCR
ROL
Comments
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/arithmetic-instructions/xadd[3/9/2019 8:49:33 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Bit Manipulation Instructions - Microprocessors@BITS
Home
Arithmetic Bit Manipulation Instructions
Instructions
AAA
This page gives information about various logical instructions which manipulate data
AAD
at binary bit level.
AAM
AAS Subpage Listing
ADC BSWAP
ADD Logical AND
CMP Logical NOT
DAA Logical OR
DAS Logical XOR
DEC RCL
DIV
RCR
IDIV
ROL
IMUL
ROR
INC
SAR
MUL
NEG SHL/SAL
SBB SHR
SUB SHRD/SHLD
XADD
Bit Manipulation
Instructions Subpages (13):
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
BSWAP RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
SHRD/SHLD
Logical AND
Logical NOT Comments
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions[3/9/2019 8:50:02 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

BSWAP - Microprocessors@BITS
Home Bit Manipulation Instructions ‎ > ‎

Arithmetic
Instructions BSWAP
AAA
AAD BYTE SWAP(486+)
AAM
AAS DESCRIPTION:
ADC Changes the byte order of a 32 bit register from big endian to
ADD little endian or vice versa. Result left in destination regist
is undefined if the operand is a 16 bit register.
CMP
DAA
USAGE: BSWAP reg32
DAS reg32- 32 bit register
DEC
FLAGS:NONE
DIV
CLOCKS AND SIZES:
IDIV
INC 8086 80286 80386 80486

reg32 - - - 1 2
MUL
NEG
EXAMPLES:
SBB
SUB
If EAX is 12345678H
XADD
Bit Manipulation
BSWAP EAX results in EAX being 78563412H.
Instructions
BSWAP
Logical AND Comments
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/bswap[3/9/2019 8:50:30 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Logical AND - Microprocessors@BITS

Arithmetic
Instructions Logical AND
AAA
AAD DESCRIPTION:
AAM Performs a logical AND of the two operands replacing the destina
AAS with the result.
ADC USAGE: AND dest,src
ADD dest-mem/reg
CMP src-imm/reg/mem
DAA
DAS Note: AND instruction uses any addressing mode except memory to memory and
DEC segment register addressing.
DIV
IDIV FLAGS: CF OF PF SF ZF (AF undefined)
IMUL
INC CLOCKS AND SIZE:
MUL
NEG
8086 80286 80386 80486
SBB
reg,reg 3 2 2 1 2
SUB mem,reg 16+EA 7 7 3 2-4
XADD reg,mem 9+EA 7 6 1 2-4
Bit Manipulation mem,immed 17+EA 7 7 3 3-6
Instructions reg,immed 4 3 2 1 3-4
BSWAP
Logical AND
EXAMPLE:
Logical NOT
AND AX,BX; AX = AX and BX
Logical OR
AND DI,3333H; DI=DI and 3333H
Logical XOR
AND AX,[DI]; The word contents of the memory location
RCL
addressed by DI are ANDed with AX
RCR
AND ARRAY[SI],AL; The byte contents of memory location
ROL
addressed by ARRAY plus SI are ANDed with AL
ROR
AND [EAX],CL; CL is ANDed with the byte contents of the memory
SAR
location addressed by EAX
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-and[3/9/2019 8:50:56 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA Comments
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Logical NOT - Microprocessors@BITS

Arithmetic
Instructions Logical NOT
AAA
AAD DESCRIPTION: Inverts the bits of the operand by taking it's
AAM one's complement.
AAS USAGE: NOT dest

ADC dest-mem/reg
ADD
CMP FLAGS: none
DAA
DAS CLOCKS AND SIZE:
DEC
DIV
8086 80286 80386 80486
IDIV reg 3 2 2 1 2
IMUL mem 16+EA 7 6 3 2-4
INC
MUL EXAMPLE:
NEG NOT AX ;AX is one's complemented
SBB NOT TEMP ;Contents of memory location TEMP is one's
SUB complemented
XADD NOT BYTE PTR[Var];Byte contents of memory location addressed
Bit Manipulation by variable are one's complemented
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL Comments
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-not[3/9/2019 8:51:24 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Logical OR - Microprocessors@BITS

Arithmetic
Instructions Logical OR
AAA
AAD DESCRIPTION: Performs a logical OR
AAM of the two operands replacing the destination
AAS with the result. Any bit set in either operand will be set in
ADC the destination.
ADD
CMP USAGE: OR dest,src
dest-mem/reg
DAA
src-imm/reg/mem
DAS
DEC
Note: OR instruction uses any addressing mode except memory to memory and
DIV segment register addressing.
IDIV
IMUL FLAGS: CF OF PF SF ZF (AF undefined)
INC
NEG
SBB Operands Clock Cycles Size in bytes
SUB 8086 80286 80386 80486
XADD reg,reg 3 2 2 1 2
mem,reg 16+EA 7 7 3 2-4
Bit Manipulation
reg,mem 9+EA 7 6 2 2-4
Instructions
mem8,immed8 17+EA 7 7 3 3-6
BSWAP mem16,immed16 25+EA 7 7 3 3-6
Logical AND reg,immed 4 3 2 1 3-4
Logical NOT accum,immed 4 3 2 1 2-3
Logical OR
Logical XOR EXAMPLE:
RCL OR AX,BX; AX=AX or BX
RCR OR DI,3333H; DI=DI or 3333H
ROL OR AX,[DI]; The word contents of the memory location addressed
ROR by DI are ORed with AX
SAR OR ARRAY[SI],AL; The byte contents of memory location
SHL/SAL addressed by ARRAY plus SI are ORed with AL
SHR OR [EAX],CL; CL is ORed with the byte contents of the memory
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-or[3/9/2019 8:51:53 PM]

SHRD/SHLD location addressed by EAX

Data Transfer
CMPXCHG
Comments
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Logical XOR - Microprocessors@BITS

Arithmetic
Instructions Logical XOR
AAA
AAD DESCRIPTION: Performs bitwise exclusive-OR
AAM of the two operands replacing the destination
AAS with the result.
ADC
ADD USAGE: XOR dest,src
dest-mem/reg
CMP
src-imm/reg/mem
DAA
DAS
Note: XOR instruction uses any addressing mode except memory to memory and
DEC segment register addressing.
DIV
IDIV FLAGS: CF OF PF SF ZF (AF undefined)
IMUL
INC CLOCKS AND SIZE:
MUL
NEG Operands Clock Cycles Size in bytes
SBB 8086 80286 80386 80486
SUB reg,reg 3 2 2 1 2
mem,reg 16+EA 7 6 3 2-4
XADD
reg,mem 9+EA 7 6 2 2-4
Bit Manipulation mem,immed 17+EA 7 7 3 3-6
Instructions reg,immed 4 3 2 1 3-4
BSWAP accum,immed 4 3 2 1 2-3
Logical AND
Logical NOT EXAMPLE:
Logical OR XOR AX,BX; AX=AX xor BX
Logical XOR XOR DI,3333H; DI=DI xor 3333H
RCL XOR AX,[DI]; The word contents of the memory location
RCR addressed by DI are Exclusive-ORed with AX
ROL XOR ARRAY[SI],AL; The byte contents of memory location
ROR addressed by ARRAY plus SI are Exclusive-ORed
SAR with AL
SHL/SAL XOR [EAX],CL; CL is Exclusive-ORed with the byte contents of
SHR the memory location addressed by EAX
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/logical-xor[3/9/2019 8:52:23 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
Comments
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

RCL - Microprocessors@BITS

Arithmetic
Instructions RCL
AAA
AAD ROTATE THROUGH CARRY LEFT
AAM
AAS DESCRIPTION:
ADC
ADD .-. .---------------.
CMP .--|C|<----|7 <---------- 0|<-.
| '-' '---------------' |
DAA '-----------------------------'
Rotates the bits in the destination to the left "count" times wi
DAS all data pushed out the left side re-
DEC entering on the right. The
Carry Flag holds the last bit rotated out.
DIV
USAGE:RCL dest,count
IDIV
dest-mem/reg
IMUL
INC FLAGS:CF OF
MUL
CLOCKS AND SIZE:
NEG
SBB Operands Clock Cycles Size in bytes
8086 80286 80386 80486
SUB
reg,1 2 2 9 3 2
XADD mem,1 15+EA 7 10 4 2-4
Bit Manipulation reg,CL 8+4n 5+n 9 8 - 30 2
Instructions mem,CL 20+EA+4n 8+n 10 9 - 31 2-4
BSWAP reg,immed8 - 5+n 9 8 - 30 3
Logical AND mem,immed8 - 8+n 10 9 - 31 3-5
Logical NOT
Logical OR EXAMPLES:
Logical XOR
RCL RCL,BX,6 : BX rotates left through carry 6 places
RCR RCL AH,CL : AH rotates left through carry by the number
ROL specified in CL
ROR RCL BYTE PTR[BX],10 :Byte contents of memory location
SAR addressed by BX is rotated left through carry by 10 places
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/rcl[3/9/2019 8:52:53 PM]

SHRD/SHLD
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

RCR - Microprocessors@BITS

Arithmetic
Instructions RCR
AAA
AAD ROTATE THROUGH CARRY RIGHT
AAM
AAS DESCRIPTION:
ADC
ADD .---------------. .-.
CMP .->|7 ----------> 0|---->|C|--.
| '---------------' '-' |
DAA '-----------------------------'
Rotates the bits in the destination to the right "count" times w
DAS all data pushed out the right side re-
DEC entering on the left. The
Carry Flag holds the last bit rotated out.
DIV
USAGE: RCR dest,count
IDIV
IMUL dest-mem/reg
INC FLAGS: CF OF
MUL
NEG CLOCKS AND SIZE:
SBB
SUB
8086 80286 80386 80486
XADD reg,1 2 2 9 3 2
Bit Manipulation mem,1 15+EA 7 10 4 2-4
Instructions reg,CL 8+4n 5+n 9 8 - 30 2
BSWAP mem,CL 20+EA+4n 8+n 10 9 - 31 2-4
Logical AND reg,immed8 - 5+n 9 8 - 30 3

mem,immed8 - 8+n 10 9 - 31 3-5
Logical NOT
Logical OR
EXAMPLES:
Logical XOR
RCL
RCR,BX,6 : BX rotates right through carry 6 places
RCR
RCR AH,CL : AH rotates right through carry by the number
ROL
specified in CL
ROR
RCR BYTE PTR[BX],10 :Byte contents of memory location
SAR
addressed by BX is rotated right through carry by 10 places
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/rcr[3/9/2019 8:53:18 PM]

SHRD/SHLD
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

ROL - Microprocessors@BITS

Arithmetic
Instructions ROL
AAA
AAD ROTATE LEFT
AAM
AAS DESCRIPTION:
ADC
ADD .-. .---------------.
|C|<-.--|7 <---------- 0|<-.
CMP '-' | '---------------' |
'---------------------'
DAA Rotates the bits in the destination to the left "count" times wi
DAS all data pushed out the left side re-
entering on the right. The
DEC Carry Flag will contain the value of the last bit rotated out.
DIV USAGE:ROL dest,count
IDIV dest-mem/reg
IMUL
FLAGS:CF OF
INC
NEG Operands Clock Cycles Size in bytes

SBB 8086 80286 80386 80486
reg,1 2 2 3 3 2
SUB
mem,1 15+EA 7 7 4 2-4
XADD
reg,CL 8+4n 5+n 3 3 2
Bit Manipulation mem,CL 20+EA+4n 8+n 7 4 2-4
Instructions reg,immed8 - 5+n 3 2 3
BSWAP mem,immed8 - 8+n 7 4 3-5
Logical AND
Logical NOT EXAMPLES:
Logical OR
Logical XOR ROL SI,10 : SI is rotated left by 10 places
RCL ROL WORD PTR[BX],2 : The word contents of the data segment
RCR addressed by BX is rotated left by 2 places
ROL
ROR
SAR
SHL/SAL Comments
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/rol[3/9/2019 8:53:49 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

ROR - Microprocessors@BITS

Arithmetic
Instructions ROR
AAA
AAD ROTATE RIGHT
AAM
AAS DESCRIPTION:
ADC
ADD .---------------. .-.
CMP .->|7 ----------> 0|--.->|C|
| '---------------' | '-'
DAA '---------------------'
Rotates the bits in the destination to the right "count" times w
DAS all data pushed out the right side re-
DEC entering on the left. The
Carry Flag will contain the value of the last bit rotated out.
DIV
USAGE:ROR dest,count
IDIV
IMUL dest-mem/reg
INC FLAGS:CF OF
NEG
SBB 8086 80286 80386 80486
SUB reg,1 2 2 3 3 2
XADD mem,1 15+EA 7 7 4 2-4
Bit Manipulation reg,CL 8+4n 5+n 3 3 2
Instructions mem,CL 20+EA+4n 8+n 7 4 2-4

reg,immed8 - 5+n 3 2 3
BSWAP
mem,immed8 - 8+n 7 4 3-5
Logical AND
Logical NOT
EXAMPLES:
Logical OR
Logical XOR
ROR SI,10 : SI is rotated left by 10 places
RCL
ROR BYTE PTR[BX],2 : The byte contents of the data segment
RCR
addressed by BX is rotated left by 2 places
ROL
ROR
SAR
SHL/SAL Comments
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/ror[3/9/2019 8:54:15 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

SAR - Microprocessors@BITS

Arithmetic
Instructions SAR
AAA
AAD SHIFT ARITHMETIC RIGHT
AAM
AAS DESCRIPTION:
ADC .---------------. .-.
ADD .--|7 ----------> 0|---->|C|
| '---------------' '-'
CMP '---^
Shifts the destination right by "count" bits with the current si
DAA bit replicated in the leftmost bit. The Carry Flag contains the
DAS last bit shifted out.
DEC USAGE:SAR dest,count

DIV dest-mem/reg
IDIV FLAGS:CF OF PF SF ZF (AF undefined)
IMUL
CLOCKS AND SIZE:
INC
MUL Operands Clock Cycles Size in bytes
8086 80286 80386 80486
NEG
reg,1 2 2 3 3 2
SBB
mem,1 15+EA 7 7 4 2-4
SUB reg,CL 8+4n 5+n 3 3 2
XADD mem,CL 20+EA+4n 8+n 7 4 2-4
Bit Manipulation reg,immed8 - 5+n 3 2 3
Instructions mem,immed8 - 8+n 7 4 3-5
BSWAP
Logical AND EXAMPLES:
Logical NOT
Logical OR SAR SI,2 : SI is arithmetically shifted 2 places to the right
Logical XOR SAR DATA1,CL : The contents of data segment addressed by DATA1
RCL is right shifted arithmetically by the number specified by CL.
SAR BYTE PTR[BX],10 :The byte contents addressed by BX is
RCR arithmetically right shifted by 10.
ROL
ROR
Comments
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/sar[3/9/2019 8:54:45 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

SHL/SAL - Microprocessors@BITS

Arithmetic
Instructions SHL/SAL
AAA
AAD SHIFT LOGICAL LEFT/ SHIFT ARITHMETIC LEFT
AAM DESCRIPTION:
AAS
.-. .---------------. .-.
ADC |C|<----|7 <---------- 0|<----|0|
ADD '-' '---------------' '-'
Shifts the destination left
CMP by "count" bits with zeroes shifted in on the right.
The Carry Flag contains the last bit shifted out.
DAA
DAS USAGE: SHL/SAL dest,count
DEC dest-mem/reg
DIV FLAGS: CF OF PF SF ZF (AF undefined)
IDIV CLOCKS AND SIZE:
IMUL
INC 8086 80286 80386 80486
MUL reg,1 2 2 3 3 2
NEG mem,1 15+EA 7 7 4 2-4
SBB reg,CL 8+4n 5+n 3 3 2
mem,CL 20+EA+4n 8+n 7 4 2-4
SUB
reg,immed8 - 5+n 3 2 3
XADD
mem,immed8 - 8+n 7 4 3--5
Bit Manipulation
Instructions
EXAMPLES:
BSWAP
Logical AND
SHL/SAL ECX,10 : ECX is logically shifted left 10 places
Logical NOT
SHL/SAL ECX,CL : ECX is logically shifted left by the number
Logical OR
of spaces specified by CL
Logical XOR
SHL/SAL BYTE PTR[BX],10 : The byte contents of data segment
RCL
addressed by BX is logically left shifted by
RCR
10
ROL
ROR
SAR Comments
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/shl-sal[3/9/2019 8:55:14 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

SHR - Microprocessors@BITS

Arithmetic
Instructions SHR
AAA
AAD SHIFT LOGICAL RIGHT
AAM DESCRIPTION:
AAS
.-. .---------------. .-.
ADC |0|---->|7 ----------> 0|---->|C|
ADD '-' '---------------' '-'
Shifts the destination right by "count" bits with zeroes shifted
CMP The Carry Flag contains the last bit shifted out.
DAA USAGE: SHR dest,count
DAS dest-mem/reg
DEC
FLAGS: CF OF PF SF ZF (AF undefined)
DIV
CLOCKS AND SIZE:
IDIV
8086 80286 80386 80486
INC
reg,1 2 2 3 2
MUL
mem,1 15+EA 7 7 2-4
NEG reg,CL 8+4n 5+n 3 2
SBB mem,CL 20+EA+4n 8+n 7 2-4
SUB reg,immed8 - 5+n 3 3
XADD mem,immed8 - 8+n 7 3--5
Bit Manipulation
Instructions EXAMPLES:
BSWAP
Logical AND SHR ECX,10 : ECX is logically shifted right 10 places
Logical NOT SHR ECX,CL : ECX is logically shifted right by the number of
Logical OR spaces specified by CL.
Logical XOR SHR BYTE PTR[BX],10 : The byte contents of data segment
RCL addressed by BX is logically right shifted by
RCR 10.
ROL
ROR
SAR Comments
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/shr[3/9/2019 8:55:41 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

SHRD/SHLD - Microprocessors@BITS

Arithmetic
Instructions SHRD/SHLD
AAA
AAD DOUBLE PRECISION SHIFT (386+)
AAM
AAS DESCRIPTION:
ADC SHLD shifts "dest" to the left "count" times and the bit positio
ADD opened are filled with the most significant bits of "src". SHRD
CMP shifts "dest" to the right "count" times and the bit positions
DAA opened are filled with the least significant bits of the second
DAS operand. Only the 5 lower bits of "count" are used.
DEC
DIV USAGE: SHLD dest,src,count
IDIV SHRD dest,src,count
IMUL
INC FLAGS: CF PF SF ZF (OF,AF undefined)
MUL
NEG CLOCKS AND SIZES:
SBB
SUB 8086 80286 80386 80486
XADD reg,reg,imm 3 2 4
Bit Manipulation mem,reg,imm 7 3 6
Instructions reg,reg,CL 3 3 3
BSWAP mem,reg,CL 7 3 5
Logical AND
Logical NOT
Logical OR
Logical XOR Comments
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/bit-manipulation-instructions/shrd-shld[3/9/2019 8:56:11 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Data Transfer - Microprocessors@BITS
Home
Arithmetic Data Transfer
Instructions
AAA
This category enlists and describes all functions used for transfer of data between
AAD
registers, between registers and memory, or between two locations in memory.
AAM
AAS Instructions
ADC CMPXCHG
ADD LAHF
CMP LAR
DAA LDS/LES
DAS LEA
DEC MOV
DIV
MOVS
IDIV
MOVSX [386+]
IMUL
MOVZX
INC
SAHF
MUL
NEG XCHG
SBB XLAT(B)
SUB
XADD
Bit Manipulation Subpages (12):
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX
Instructions [386+]
MOVZX
SAHF
XCHG
XLAT(B)
BSWAP
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer[3/9/2019 8:56:41 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

CMPXCHG - Microprocessors@BITS
Home Data Transfer ‎ > ‎

Arithmetic
Instructions CMPXCHG
AAA
AAD This instruction compares the accumulator (AL/AX/EAX) (8-32 bits) with the operand
AAM "dest". If equal the "dest" is loaded with the operand "src", otherwise the accumulator is
loaded with "dest".
AAS
ADC Usage CMPXCHG dest,src
ADD
Flags AF PF OF CF ZF SF
CMP
DAA Clocks and Size
Operands Clocks Size Bytes
DAS
486
DEC
reg,reg 6 2
DIV reg,mem 7 2
IDIV
IMUL Example
INC
MUL ;Assume AX = 0010H, CX = 0010H, DX = 0012H
NEG CMPXCHG CX, DX ; CX = AX so CX = 0012H
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/cmpxchg[3/9/2019 8:57:08 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

LAHF - Microprocessors@BITS

Arithmetic
Instructions LAHF
AAA
AAD This instruction copies the low byte of the flag register to AH. Only five flags are copied
AAM the remaining bits are undefined. After copying, AH looks like this:
AAS AH = SF ZF xx AF xx PF xx CF
ADC
ADD
Usage LAHF
CMP
DAA
Flags None
DAS
DEC
Clocks and Size
IDIV 8086 80286 80386 80486
IMUL none 4 2 2 3 1
INC
MUL
NEG
Comments
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/lahf[3/9/2019 8:57:39 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

LAR - Microprocessors@BITS

Arithmetic
Instructions LAR
AAA
AAD
LOAD ACCESS RIGHT (286+ protected)
AAM
AAS
DESCRIPTION:
ADC The high byte of the of the destination register is overwritten
ADD the value of the access rights byte and the low order byte is ze
CMP depending on the selection in the source operand. The Zero Flag
DAA set if the load operation is successful.
DAS
DEC USAGE: LAR dest,src
DIV
IDIV
FLAGS: ZF
IMUL
INC CLOCKS AND SIZES:
MUL
NEG 8086 80286 80386 80486
SBB reg16, reg16 14 15 11 3
SUB reg32, reg32 15 11 3
XADD reg16, mem16 16 16 11 3-7

reg32, mem32 16 11 3-7
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/lar[3/9/2019 8:58:05 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

LDS/LES - Microprocessors@BITS

Arithmetic
Instructions LDS/LES
AAA
AAD This instruction copies a word from two memory locations into the register specified in the
AAM instruction. It then copies a word from the next two memory locations into the DS(ES)
AAS register. It is useful for pointing to SI(DI) and DS(ES) at the start of a string before using a
ADC string instruction.
ADD
CMP
Usage LDS dest, src
DAA
Operands
DAS
src
DEC
Memory address of first word
DIV
dest
IDIV
Register
IMUL
INC
Flags None.
MUL
NEG
Clocks and Size
SBB Operands Clocks Size in bytes
SUB 8086 286 386 486
XADD reg16,mem32 16+EA 7 7 6 2-4
Bit Manipulation reg,mem (PM) - - 22 12 5 - 7
Instructions
BSWAP Example
LDS BX, [4326] ;Copy contents of memory at displacement 4326H in DS to BL,
Logical AND contents of 4327H to BH. The contents at a displacement of 4328H and 4329H
Logical NOT are copied to the DS register.
Logical OR
Logical XOR Comments
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/lds-les[3/9/2019 8:58:34 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

LEA - Microprocessors@BITS

Arithmetic
Instructions LEA
AAA
AAD Transfers offset address of "src" to the destination register. LEA is very similar to MOV, except
AAM that math can be done on the original value before it is used.
AAS
ADC Usage LEA dest, src
ADD dest must be a register.
CMP
Flags None.
DAA
DAS Clocks and Size
DEC Operands Clocks Size in bytes
DIV 8086 286 386 486
IDIV reg,mem 2+EA 3 2 1 2-4
IMUL
INC Example
MUL lea eax, [eax+eax] ; Double the value of eax -- eax = eax * 2
lea edi, [esi+0Bh] ; Add 11 to esi and store the result in edi
NEG
SBB
SUB Comments
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/lea[3/9/2019 8:59:00 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

MOV - Microprocessors@BITS

Arithmetic
Instructions MOV
AAA
AAD
Description
AAM
AAS
The MOV instruction copies a word or byte of data from a specified source to a
ADC
specified destination. The source and destination in an instrcution cannot both be
ADD
memory locations. For the MOV instruction, the src and dest addresses must both be
CMP
of type byte or both of type word.
DAA
DAS
Usage MOV dest, src
DEC
DIV dest - Reg/Mem
IDIV src - Reg/Mem/Imm
IMUL
INC
Flags
MUL
None.
NEG
SBB
Clocks and Size
SUB Clock Cycles
XADD Instruction 8086 80286 80386 80486 Size in bytes
Bit Manipulation reg,reg 2 2 2 1 2
Instructions mem,reg 9+EA 3 2 1 2-4
reg,mem 8+EA 5 4 1 2-4
BSWAP
Logical AND
reg,immed 4 2 2 1 2-4
Logical NOT mem,accum 10 3 2 1 3.000
Logical OR accum,mem 10 5 4 1 3.000
Logical XOR segreg,reg16 2 2 2 3 2.000
RCL segreg,mem16 8+EA 5 5 9 2-4

reg16,segreg 2 2 2 3 2.000
RCR
mem16,segreg 9+EA 3 2 3 2-4
ROL reg32,CR0/CR2/CR3 6 4
ROR CR0,reg32 10 16
SAR CR2,reg32 4 4 3
SHL/SAL CR3,reg32 5 4 3
reg32,DR0/DR1/DR2/DR3 22 10 3
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/move[3/9/2019 8:59:36 PM]

reg32,DR6/DR7 22 10 3
SHRD/SHLD DR0/DR1/DR2/DR3,reg32 22 11 3
Data Transfer DR6/DR7,reg32 16 11 3
CMPXCHG reg32,TR6/TR7 12 4 3
LAHF TR6/TR7,reg32 12 4 3
reg32,TR3 3
LAR
TR3,reg32 6
LDS/LES
LEA
Examples
MOV
MOVS
mov eax, ebx — copy the value in ebx into eax
MOVSX [386+] mov byte ptr [var], 5 — store the value 5 into the byte at location var
MOVZX
SAHF
XCHG
Comments
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

MOVS - Microprocessors@BITS

Arithmetic
Instructions MOVS
AAA
AAD Copies data from addressed by DS:SI (even if operands are given) to the location ES:DI
AAM destination and updates SI and DI based on the size of the operand or instruction used. SI and
DI are incremented when the Direction Flag is cleared and decremented when the Direction
AAS
Flag is Set. Use with REP prefixes.
ADC
ADD Usage MOVS( /B/W/D) dest, src
CMP
dest ES:DI
DAA src DS:SI
DAS
Flags
DEC
None.
DIV
IDIV Clocks and Size
IMUL Operands Clocks Size in bytes
INC 8086 286 386 486

dest,src 18 5 7 7 1
MUL
NEG
Example
SBB
SUB ; copy mystr into mystr2
XADD mov esi, mystr
mov edi, mystr2
Bit Manipulation cld
Instructions mov ecx,4
rep movsw
BSWAP
Logical AND
Logical NOT
Logical OR Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/movs[3/9/2019 9:00:03 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

MOVSX [386+] - Microprocessors@BITS

Arithmetic
Instructions MOVSX [386+]
AAA
AAD Copies the value of the source operand to the destination register with the sign extended.
AAM
AAS Usage MOVSX dest,src
ADC Flags None
ADD
CMP
386 486
DAA reg,reg 3 3 3
DAS reg,mem 6 3 3-7
DEC
DIV Example
IDIV MOVSX r32,r/m16 Move word to double word, sign-extension
IMUL 0x1000 becomes 0x00001000, since it was positive

INC 0x7FFF becomes 0x00007FFF, since it was positive
0xFFFF becomes 0xFFFFFFFF, since it was negative (note that 0xFFFF is -1 in 16-
MUL bit signed, and 0xFFFFFFFF is -1 in 32-bit signed)
NEG 0x8000 becomes 0xFFFF8000, since it was negative (note that 0x8000 is -32768 in 16-
SBB bit signed, and 0xFFFF8000 is -32768 in 32-bit signed)
SUB
XADD
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/movsx[3/9/2019 9:00:29 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

MOVZX - Microprocessors@BITS

Arithmetic
Instructions MOVZX
AAA
AAD This instruction copies the value of the source operand to the destination operand with the
AAM
zeros extended. This instruction is only available 386 onwards.
AAS
ADC
Usage MOVZX dest, src
ADD
CMP
Flags None
DAA
DAS
Clocks and Size
DEC Operands Clocks Size in bytes
DIV 8086 286 386 486
IDIV reg,reg - - 3 3 3
IMUL reg,mem - - 6 3 3- 7
INC
MUL
NEG
SBB Comments
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/movzx[3/9/2019 9:00:54 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

SAHF - Microprocessors@BITS

Arithmetic
Instructions SAHF
AAA
AAD SAHF- Store AH Register into Flags
AAM
AAS DESCRIPTION: Transfers bits of AH register into the Flag
ADC Register. This includes AF, CF, PF, SF and ZF.
ADD
CMP USAGE: SAHF
DAA FLAGS: AF CF PF SF ZF
DAS
CLOCKS AND SIZES:
DEC
8086 80286 80386 80486
IDIV
none 4 2 3 2 1
IMUL
INC
MUL
NEG Comments
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/sahf[3/9/2019 9:01:20 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

XCHG - Microprocessors@BITS

Arithmetic
Instructions XCHG
AAA
AAD The xchg (exchange) instruction swaps the src operand with the dest operand. It's like doing three
AAM move operations: from dest to a temporary (another register), then from src to dest, then from the
temporary to src, except that no register needs to be reserved for temporary storage.
AAS
ADC Only one operands can be in memory: at least one has to be a register.
ADD
CMP Usage XCHG dest, src

DAA Flags None.
DAS
DEC Clocks and Size
DIV
8086 286 386 486
IDIV reg,reg 4 3 3 3 2
IMUL mem,reg 17+EA 5 5 5 2-4
INC reg,mem 17+EA 5 5 3 2-4
MUL accum,reg 3 3 3 3 1
reg,accum 3 3 3 3 1
NEG
SBB
Example
SUB XCHG AX, r16 Exchange r16 with AX
XADD XCHG r/m32,r32 Exchange r32 with doubleword from r/m32
Bit Manipulation
Instructions Comments
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/xchg[3/9/2019 9:01:46 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

XLAT(B) - Microprocessors@BITS

Arithmetic
Instructions XLAT(B)
AAA
AAD Replaces the byte in AL with byte from a user table addressed by BX. Before the XLAT
AAM instruction can be executed, the lookup table containing the values for the new code must be
put in memory, and the offset of the starting address of the lookup table must be loaded in
AAS
BX. The best way to describe this is MOV AL,[BX+AL].
ADC
ADD Usage XLATB
CMP
Flags None.
DAA
DAS Clocks and Size
Operands Clocks Size in bytes
DEC
8086 286 386 486
DIV table offset 11 5 5 4 1
IDIV
IMUL Example
INC XLATB Set AL to memory byte DS:[(E)BX + unsigned AL]
MUL
NEG Comments
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/data-transfer/xlat[3/9/2019 9:02:13 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Miscellaneous - Microprocessors@BITS
Home
Arithmetic Miscellaneous
Instructions
AAA
This page includes instructions that don't quite fall under any of the other major
AAD
categories.
AAM
AAS Subpage Listing
ADC BT
ADD CBW
CMP CDQ
DAA CWD
DAS CWDE
DEC
DIV
IDIV Subpages (5):
BT
CBW
CDQ
CWD
CWDE
IMUL
INC
Comments
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/miscellaneous[3/9/2019 9:02:44 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

BT - Microprocessors@BITS
Home Miscellaneous ‎ > ‎

Arithmetic
Instructions BT
AAA
AAD The Bit Test instruction copies to the CF the bit at index 'src' in the 'dest' operand. This
AAM instruction is available 386 onwards.
AAS
ADC
Usage BT dest, src
ADD
CMP
Flags CF
DAA
DAS
Clocks and Size
DEC Operands Clocks Size in Bytes
DIV 8086 286 386 486
IDIV reg16,immed8 - - 3 3 4-8
IMUL mem16,immed8 - - 6 6 4-8

reg16,reg16 - - 3 3 3-7
INC
mem16,reg16 - - 12 12 3-7
MUL
NEG
Example
SBB
SUB
BT AX, 4 ;Copy the fifth least-significant bit from AX to CF
XADD
Bit Manipulation
Instructions
BSWAP
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/miscellaneous/bt[3/9/2019 9:03:12 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

CBW - Microprocessors@BITS

Arithmetic
Instructions CBW
AAA
AAD This instruction (Convert signed Byte to signed Word) fills AH with the sign of the byte in
AAM AL. AH is then the sign extension of AL.
AAS
ADC CBW is usually done before the signed byte in AL can be divided by another signed byte
ADD with the IDIV instruction.
CMP
DAA
Usage CBW
DAS
DEC
Flags None
DIV
IDIV
Clocks and Size
INC 8086 286 386 486
MUL none 2 2 3 3 1
NEG
SBB Example
SUB ; AL = 10011011 = -155 in Decimal (Signed)
XADD CBW ;AX = 11111111 10011011 = -155 in Decimal (Signed)
Bit Manipulation
Instructions
Comments
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/miscellaneous/cbw[3/9/2019 9:03:40 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

CDQ - Microprocessors@BITS

Arithmetic
Instructions CDQ
AAA
AAD CONVERT DOUBLE TO QUAD
AAM
AAS DESCRIPTION:Converts signed DWORD in EAX to a signed quad word i
ADC extending the high order bit of EAX throughout EDX.
ADD USAGE:CDQ
CMP
FLAGS:NONE
DAA
DAS CLOCKS AND SIZES:
DEC Operands Clock Cycles Size in bytes

DIV 8086 80286 80386 80486
none - - 2 3 1
IDIV
IMUL
EXAMPLE:
INC
MUL
If EAX is 011111110011101110011101110010111110
NEG
CDQ will result in
SBB
EDX:EAX =
SUB
00000000000000000000000000000000:0111111100111011100111011100101
XADD
Bit Manipulation
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/miscellaneous/cdq[3/9/2019 9:04:09 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

CWD - Microprocessors@BITS

Arithmetic
Instructions CWD
AAA
AAD This instruction (Convert signed Word to signed Doubleword) copies the sign bit of a word in
AAM AX to all the bits of DX. DX is then the sign extension of AX.
AAS
ADC This instruction must be done before a signed word in AX can be divided by another signed
ADD word with the IDIV instruction.
CMP
DAA
Usage CWD
DAS
DEC
Flags None
DIV
IDIV
Clocks and Size
INC 8086 286 386 486
MUL none 5 2 2 3 1
NEG
SBB Example
SUB
XADD ;AX = 11110000 11000111 = -3897 decimal
Bit Manipulation CWD ;Result: DX = 11111111 11111111, AX = 11110000 11000111
Instructions
BSWAP
Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/miscellaneous/cwd[3/9/2019 9:04:34 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

CWDE - Microprocessors@BITS

Arithmetic
Instructions CWDE
AAA
AAD This instruction converts a signed word in AX to a signed doubleword in EAX by extending
AAM the sign bit of AX throughout EAX (unlike CWD which uses DX:AX).
AAS
Usage CWDE
ADC
ADD Flags None
CMP Clocks and Size
DAA Operands Clocks Size in Bytes
DAS 8086 286 386 486
none - - 3 3 1
DEC
DIV
Example
IDIV
;AX = 11110000 11000111 = -3897 decimal
IMUL
CWD ;Result: EAX = 11111111 11111111 11110000 11000111, AX = 11110000
INC
11000111
MUL
NEG
SBB Comments
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/miscellaneous/cwde[3/9/2019 9:05:00 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Processor Control Instructions - Microprocessors@BITS
Home
Arithmetic Processor Control Instructions
Instructions
AAA
AAD Subpage Listing
AAM CLC
AAS CLD
ADC CLI
ADD CMC
CMP ESC
DAA LOCK
DAS
NOP
DEC
STC
DIV
STD
IDIV
STI
IMUL
INC WAIT
MUL
NEG
SBB Subpages (11):
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions[3/9/2019 9:05:28 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

CLC - Microprocessors@BITS
Home Processor Control Instructions ‎>‎

Arithmetic
Instructions CLC
AAA
AAD This instruction clears the Carry Flag (CF).
AAM
AAS
Usage CLC
ADC
ADD
Flags CF
CMP
DAA
Clocks and Size
DAS Operands Clocks Size in Bytes
DEC 8086 286 386 486
DIV none 2 2 2 2 1
IDIV
IMUL
Comments
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/clc[3/9/2019 9:05:55 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

CLD - Microprocessors@BITS

Arithmetic
Instructions CLD
AAA
AAD This instruction resets the Direction Flag to 0. SI and DI are automatically incremented
AAM when one of the string instructions is executed.
AAS
ADC
Usage CLD
ADD
CMP
Flags CF
DAA
DAS
Clocks and Size
DIV 8086 286 386 486
IDIV none 2 2 2 2 1
IMUL
INC
Comments
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/cld[3/9/2019 9:06:23 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

CLI - Microprocessors@BITS

Arithmetic
Instructions CLI
AAA
AAD This instruction resets the interrupt flag to 0. If the interrupt flag is reset, the 8086 will n
AAM
respond to an interrupt signal on its INTR input.
AAS
ADC
The CLI instruction has no effect on the non-maskable interrupt (NMI).
ADD
CMP
Usage CLI
DAA
DAS
Flags IF
DEC
DIV
Clocks and Size
IDIV Operands Clocks Size in Bytes
IMUL 8086 286 386 486
INC none 2 2 3 5 1
MUL
NEG
SBB
Comments
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/cli[3/9/2019 9:06:51 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

CMC - Microprocessors@BITS

Arithmetic
Instructions CMC
AAA
AAD COMPLEMENT CARRY
AAM
AAS DESCRIPTION:Toggles (inverts) the Carry Flag.
ADC
ADD USAGE: CMC
CMP FLAGS: CF
DAA CLOCKS AND SIZES:
DAS
DEC 8086 80286 80386 80486
DIV none 2 2 2 2 1
IDIV
IMUL
INC
MUL
Comments
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/cmc[3/9/2019 9:07:17 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

ESC - Microprocessors@BITS

Arithmetic
Instructions ESC
AAA
AAD ESCAPE
AAM
AAS DESCRIPTION: The ESC instruction passes instructions to
ADC floating point coprocessor from the microprocessor. Whenever
ADD an ESC instruction executes, the microprocessor provides the
CMP memory address, if required, but otherwise performs a NOP.
DAA
DAS USAGE: ESC immed,src
DEC FLAGS: NONE
DIV
CLOCKS AND SIZES:
IDIV
8086 80286 80386 80486
INC
immed, reg 2 9-20 2
MUL
immed, mem 2 9-20 2-4
NEG
SBB
SUB Comments
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/esc[3/9/2019 9:07:46 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

LOCK - Microprocessors@BITS

Arithmetic
Instructions LOCK
AAA
AAD
DESCRIPTION: The LOCK prefix appends to an instruction and
AAM
causes the x86 LOCK Pin to be asserted(become logic 0) and
AAS
thereby causing external bus masters and other peripherals to
ADC
be disabled.
ADD
The LOCK instruction causes the LOCK pin to be activated for
CMP
only the duration of the locked instruction.
DAA
DAS
USAGE : LOCK : [Instruction]
DEC
DIV
FLAGS : NONE
IDIV
IMUL
CLOCKS AND SIZES:
INC
MUL Operands Clock Cycles Size in bytes
NEG 8086 80286 80386 80486
SBB none 2 0 0 1 1
SUB
XADD EXAMPLES:
Bit Manipulation
Instructions LOCK: MOV AL,BL ; Causes the LOCK Pin to be activated for
BSWAP the particular mov instruction
Logical AND
Logical NOT
Logical OR
Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/lock[3/9/2019 9:08:14 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

NOP - Microprocessors@BITS

Arithmetic
Instructions NOP
AAA
AAD NO OPERATION
AAM
AAS DESCRIPTION:This is a do nothing instruction. It results in occ
ADC space and time and is most useful for patching code segments.
ADD USAGE: NOP
CMP
FLAGS: NONE
DAA
DAS CLOCKS AND SIZES:
DEC Operands Clock Cycles Size in bytes

DIV 8086 80286 80386 80486
none 3 3 3 1 1
IDIV
IMUL
EXAMPLE:
INC
MUL ;To do nothing 2 times:
NEG DELAY:
SBB
NOP ; does nothing
SUB NOP ; does nothing
XADD
RET ; returns to point of function call
Bit Manipulation
Instructions
BSWAP
Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/nop[3/9/2019 9:08:40 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

STC - Microprocessors@BITS

Arithmetic
Instructions STC
AAA
AAD This instruction sets the carry flag (CF) to 1.
AAM
AAS
Usage STC
ADC
ADD
Flags CF
CMP
DAA
Clocks and Size
DAS Operands Clocks Size in Bytes
DEC 8086 286 386 486
DIV none 2 2 2 2 1
IDIV
IMUL
Comments
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/stc[3/9/2019 9:09:09 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

STD - Microprocessors@BITS

Arithmetic
Instructions STD
AAA
AAD This instruction is used to set the Direction Flag to 1 so that SI/DI will automatically
AAM
decrement when one of the string instructions executes.
AAS
ADC
Usage STD
ADD
CMP
Flags DF
DAA
DAS
Clocks and Size
DIV 8086 286 386 486
IDIV none 2 2 2 2 1
IMUL
INC
Comments
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/std[3/9/2019 9:09:37 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

STI - Microprocessors@BITS

Arithmetic
Instructions STI
AAA
AAD Setting the interrupt flag enables the INTR interrupt input of the 8086. The instruction
AAM will not take effect until after the next instruction after STI.
AAS
ADC When the INTR input is enabled, an interrupt signal on this input will then cause the 8086 to
ADD interrupt program execution, push the return address and flags on the stack, and execute an
CMP interrupt service procedure. An IRET instruction after the interrupt service procedure restores
DAA flags and returns execution to the interrupted program.
DAS
DEC
Usage STI
DIV
IDIV
Flags IF
IMUL
INC
Clocks and Size
MUL Operands Clocks Size in Bytes
NEG 8086 286 386 486
SBB none 2 2 2 5 1
SUB
XADD
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/sti[3/9/2019 9:10:03 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

WAIT - Microprocessors@BITS

Arithmetic
Instructions WAIT
AAA
AAD DESCRIPTION: The WAIT instruction monitors the hardware BUSY
AAM pin on 80286 and 80386, and the TEST pin on the 8086/8088. If
AAS WAIT instruction executes while the pin=1, nothing happens and
ADC the next instruction executes normally. If pin=0, when the
ADD WAIT instruction executes, the microprocessor waits for the
CMP pin to return to logic 1. This instruction is used to prevent
DAA the CPU fromaccessing memory that may be
DAS temporarily in use by the coprocessor.
DEC
DIV USAGE: WAIT
IDIV
IMUL
INC FLAGS: NONE
MUL CLOCKS AND SIZES:
NEG
SBB
8086 80286 80386 80486
SUB none 4 3 6+ 1-3 1
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/processor-control-instructions/wait[3/9/2019 9:10:29 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Program Execution Transfer Instructions - Microprocessors@BITS
Home
Arithmetic Program Execution Transfer
Instructions
AAA Instructions
AAD
AAM
Instructions here transfer control of the program from the current address to some
AAS
other address below or above. This is necessary if sequential execution of
ADC
instructions is not desired like in cases of conditional/ unconditional branch, loop, etc.
ADD
CMP
The conditional transfer instructions like jump if carry, compare values in order to
DAA
decide whether or not a jump is taken to the given address. The
DAS
terms above and below refer to unsigned binary numbers where above means
DEC
greater in magnitude and below means lesser in magnitude in such instructions. In
DIV
signed number comparisons the terms greater than and less than are used.
IDIV
IMUL
INC Subpage Listing
MUL CALL
NEG ENTER
SBB INT
SUB INTO
XADD IRET
Bit Manipulation JA/JNBE
Instructions
JAE/JNB
BSWAP
JB/JNAE/JC
Logical AND
Logical NOT JBE/JNA
Logical OR JC
Logical XOR JCXZ
RCL JE/JZ
RCR JG/JNLE
ROL JGE/JNL
ROR JL/JNGE
SAR JLE/JNG
SHL/SAL
JMP
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions[3/9/2019 9:10:58 PM]

JNE/JNZ
SHRD/SHLD
JNO
Data Transfer
JNP/JPO
CMPXCHG
JNS
LAHF
LAR JO
LDS/LES JP/JPE
LEA JS
MOV LEAVE
MOVS LOOP
MOVSX [386+] LOOPE/LOOPZ
MOVZX LOOPNE/LOOPNZ
SAHF TEST
XCHG
XLAT(B)
Miscellaneous Subpages (29):
View All
BT
CBW
Comments
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution Transfer
Instructions
CALL
ENTER

INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
CMPS/CMP…

INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

CALL - Microprocessors@BITS
Home Program Execution Transfer Instructions ‎>‎

Arithmetic
Instructions CALL
AAA
AAD DESCRIPTION:Pushes Instruction Pointer (and Code Segment for far
AAM stack and loads Instruction Pointer with the address of procedur
name.
AAS Code continues with execution at CS:IP.
ADC USAGE: CALL destination
ADD destination-label/reg/mem
CMP
FLAGS: None
DAA
DAS CLOCK CYCLES:
DEC Operands Clock Cycles

DIV 8086 80286 80386 80486
label(near) 19 7 7 3
IDIV
label(far) 28 13 17 18
IMUL
reg(near) 16 7 7 5
INC mem(near) 21+EA 11 10 5
MUL mem(far) 16 7 7 5
NEG
SBB EXAMPLES:
SUB
CALL BX ; The program flow jumps to the offset address
XADD specified in BX register(within the current code segment).
CALL FUNCTION1 ; Program flow switches to location with label
Bit Manipulation 'FUNCTION1'.
Instructions
BSWAP
Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/call[3/9/2019 9:11:27 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

ENTER - Microprocessors@BITS

Arithmetic
Instructions ENTER
AAA
AAD Description: Modifies stack for entry into procedures for high level languages. Paired with
AAM the LEAVE instruction, this is an efficient method of entry and exit to procedures. This
AAS instruction is available from 80188 onward.
ADC
ADD Usage: ENTER storage, level
CMP [storage: amount of storage to be allocated on the stack, a 16 bit immediate value]
DAA [level: nesting level of the routine, an 8 bit immediate value]
DAS
DEC Flags: the instruction has no effect on any flags.
DIV
IDIV Clocks and size:
INC 8086 286 386 486
MUL
none - 5 4 5 1
NEG
SBB
Example:
SUB
ENTER 16, 0; creates a stack frame for a procedure
XADD
Bit Manipulation
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/enter[3/9/2019 9:11:55 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

INT - Microprocessors@BITS

Arithmetic
Instructions INT
AAA
AAD The INT instruction initiates a software interrupt by doing the following:
AAM
AAS 1. Decremenet the stack pointer by 2 and push the flags onto the stack.
ADC 2. Decrement the stack pointer by 2 and push the contents of CS onto the stack.
ADD 3. Decrement the stack pointer by 3 and push the offset of the next instruction after the INT
CMP number instruction on the stack.
DAA 4. Get a new value for UP from an absolute memory address of 4 times the type specified in
DAS the instruction. For an INT 8 instruction, for example, the new IP will be read from address
DEC 00020H.
DIV 5. Get a new value for CS from an absolute memory address of 4 times the type specified in
IDIV the instruction plus 2. For the same example, CS = 00022H.
IMUL 6. Reset both IF and TF.
INC
MUL
Usage INT <Type>
NEG
Type is between 0 and 255
SBB
SUB
Flags IF, TF
XADD
Bit Manipulation Clocks and Size
Instructions
BSWAP 8086 286 386 486
Logical AND 3 (constant) 51/71 23+m 33 26 2
Logical NOT 3 (prot. mode,
same priv.) - 40+m 59 44 2
Logical OR
3 (prot. mode,
Logical XOR more priv.) - 78+m 99 71 2
RCL 3 (from VM86 to
RCR PL 0) - - 119 82 2
ROL 3 (prot. mode via

task gate) - 167+m TS 37+TS 2
ROR
immed8 52/72 23+m 37 30 1
SAR immed8 (prot.
SHL/SAL mode, same
SHR priv.) - 40+m 59 44 1
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/int[3/9/2019 9:12:24 PM]

immed8 (prot.
SHRD/SHLD
mode, more
Data Transfer priv.) - 78+m 99 71 1
CMPXCHG immed8 (from
LAHF VM86 to PL 0) - - 119 86 1
LAR immed8 (prot.

mode, via task
LDS/LES
gate) - 167+m TS 37+TS 1
LEA
MOV
Example
MOVS
MOVSX [386+]
INT 35 ;New IP from 0008CH, new CS from 0008EH
MOVZX
SAHF
INT 3 ;Special form which is used as a breakpoint instruction on many systems. New
XCHG
IP: 0000CH, CS: 0000EH. Has a single-byte
XLAT(B)
;code CCH.
Miscellaneous
BT
CBW Comments
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

INTO - Microprocessors@BITS

Arithmetic
Instructions INTO
AAA
AAD INTO stands for the Interrupt on Overflow instruction. If the Overflow Flag (OF) = 1, this
AAM instruction causes the 8086 to do an indirect far call to a procedure you write to handle the
AAS overflow condition (INT 4). IP is read from 00010H and CS from 00012H.
ADC
ADD The foll. steps are executed by the 8086 before doing the call:
CMP
DAA 1. Decrement the stack pointer by 2 and push the flags onto the stack
DAS 2. Decrement SP by 2, push CS onto the stack.
DEC 3. Decrement SP by 2, push the offset of the next instruction after INTO onto the stack
DIV 4. Reset TF and IF.
IDIV
IMUL
Usage INTO
INC
MUL
Flags IF, TF
NEG
SBB
Clocks and Size
SUB Operands Clocks Size in Bytes
XADD 8086 286 386 486
Bit Manipulation none: jump 53/73 24+m 35 28 1
Instructions none: no jump 4 3 3 3 1
none: (prot.
BSWAP
mode, same
Logical AND priv.) - - 59 46 1
Logical NOT none: (prot.
Logical OR mode, more
Logical XOR priv.) - - 99 73 1

none: (from
RCL
VM86 to PL 0) - - 84 119 1
RCR none: (prot.
ROL mode, via task
ROR gate) - - TS 39+TS 1
SAR
SHL/SAL Comments
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/into[3/9/2019 9:12:59 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

IRET - Microprocessors@BITS

Arithmetic
Instructions IRET
AAA
AAD The IRET instruction is used at the end of an interrupt service procedure to return execution
AAM to the interrupted program. To do this return, the 8086 copies the saved value of IP from the
AAS stack to IP, the stored value of CS from the stack to CS, and the stored value of the flags back
ADC to the flag register.
ADD
CMP Flag values from the procedure will be lost unless they are specifically saved in some way.
DAA
DAS
Usage IRET
DEC
IRETD (386+)
DIV
IDIV
Flags AF, CF, DF, IF, ZF, SF, TF, PF
IMUL
INC
Clocks and Size
NEG 8086 286 386 486
SBB (iret)none 32/44 17+m 22 15 1
SUB (prot. mode) - 31+m 38 15 1

(to less
XADD
privilege) - 55+m 82 36 1
Bit Manipulation (different task,
Instructions NT=1) - 169+m TS TS+32 1
BSWAP (iretd) - - 22/38 15 1
Logical AND (to less
privilege) - - 82 36 1
Logical NOT
(to VM86 mode) - - 60 15 1
Logical OR iretd (different
Logical XOR task, NT=1) - - TS TS+32 1
RCL
RCR
ROL
Comments
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/iret[3/9/2019 9:13:35 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JA/JNBE - Microprocessors@BITS

Arithmetic
Instructions JA/JNBE
AAA
AAD Jump if above/ Jump if not below or equal
AAM Description: Jumps to the destination label mentioned in the instruction if the result of
AAS previous instruction (generally compare) causes both CF and ZF to have value equal to 0, else
ADC no action is taken.
ADD
CMP Usage: JA dest, JNBE dest
DAA [dest: addressin the range of -128 bytes to +127 bytes from the address of instruction after
DAS JA/JNBE]
DEC
DIV Flags: the instruction has no effect on any flags.
IDIV
IMUL Example:
INC CMP AX, 0030H; compares by subtracting 0030H from the value in AX regsiter
MUL JA LABEL1; jumps to the address specified by LABEL1 if value in register AX is above
NEG the value 0030H
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/ja-jnbe-1[3/9/2019 9:14:09 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JAE/JNB - Microprocessors@BITS

Arithmetic
Instructions JAE/JNB
AAA
AAD Jump if above or equal/ Jump if not below
AAS previous instruction (generally compare) causes CF to have value equal to 0, else no action is
ADC taken.
ADD
CMP Usage: JAE dest, JNB dest
DAA [dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
DAS JAE/JNB]
DEC
IDIV
IMUL Example:
MUL JAE LABEL1; jumps to the address specified by LABEL1 if value in register AX is above
NEG or equal to the value 0030H
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jae-jnb[3/9/2019 9:14:40 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JB/JNAE/JC - Microprocessors@BITS

Arithmetic
Instructions JB/JNAE/JC
AAA
AAD Jump if below/ Jump if not above or equal
AAS previous instruction (generally compare) causes CF to have value equal to 1, else no action is
ADC taken.
ADD
CMP Usage: JB dest, JNAE dest, JC dest
DAS JB/JNAE/JC]
DEC
IDIV
IMUL Example:
MUL JB LABEL1; jumps to the address specified by LABEL1 if value in register AX is below
NEG the value 0030H
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jb-jnae[3/9/2019 9:15:15 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JBE/JNA - Microprocessors@BITS

Arithmetic
Instructions JBE/JNA
AAA
AAD Jump if below or equal/ Jump if not above
AAS previous instruction (generally compare) causes either the CF or ZF to have value equal to 1,
ADC else no action is taken.
ADD
CMP Usage: JBE dest, JNA dest
DAS JBE/JNA]
DEC
IDIV
IMUL Example:
MUL JBE LABEL1; jumps to the address specified by LABEL1 if value in register AX is below
NEG or equal to the value 0030H
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jbe-jna[3/9/2019 9:15:46 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JC - Microprocessors@BITS

Arithmetic
Instructions JC
AAA
AAD Jump if carry
AAM Description: Jumps to the destination label mentioned in the instruction if the value of CF is
AAS 1, else no action is taken.
ADC
ADD Usage: JC dest
CMP [dest: address in the range of -128 bytes to +127 bytes from the address of instruction after
DAA JC]
DAS
DIV
IDIV Example:
IMUL JC LABEL1; jumps to the address specified by LABEL1 if CF is set
INC
MUL
NEG Comments
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jc[3/9/2019 9:16:16 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JCXZ - Microprocessors@BITS

Arithmetic
Instructions JCXZ
AAA
AAD The Jump if CX is Zero causes a jump to a label given in the instruction if CX contains all
AAM zeros; unsigned comparison is used.
AAS
ADC JCXZ does not look at ZF when deciding to jump. Destination label must be in the range
ADD of -128 to 127 bytes from the address of the instruction after the JCXZ instruction.
CMP
DAA
Usage JCXZ Label
DAS
JECXZ Label (386+)
DEC
DIV
Flags None
IDIV
IMUL
Clocks and Size
INC Operands Clocks Size in bytes
MUL 8086 286 386 486
NEG label: jump 18 8+m 9+m 8 2
SBB no jump 6 4 5 5 2
SUB
XADD
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jcxz[3/9/2019 9:16:42 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JE/JZ - Microprocessors@BITS

Arithmetic
Instructions JE/JZ
AAA
AAD Jump if equal/ Jump if zero
AAM Description: Jumps to the destination label mentioned in the instruction if the ZF is set, else
AAS no action is taken.
ADC
ADD Usage: JE dest, JZ dest
DAA JE/JZ]
DAS
DIV
IDIV Example:
IMUL JZ LABEL1; jumps to the address specified by LABEL1 if ZF=1
INC
MUL
NEG Comments
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/je-jz[3/9/2019 9:17:12 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JG/JNLE - Microprocessors@BITS

Arithmetic
Instructions JG/JNLE
AAA
AAD Jump if greater/ Jump if not less than or equal
AAS previous instruction (generally compare) causes ZF to have value equal to 0 and CF and OF
ADC to have same values, else no action is taken.
ADD
CMP Usage: JG dest, JNLE dest
DAA [dest: addressin the range of -128 bytes to +127 bytes from the address of instruction after
DAS JG/JNLE]
DEC
IDIV
IMUL Example:
MUL JG LABEL1; jumps to the address specified by LABEL1 if value in register AX is more
NEG positive than the value 0030H
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jg-jnle[3/9/2019 9:17:41 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JGE/JNL - Microprocessors@BITS

Arithmetic
Instructions JGE/JNL
AAA
AAD Jump if greater than or equal/ Jump if not less than
AAS previous instruction (generally compare) causes CF to have value equal to OF, else no action
ADC is taken.
ADD
CMP Usage: JGE dest, JNL dest
DAS JGE/JNL]
DEC
IDIV
IMUL Example:
MUL JGE LABEL1; jumps to the address specified by LABEL1 if value in register AX is more
NEG positive or equal to the value 0030H
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jge-jnl[3/9/2019 9:18:08 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JL/JNGE - Microprocessors@BITS

Arithmetic
Instructions JL/JNGE
AAA
AAD Jump if less than/ Jump if not greater than or equal
AAS previous instruction (generally compare) causes CF to have value not equal to OF, else no
ADC action is taken.
ADD
CMP Usage: JL dest, JNGE dest
DAS JL/JNGE]
DEC
IDIV
IMUL Example:
MUL JL LABEL1; jumps to the address specified by LABEL1 if value in register AX is more
NEG negative than the value 0030H
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jl-jnge[3/9/2019 9:18:37 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JLE/JNG - Microprocessors@BITS

Arithmetic
Instructions JLE/JNG
AAA
AAD Jump if less than or equal/ Jump if not greater than
AAS previous instruction (generally compare) causes either the ZF to have value equal to 1 or OF
ADC to have value unequal to SF, else no action is taken.
ADD
CMP Usage: JLE dest, JNG dest
DAS JLE/JNG]
DEC
IDIV
IMUL Example:
MUL JLE LABEL1; jumps to the address specified by LABEL1 if value in register AX is more
NEG negative than or equal to the value 0030H
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jle-jng[3/9/2019 9:19:04 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JMP - Microprocessors@BITS

Arithmetic
Instructions JMP
AAA
AAD Jump
AAM Description: Jumps to the destination label mentioned in the instruction. NEAR and SHORT
AAS jumps cause the IP to be updated whereas the FAR jumps cause CS and IP to be updated.
ADC
ADD Usage: JMP dest
CMP [dest: address in the range of -32768 bytes to +32767 bytes from the address of instruction
DAA after JMP]
DAS
DIV
IDIV Clocks and Size:
IMUL Operands Clocks
INC 8086 286 386 486
MUL rel8 (relative) 15 7+m 7+m 3
NEG rel16 (relative) 15 7+m 7+m 3

rel8 (relative) - - 7+m 3
SBB
reg16 (near,
SUB register indirect) 11 7+m 7+m 5
XADD reg32 (near,
Bit Manipulation register indirect) - - 7+m 5
Instructions mem16 (near,
register indirect) 18+EA 11+m 10+m 5
BSWAP
mem32 (near,
Logical AND register indirect) 24+EA 15+m 10+m 5
Logical NOT ptr16:16 (far,
Logical OR dword immed) - - 12+m 17
Logical XOR
RCL
RCR Example:
ROL JMP LABEL1; jumps to the address specified by LABEL1
ROR
SAR
Comments
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jmp[3/9/2019 9:19:31 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JNE/JNZ - Microprocessors@BITS

Arithmetic
Instructions JNE/JNZ
AAA
AAD Jump if not equal/ Jump if not zero
AAM Description: Jumps to the destination label mentioned in the instruction if the ZF is 0, else no
AAS action is taken.
ADC
ADD Usage: JNZ dest, JNE dest
DAA JNZ/JNE]
DAS
DIV
IDIV Example:
IMUL JNZ LABEL1; jumps to the address specified by LABEL1 if ZF=0
INC
MUL
NEG Comments
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jne-jnz[3/9/2019 9:20:05 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JNO - Microprocessors@BITS

Arithmetic
Instructions JNO
AAA
AAD Jump if no overflow
AAM Description: Jumps to the destination label mentioned in the instruction if the OF is 0, else
AAS no action is taken. The overflow flag is set when a signed arithmetic operation produces a
ADC result too large for the destination register or memory location to store.
ADD
CMP Usage: JNO dest
DAS JNO]
DEC
IDIV
IMUL Example:
INC ADD AL,BL; add signed bytes in AL and BL
MUL JNZ LABEL1; jumps to the address specified by LABEL1 if OF=0 after to the add
NEG instruction above
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jno[3/9/2019 9:20:31 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JNP/JPO - Microprocessors@BITS

Arithmetic
Instructions JNP/JPO
AAA
AAD Jump if no parity/ Jump if parity odd
AAS previous instruction (generally compare) causes PF to have value equal to 0, else no action is
ADC taken.
ADD
CMP Usage: JNP dest, JPO dest
DAS JNP/JPO]
DEC
IDIV
IMUL Example:
INC OR AX, AX; Set flags
MUL JNP LABEL1; even parity is expected, jumps to the address specified by LABEL1 if parity
NEG is found to be odd
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jnp-jpo[3/9/2019 9:20:58 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JNS - Microprocessors@BITS

Arithmetic
Instructions JNS
AAA
AAD Jump if not signed (Jump if positive)
AAM Description: Jumps to the destination label mentioned in the instruction if the SF is set, else
AAS no action is taken. If the sign flag is 0 it indicates a positive signed number. Hence the
ADC instruction causes a jump if the result of previous instruction is positive.
ADD
CMP Usage: JNS dest
DAS JNS]
DEC
IDIV
IMUL Example:
MUL JNS LABEL1; jumps to the address specified by LABEL1 if SF=0 due to the add
NEG instruction above
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jns[3/9/2019 9:21:35 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JO - Microprocessors@BITS

Arithmetic
Instructions JO
AAA
AAD Jump if overflow
AAM Description: Jumps to the destination label mentioned in the instruction if the OF is set, else
AAS no action is taken. The overflow flag is set when a signed arithmetic operation produces a
ADC result too large for the destination register or memory location to store.
ADD
CMP Usage: JO dest
DAS JO]
DEC
IDIV
IMUL Example:
MUL JZ LABEL1; jumps to the address specified by LABEL1 if OF=1 due to the add instruction
NEG above
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jo[3/9/2019 9:22:04 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JP/JPE - Microprocessors@BITS

Arithmetic
Instructions JP/JPE
AAA
AAD Jump if parity/ Jump if parity even
AAS previous instruction (generally compare) causes PF to have value equal to 1, else no action is
ADC taken.
ADD
CMP Usage: JP dest, JPE dest
DAS JP/JPE]
DEC
IDIV
IMUL Example:
INC OR AX, AX; Set flags
MUL JNP LABEL1; odd parity is expected, jumps to the address specified by LABEL1 if parity
NEG is found to be even
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/jp-jpe[3/9/2019 9:22:34 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

JS - Microprocessors@BITS

Arithmetic
Instructions JS
AAA
AAD Jump if signed (Jump if negative)
AAM Description: Jumps to the destination label mentioned in the instruction if the SF is 0, else no
AAS action is taken. If the sign flag is 0 it indicates a positive signed number. Hence the
ADC instruction causes a jump if the result of previous instruction is negative.
ADD
CMP Usage: JS dest
DAS JS]
DEC
IDIV
IMUL Example:
MUL JS LABEL1; jumps to the address specified by LABEL1 if SF=1 due to the add instruction
NEG above
SBB
SUB
XADD Comments
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/js[3/9/2019 9:23:01 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

LEAVE - Microprocessors@BITS

Arithmetic
Instructions LEAVE
AAA
AAD Description: Releases the local variables created by the previous ENTER instruction by
AAM restoring SP and BP to their condition before the procedure stack frame was initialized.
AAS This instruction is available from 80188 onward.
ADC
ADD Usage: LEAVE
CMP
DAA Flags: the instruction has no effect on any flags.
DAS
DEC Clocks and size:
DIV Operands Clocks Size in Bytes
IDIV 8086 286 386 486
IMUL none - 5 4 5 1
INC
MUL Example:
NEG LEAVE; set SP/ESP to BP/EBP and then pop BP/EBP
SBB
SUB
Comments
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/leave[3/9/2019 9:23:28 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

LOOP - Microprocessors@BITS

Arithmetic
Instructions LOOP
AAA
AAD Description: Contents of CX register are decremented by 1 and if the new value in CX
AAM register is non-zero, a jump is taken to the destination label mentioned in the instruction, else
AAS no action is taken.
ADC Usage: LOOP dest
ADD [dest: addressin the range of -128 bytes to +127 bytes from the address of instruction after
CMP LOOP]
DAA
DAS Flags: the instruction has no effect on any flags.
DEC
DIV Clocks and Size:
IMUL 8086 286 386 486
INC jump is taken 18 8+m 11+m 6 2
MUL jump is not

taken 5 4 ? 2 2
NEG
SBB
Example:
SUB
LOOP LABEL1; jumps to the address specified by LABEL1 if value in register CX is non-
XADD
zero after it has been decremented
Bit Manipulation
Instructions
BSWAP Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/loop[3/9/2019 9:23:57 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

LOOPE/LOOPZ - Microprocessors@BITS

Arithmetic
Instructions LOOPE/LOOPZ
AAA
AAM register is non-zero and the ZF is set, a jump is taken to the destination label mentioned in the
AAS instruction, else no action is taken.
ADC Usage: LOOPE dest, LOOPZ dest
CMP LOOPE/LOOPZ]
DAA
DEC
IMUL 8086 286 386 486
MUL jump is not

taken 5 4 ? 6 2
NEG
SBB
Example:
SUB
LOOPE LABEL1; jumps to the address specified by LABEL1 if value in register CX is
XADD
non-zero after it has been decremented and ZF is set due to previous instruction
Bit Manipulation
Instructions
BSWAP Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/loope-loopz[3/9/2019 9:24:29 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

LOOPNE/LOOPNZ - Microprocessors@BITS

Arithmetic
Instructions LOOPNE/LOOPNZ
AAA
AAM register is non-zero and the ZF is 0, a jump is taken to the destination label mentioned in the
AAS instruction, else no action is taken.
ADC Usage: LOOPNE dest, LOOPNZ dest
CMP LOOPNE/LOOPNZ]
DAA
DEC
IMUL 8086 286 386 486
MUL jump is not

taken 5 4 ? 6 2
NEG
SBB
Example:
SUB
LOOPNE LABEL1; jumps to the address specified by LABEL1 if value in register CX is
XADD
non-zero after it has been decremented and ZF is 0 due to previous instruction
Bit Manipulation
Instructions
BSWAP Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/loopne-loopnz[3/9/2019 9:25:01 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

TEST - Microprocessors@BITS

Arithmetic
Instructions TEST
AAA
AAD DESCRIPTION:
AAM Performs a logical AND of the two operands updating the flags
AAS register without saving the result.
ADC
ADD USAGE: TEST dest,src
CMP
DAA FLAGS: CF OF PF SF ZF (AF undefined)
DAS
DEC CLOCKS AND SIZES:
DIV
IDIV 8086 80286 80386 80486
IMUL reg,reg 5 2 2 1 2
INC mem,reg 9+EA 6 5 2 2-4

NEG
reg,immed 4 3 2 1 3-4
SBB accum,mem 4 3 2 1 2-3
SUB
XADD
Bit Manipulation
Instructions
BSWAP Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/program-execution-transfer-instructions/test[3/9/2019 9:25:39 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Stack Instructions - Microprocessors@BITS
Home
Arithmetic Stack Instructions
Instructions
AAA
This section contains all instructions that are involved in manipulating stacks.
AAD
AAM Subpage Listing
AAS POP
ADC POPA/POPAD
ADD POPF/POPFD
CMP PUSH
DAA PUSHA/PUSHAD
DAS PUSHF/PUSHFD
DEC
RET
DIV
IDIV
IMUL
Subpages (7):
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUSHAD
INC
PUSHF/PUSHFD
RET
MUL
NEG
Comments
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions[3/9/2019 9:26:13 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

POP - Microprocessors@BITS
Home Stack Instructions ‎ > ‎

Arithmetic
Instructions POP
AAA
AAD This instruction transfers the word at the current stack top (SS:SP) to the destination, and then
AAM increments SP by two to point to the new stack top.
AAS
The POP CS instruction is illegal.
ADC
ADD Usage POP Destination
CMP Flags None
DAA
Clocks and Size
DAS
DEC 8086 286 386 486
DIV reg16 8 5 4 4 1
IDIV reg32 4 4 1
IMUL segreg 8 5 7 3 1
mem16 17+EA 5 5 6 2-4
INC
mem32 5 6 2-4
MUL immed - - 3 2 1
NEG
SBB Example
SUB
XADD POP DS ; Copy a word from the top of the stack to DS and increment SP by 2.
Bit Manipulation
Instructions
BSWAP Comments
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions/pop[3/9/2019 9:26:44 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

POPA/POPAD - Microprocessors@BITS

Arithmetic
Instructions POPA/POPAD
AAA
AAD This instruction pops the top 8 words off the stack into the 8 general purpose 16/32 bit
AAM registers. Registers are popped in the following order: (E)DI, (E)SI, (E)BP, (E)SP, (E)DX,
(E)CX and (E)AX.
AAS
ADC The (E)SP value popped from the stack is actually discarded.
ADD
Usage POPA
CMP POPAD (386+)
DAA
Flags None
DAS
DEC Clocks and Size
8086 286 386 486
IDIV
none - 19 24 9 1
IMUL
INC
MUL
NEG
SBB Comments
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions/popa[3/9/2019 9:27:19 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

POPF/POPFD - Microprocessors@BITS

Arithmetic
Instructions POPF/POPFD
AAA
AAD The POPF (POPFD) instruction pops a word (doubleword) from the stack into the Flags
AAM Register and then increments SP by 2 (4).
AAS
Usage POPF
ADC POPFD
ADD
Flags None
CMP
DAA Clocks and Size
DAS
8086 286 386 486
DEC
none/ (dest/src) 8/12 5 5 9 1
DIV
IDIV
IMUL Comments
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions/popf-popfd[3/9/2019 9:27:50 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

PUSH - Microprocessors@BITS

Arithmetic
Instructions PUSH
AAA
AAD This instruction decrements SP by the size of the operand (two or four, byte values are sign
AAM extended) and transfers one word from source to the stack top (SS:SP).
AAS
The source can be a general purpose register, a segment register, or memory. SS & SP must
ADC be initialized before this instruction can be used.
ADD
Bytes cannot be pushed using this instruction, only words or doublewords.
CMP
DAA Usage PUSH Source
DAS
Flags None
DEC
DIV Clocks and Size
IDIV
8086 286 386 486
IMUL reg16 11 - 15 3 2 1 1
INC reg32 - - 2 1 1
MUL mem16 16 + EA 5 5 4 2-4
NEG mem32 - - 5 4 2-4

segreg 10 - 14 3 2 3 1
SBB
immed - 3 2 1 2-3
SUB
XADD
Example
Bit Manipulation
Instructions
PUSH BX ; Decrement SP by 2, copy BX to stack
BSWAP
Logical AND
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions/push[3/9/2019 9:28:24 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

PUSHA/PUSHAD - Microprocessors@BITS

Arithmetic
Instructions PUSHA/PUSHAD
AAA
AAD Pushes all general purpose registers onto the stack in the following order: (E)AX, (E)CX,
AAM (E)DX, (E)BX, (E)SP, (E)BP, (E)SI, (E)DI. (The EAX etc. values are pushed when the
PUSHAD instruction is used.)
AAS
ADC The value of SP pushed into the stack is its value before the actual push of SP.
ADD
Usage PUSHA
CMP PUSHAD (386+)
DAA
Flags None
DAS
DEC Clocks and Size
8086 286 386 486
IDIV
none - 19 24 11 1
IMUL
INC
MUL Comments
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions/pusha[3/9/2019 9:28:58 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

PUSHF/PUSHFD - Microprocessors@BITS

Arithmetic
Instructions PUSHF/PUSHFD
AAA
AAD This instruction transfers the Flags Register onto the stack. PUSHF saves a 16 bit value
AAM while PUSHFD saves a 32 bit value.
AAS
The stack pointer is decremented by 2.
ADC
ADD Usage PUSHF
PUSHFD
CMP
DAA Flags None
DAS
Clocks and Size
DIV 8086 286 386 486
IDIV none/ (dest/src) 10-14 3 4 4 1
IMUL
INC Comments
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions/pushf[3/9/2019 9:29:29 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

RET - Microprocessors@BITS

Arithmetic
Instructions RET
AAA
AAD DESCRIPTION:
AAM Transfers control from a procedure back to the instruction addre
AAS saved on the stack. "n bytes" is an optional number of bytes to
ADC release. Far returns pop the IP followed by the CS, while near
ADD returns pop only the IP register.
CMP
DAA USAGE: RET nBytes
DAS RETF nBytes
DEC RETN nBytes
DIV
IDIV FLAGS:NONE
IMUL CLOCKS AND SIZES:
INC
MUL
8086 80286 80386 80486
NEG retn 16/20 11+m 10+m 5 1
SBB retn immed 20/24 11+m 10+m 5 3
SUB retf 26/34 15+m 18+m 13 1
XADD retf immed 25/33 15+m 18+m 14 3
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Comments
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/stack-instructions/ret[3/9/2019 9:30:00 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

String Instructions - Microprocessors@BITS
Home
Arithmetic String Instructions
Instructions
AAA
This section describes the various string-related operations that are supported by the
AAD
Intel x86 family.
AAM
AAS Subpage Listing
ADC CMPS/CMPSB/CMPSW
ADD INS/INSB/INSW
CMP LODS/LODSB/LODSW
DAA MOVS/MOVSB/MOVSW
DAS OUTS/OUTSB/OUTSW
DEC REP
DIV
REPE/REPNE/REPZ/REPNZ
IDIV
SCAS/SCASB/SCASW
IMUL
STOS/STOSB/STOSW
INC
MUL
NEG
Subpages (9):
CMPS/CMPSB/CMPSW
INS/INSB/INSW
LODS/LODSB/LODSW
SBB
MOVS/MOVSB/MOVSW
OUTS/OUTSB/OUTSW
REP
SUB
REPE/REPNE/REPZ/REPNZ
SCAS/SCASB/SCASW
STOS/STOSB/STOSW
XADD
Bit Manipulation
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions[3/9/2019 9:30:35 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

CMPS/CMPSB/CMPSW - Microprocessors@BITS
Home String Instructions ‎ > ‎

Arithmetic
Instructions CMPS/CMPSB/CMPSW
AAA
AAD The CMPSB(W) instruction can be used to compare a byte(word) in one string (DS:offset in
AAM SI) with a byte (word) in another string (ES:offset in DI). The comparison is executed by
AAS subtracting the byte (word) in DI from the byte (word) in SI.
ADC
ADD The Direction Flag (DF) value determines whether SI and DI are to be incremented (DF =
CMP 0) or decremented (DF = 1) after each move. Increments/decrements happen by 1 for byte
DAA strings and by 2 for word strings.
DAS
DEC The CMPSB(W) instruction is almost always used with a REP(E/Z) prefix to compare
DIV multiple words/bytes.
IDIV
IMUL The result of the comparison can be gleaned from flag updates.
INC
MUL
Usage CMPS src, dest
NEG
CMPSB
SBB CMPSW
SUB
XADD
Flags AF,CF,OF,PF,SF,ZF
Bit Manipulation
Instructions
Clocks and Size
BSWAP
Logical AND 8086 286 386 486
Logical NOT none/ (dest/src) 22 8 10 8 1
Logical OR
Logical XOR Example
RCL
RCR Compare, till a difference is found, two data items of 100 bytes each at STR1 and STR2
ROL
ROR MOV SI, STR1
SAR MOV DI, STR2
SHL/SAL MOV CX, 100
SHR CLD; Clear the direction flag
https://sites.google.com/site/microprocessorsbits/string-instructions/cmps-cmpsb-cmpsw[3/9/2019 9:31:07 PM]

SHRD/SHLD
Data Transfer REPE CMPSB
CMPXCHG
LAHF
LAR
Comments
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

INS/INSB/INSW - Microprocessors@BITS

Arithmetic
Instructions INS/INSB/INSW
AAA
AAD Loads data from a port to the destination [ES:DI]. DI is incremented or decremented
AAM depending on the value of DF.
AAS
ADC
Usage INS dest, port
ADD
INSB
CMP
INSW
DAA
DAS
Flags None
DEC
DIV
Clocks and Size
IMUL 8086 286 386 486
INC dest,port Not Implemented 5 15 17 1
MUL
NEG Example
SBB Move a word from <port address> to STR
SUB
XADD MOV DX, <port address>
Bit Manipulation MOV DI, offset STR
Instructions
BSWAP INSW
Logical AND
Logical NOT
Comments
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/ins-insb-insw[3/9/2019 9:31:39 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

LODS/LODSB/LODSW - Microprocessors@BITS

Arithmetic
Instructions LODS/LODSB/LODSW
AAA
AAD This instruction copies a byte (word) of string from the location pointed to by SI. The SI
AAM value is automatically incremented (depending on the DF value) after each movement by 1
AAS byte (2 bytes) for a byte string (word string).
ADC
ADD This instruction is preferred over MOV for string manipulation due to its treatment of the
CMP SI pointer and the ability to use it with REP prefixes.
DAA
DAS
Usage LODS <String>
DEC
LODSB
DIV
LODSW
IDIV
IMUL
Flags None
INC
MUL
Clocks and Size
NEG Operands Clocks Size in Bytes
SBB 8086 286 386 486
SUB none/ (dest/src) 12/16 5 5 5 1
XADD
Bit Manipulation Example
Instructions CLD
BSWAP MOV SI, Offset STR
Logical AND LODSB
Logical NOT
Logical OR
Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/lods-lodsb-lodsw[3/9/2019 9:32:13 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

MOVS/MOVSB/MOVSW - Microprocessors@BITS

Arithmetic
Instructions MOVS/MOVSB/MOVSW
AAA
AAD This instruction copies a byte or a word from a location in the data segment [DS:SI] to
AAM location in the extra segment [ES:DI]. The offset in the data segment for the source is to be
AAS stored in the SI register and the offset for the destination in the extra segment is to be stored
ADC in the DI register.
ADD
CMP For multiple byte/word movement, the value stored in the CX register by the user functions as
DAA a counter. After each move, SI and DI are automatically adjusted to point to the next source
DAS and destination respectively.
DEC
DIV The Direction Flag (DF) value determines whether SI and DI are to be incremented (DF =
IDIV 0) or decremented (DF = 1) after each move.
IMUL
INC The MOVSB instruction tells the assembler to move data as bytes; the MOVSW implies the
MUL string is to be moved as words.
NEG
SBB
Usage MOVS dest, src (This usage is misleading; movement of data still happens from
SUB DS:SI to ES:DI)
XADD
MOVSB
Bit Manipulation MOVSW
Instructions
BSWAP
Flags None
Logical AND
Logical NOT
Clocks and Size
Logical OR
Logical XOR
RCL 8086 286 386 486
RCR none/ (dest/src) 18 5 7 7 1
ROL
ROR Example
SAR
SHL/SAL To move a string of length 4 bytes from SRC to DST
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/movs-movsb-movsw[3/9/2019 9:32:45 PM]

SHRD/SHLD MOV SI, SRC

Data Transfer MOV DI, DST
CMPXCHG MOV CX, 04H
LAHF CLD; Clear the direction flag
LAR
LDS/LES REP MOVSB
LEA
MOV
Comments
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

OUTS/OUTSB/OUTSW - Microprocessors@BITS

Arithmetic
Instructions OUTS/OUTSB/OUTSW
AAA
AAD Transfers a data byte/word from [DS:SI] to a port specified in the DX register. SI is
AAM incremented/decremented depending on the value of the DF.
AAS
ADC
Usage OUTS port, src
ADD
OUTSB
CMP
OUTSW
DAA
DAS
Flags None
DEC
DIV
Clocks and Size
IMUL 8086 286 386 486
INC string Not implmented 5 14 17 1
MUL
NEG Example
SBB Move a byte from STR to the port PORT
SUB
XADD MOV SI, offset STR
Bit Manipulation MOV DX, <addr. PORT>
Instructions
BSWAP OUTSB
Logical AND
Logical NOT
Comments
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/outs-outsb-outsw[3/9/2019 9:33:20 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

REP - Microprocessors@BITS

Arithmetic
Instructions REP
AAA
AAD REP is a prefix written before one of the string instructions. It is used for repeating an
AAM instruction count number of times, where count is stored in the CX register. After every
AAS operation the CX register is decremented and the zero flag is tested; the process continues till
ADC CX = 0.
ADD
CMP
Usage REP <String-Instruction>
DAA
DAS
Flags Depend on String instruction used
DEC
DIV
Clocks and Size
IMUL 8086 286 386 486
INC none 2 2 2 1 1
MUL
NEG Example
SBB
SUB REP MOVSB
XADD (Should be preceded with a MOV CX, count instruction somewhere in the code.)
Bit Manipulation
Instructions
BSWAP
Logical AND
Comments
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/rep[3/9/2019 9:33:56 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

REPE/REPNE/REPZ/REPNZ - Microprocessors@BITS

Arithmetic
Instructions REPE/REPNE/REPZ/REPNZ
AAA
AAD
REPE and REPZ are mnemonics for the same prefix; they stand for Repeat if Equal and
AAM Repeat if Zero respectively. REPE/REPZ causes the succeeding string instruction to be
AAS repeated as long as the comapred bytes or words are equal (ZF = 1) and CX is not yet
ADC counted down to zero.
ADD
CMP The REPNE and the REPNZ instructions stand for Repeat if Not Equal and Repeat if Not
DAA Zero respectively and cause the string instruction to be repeated until the compared bytes or
DAS words are equal (ZF = 1) or until CX = 0 (end of string.)
DEC
DIV CX is decremented and the zero flag is tested after each operation.
IDIV
IMUL
Usage REPE/REPE/REPZ/REPNZ <String Instruction>
INC
MUL
Flags Depend on string instruction used
NEG
SBB
Clocks and Size
SUB Operands Clocks Size in Bytes
XADD 8086 286 386 486
Bit Manipulation none 2 2 2 1 1
Instructions
BSWAP Example
Logical AND REPNE SCASW
Logical NOT Scans a string of words (i.e. repeats SCASW) until a word in the string matches the word in
Logical OR AX (as dictated by the SCASW instruction) or until all of the string has been scanned.
Logical XOR
RCL
Comments
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/repe-repne-repz-repnz[3/9/2019 9:34:31 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

SCAS/SCASB/SCASW - Microprocessors@BITS

Arithmetic
Instructions SCAS/SCASB/SCASW
AAA
AAD
SCAS(/B/W) compares a byte in AL or a word in AX with a byte or word pointed to by DI
AAM in ES. The direction flag determines the direction of scan.
AAS Used with the REP prefix to find the first occurrence of a specified byte(word) in a string.
ADC
ADD
Usage SCAS <String>
CMP
SCASB
DAA
SCASW
DAS
DEC
Flags AF,PF,OF,PF,SF,ZF
DIV
IDIV
Clocks and Size
INC 8086 286 386 486
MUL string 15 7 7 6 1
NEG
SBB Example
SUB Scan a string STR of 100 characters for the 'space' character, 20H
XADD
Bit Manipulation MOV CX, 100
Instructions MOV DI, offset STR
BSWAP MOV AL, 20H
Logical AND REPNE SCASB
Logical NOT
Logical OR
Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/scas-scasb-scasw[3/9/2019 9:35:07 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

STOS/STOSB/STOSW - Microprocessors@BITS

Arithmetic
Instructions STOS/STOSB/STOSW
AAA
AAD The STOS instruction copies a byte (word) from AL (AX) to a memory location stored in
AAM [ES:DI]. DI is automatically incremented after the copy, the DF determines the
AAS increment/decrement.
ADC
ADD In effect, it replaces a string element with a byte (word) from AL (AX).
CMP
DAA
Usage STOS <String>
DAS
STOSB
DEC
STOSW
DIV
IDIV
Flags None
IMUL
INC
Clocks and Size
NEG 8086 286 386 486
SBB string 11 3 4 5 1
SUB
XADD Example
Bit Manipulation Copy AX to STR
Instructions
BSWAP MOV DI, offset STR
Logical AND STOSW
Logical NOT
Logical OR
Comments
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/string-instructions/stos-stosb-stosw[3/9/2019 9:35:37 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Arithmetic
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Instructions
AAA
Collapse all
AAD
AAM
Arithmetic Instructions
AAS
Bit Manipulation Instructions
ADC
Data Transfer
ADD
Home
CMP
DAA Miscellaneous
DAS Processor Control Instructions
DEC Program Execution Transfer Instructions
DIV Stack Instructions
IDIV String Instructions

IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/system/app/pages/sitemap/hierarchy[3/9/2019 9:37:20 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap
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Recent site activity - Microprocessors@BITS
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Arithmetic
Recent site activity
Instructions
AAA Jul 10, 2015, 12:56 PM K.R. Anupama edited Logical AND
AAD Dec 24, 2014, 10:57 AM K.R. Anupama edited Home
AAM Jan 23, 2014, 10:20 PM pratik gangwal edited CALL
AAS Jan 23, 2014, 10:08 PM pratik gangwal created CALL
ADC Jan 20, 2014, 3:59 PM pratik gangwal edited XADD
ADD Jan 20, 2014, 3:57 PM pratik gangwal edited XADD
CMP Jan 20, 2014, 3:51 PM pratik gangwal created XADD
DAA Jan 20, 2014, 3:49 PM pratik gangwal edited SHRD/SHLD
DAS Jan 20, 2014, 3:26 PM pratik gangwal edited SHRD/SHLD
DEC Jan 20, 2014, 3:23 PM pratik gangwal created SHRD/SHLD
DIV Jan 20, 2014, 3:18 PM pratik gangwal edited TEST
IDIV Jan 20, 2014, 3:09 PM pratik gangwal created TEST
Jan 20, 2014, 2:49 PM pratik gangwal edited LAR

IMUL
Jan 20, 2014, 2:44 PM pratik gangwal created LAR
INC
Jan 20, 2014, 2:40 PM pratik gangwal edited RET
MUL
Jan 20, 2014, 11:50 AM Rohit Sant edited Home
NEG
SBB
SUB
Jan 20, 2014, 9:23 AM Rohit Sant edited String Instructions
XADD
Jan 20, 2014, 9:23 AM Rohit Sant edited Stack Instructions
Bit Manipulation
Jan 20, 2014, 9:22 AM Rohit Sant edited Program Execution Transfer Instructions
Instructions
Jan 20, 2014, 9:22 AM Rohit Sant edited Miscellaneous
BSWAP
Jan 20, 2014, 9:21 AM Rohit Sant edited Processor Control Instructions
Logical AND
Jan 20, 2014, 9:21 AM Rohit Sant deleted HLT
Logical NOT
Jan 20, 2014, 9:20 AM Rohit Sant deleted Email_Page_Untitled
Logical OR
Logical XOR older | newer
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges[3/9/2019 9:37:50 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Home
Arithmetic Home
Instructions
AAA
AAD Clock
AAM
AAS
8:46 PM
Jun 27, 51155 (Mon)
ADC
ADD
CMP Copyright
DAA
The Instruction Set Dictionary is subject to copyright protection and may be used
DAS
only for private study by persons who are enrolled in this course. Any other use of
DEC
these materials must be with the express, written permission of any of the course
DIV
instructors from Goa campus
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/home[3/9/2019 9:40:22 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT

Program
Execution
Transfer
Instructions
CALL
ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
…

PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions
CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Subpages - Microprocessors@BITS
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Arithmetic
Subpages
Instructions
AAA Item
AAD CALL
AAM ENTER
AAS INT
ADC INTO
ADD IRET
CMP JAE/JNB
JA/JNBE
DAA
JBE/JNA
DAS
JB/JNAE/JC
DEC
JC
DIV
JCXZ
IDIV
JE/JZ
IMUL
JGE/JNL
INC
JG/JNLE
MUL
JLE/JNG
NEG
JL/JNGE
SBB
JMP
SUB JNE/JNZ
XADD JNO
Bit Manipulation JNP/JPO
Instructions JNS
BSWAP JO
Logical AND JP/JPE
Logical NOT JS
Logical OR LEAVE
Logical XOR LOOP
RCL LOOPE/LOOPZ
RCR LOOPNE/LOOPNZ
ROL TEST
ROR
1-29 of 29
SAR
SHL/SAL
SHR
https://sites.google.com/...its/system/app/pages/subPages?path=/program-execution-transfer-instructions[3/9/2019 9:40:56 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Arithmetic
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AAA
We're sorry, but we were unable to locate the page you requested.
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/...oprocessorsbits/system/errors/NodeNotFound?suri=wuid:gx:38ba0a858e008e9e[3/9/2019 9:41:30 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Arithmetic
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Instructions
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/...icroprocessorsbits/system/errors/NodeNotFound?suri=wuid:gx:4ffcb698fc30ed64[3/9/2019 9:42:01 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

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Arithmetic
Instructions
AAA Jan 20, 2014, 9:20 AM Rohit Sant edited Bit Manipulation Instructions
AAD Jan 20, 2014, 9:19 AM Rohit Sant edited Arithmetic Instructions
AAM Jan 20, 2014, 9:18 AM Rohit Sant edited BT
AAS Jan 20, 2014, 9:13 AM Rohit Sant created BT
ADC Jan 20, 2014, 9:11 AM Rohit Sant edited MOVZX
ADD Jan 20, 2014, 9:07 AM Rohit Sant created MOVZX
CMP Jan 20, 2014, 9:07 AM Rohit Sant edited MOV
DAA Jan 20, 2014, 9:06 AM Rohit Sant edited LAHF
DAS Jan 20, 2014, 9:02 AM Rohit Sant created LAHF
DEC Jan 20, 2014, 12:45 AM shridevi muthkhod edited JMP
DIV Jan 20, 2014, 12:39 AM pratik gangwal created RET
IDIV Jan 20, 2014, 12:34 AM pratik gangwal edited SAHF
Jan 20, 2014, 12:29 AM pratik gangwal created SAHF

IMUL
Jan 19, 2014, 11:46 PM shridevi muthkhod edited JMP
INC
Jan 19, 2014, 11:40 PM shridevi muthkhod created JMP
MUL
Jan 19, 2014, 11:39 PM shridevi muthkhod edited LOOPNE/LOOPNZ
NEG
Jan 19, 2014, 11:38 PM shridevi muthkhod edited LOOPE/LOOPZ
SBB
Jan 19, 2014, 11:36 PM shridevi muthkhod edited LOOP
SUB
Jan 19, 2014, 11:32 PM shridevi muthkhod edited JC
XADD
Jan 19, 2014, 11:29 PM shridevi muthkhod edited JA/JNBE
Bit Manipulation
Jan 19, 2014, 11:22 PM shridevi muthkhod edited ENTER
Instructions
Jan 19, 2014, 11:21 PM shridevi muthkhod edited ENTER
BSWAP
Jan 19, 2014, 11:20 PM shridevi muthkhod edited LEAVE
Logical AND
Jan 19, 2014, 11:08 PM shridevi muthkhod edited LEAVE
Logical NOT
Jan 19, 2014, 11:04 PM shridevi muthkhod created LEAVE
Logical OR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/site/microprocessorsbits/system/app/pages/recentChanges?offset=25[3/9/2019 9:42:33 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

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‪English (United Kingdom)‬ Help Privacy Terms
https://accounts.google.com/...followup=https://sites.google.com/site/sites/system/app/pages/meta/terms[3/9/2019 9:42:52 PM]

https://accounts.google.com/...followup=https://sites.google.com/site/sites/system/app/pages/meta/terms[3/9/2019 9:42:52 PM]

Home
Arithmetic
Instructions
AAA Jan 16, 2014, 5:26 PM Rohit Sant edited CLI
AAD Jan 16, 2014, 5:23 PM Rohit Sant created CLI
AAM Jan 16, 2014, 5:23 PM Rohit Sant edited CLD
AAS Jan 16, 2014, 5:20 PM Rohit Sant created CLD
ADC Jan 16, 2014, 5:19 PM Rohit Sant edited CLC
ADD Jan 16, 2014, 5:18 PM Rohit Sant created CLC
CMP Jan 16, 2014, 5:17 PM Rohit Sant edited STD
DAA Jan 16, 2014, 5:17 PM Rohit Sant deleted STD
DAS Jan 16, 2014, 5:16 PM Rohit Sant edited STI
DEC Jan 16, 2014, 5:15 PM Rohit Sant edited STI
DIV Jan 16, 2014, 5:10 PM Rohit Sant created STI
IDIV Jan 16, 2014, 5:10 PM Rohit Sant edited STD
Jan 16, 2014, 5:07 PM Rohit Sant created STD

IMUL
Jan 16, 2014, 5:07 PM Rohit Sant created STD
INC
Jan 16, 2014, 5:06 PM Rohit Sant edited STC
MUL
Jan 16, 2014, 5:04 PM Rohit Sant created STC
NEG
Jan 16, 2014, 5:03 PM Rohit Sant created Processor Control Instructions
SBB
Jan 15, 2014, 10:08 PM shridevi muthkhod edited Program Execution Transfer Instructions
SUB
Jan 15, 2014, 9:47 PM shridevi muthkhod created Program Execution Transfer Instructions
XADD
Jan 15, 2014, 6:52 PM Rohit Sant edited POPF/POPFD
Bit Manipulation
Jan 15, 2014, 6:49 PM Rohit Sant created POPF/POPFD
Instructions
Jan 15, 2014, 6:49 PM Rohit Sant edited PUSHF/PUSHFD
BSWAP
Jan 15, 2014, 6:45 PM Rohit Sant created PUSHF
Logical AND
Jan 15, 2014, 6:43 PM Rohit Sant edited POPA/POPAD
Logical NOT
Jan 15, 2014, 6:35 PM Rohit Sant edited PUSHA/PUSHAD
Logical OR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Home
Arithmetic
Page not found
Instructions
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/...roprocessorsbits/system/errors/NodeNotFound?suri=wuid:gx:788a7168d4310f8e[3/9/2019 9:47:59 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Home
Arithmetic
Instructions
AAA Jan 15, 2014, 6:34 PM Rohit Sant edited PUSHA/PUSHAD
AAD Jan 15, 2014, 6:33 PM Rohit Sant edited POPA
AAM Jan 15, 2014, 6:28 PM Rohit Sant created POPA
AAS Jan 15, 2014, 6:27 PM Rohit Sant edited PUSHA
ADC Jan 15, 2014, 6:23 PM Rohit Sant created PUSHA
ADD Jan 15, 2014, 6:21 PM Rohit Sant edited POP
CMP Jan 15, 2014, 6:15 PM Rohit Sant created POP
DAA Jan 15, 2014, 6:14 PM Rohit Sant edited PUSH
DAS Jan 15, 2014, 6:05 PM Rohit Sant created PUSH
DEC Jan 15, 2014, 6:02 PM Rohit Sant edited Stack Instructions
DIV Jan 15, 2014, 6:02 PM Rohit Sant created Stack Instructions
IDIV Jan 13, 2014, 5:43 PM Rohit Sant edited CWD
Jan 13, 2014, 5:39 PM Rohit Sant edited CWD

IMUL
Jan 13, 2014, 5:35 PM Rohit Sant created CWD
INC
Jan 13, 2014, 5:35 PM Rohit Sant edited CBW
MUL
NEG
SBB
Jan 13, 2014, 4:52 PM Rohit Sant created CBW
SUB
Jan 13, 2014, 4:51 PM Rohit Sant edited Miscellaneous
XADD
Jan 13, 2014, 4:49 PM Rohit Sant created Miscellaneous
Bit Manipulation
Jan 13, 2014, 4:48 PM Rohit Sant edited AAD
Instructions
Jan 13, 2014, 4:42 PM Rohit Sant edited AAM
BSWAP
Jan 13, 2014, 4:25 PM Rohit Sant created AAD
Logical AND
Jan 13, 2014, 4:25 PM Rohit Sant edited IDIV
Logical NOT
Jan 13, 2014, 2:18 PM Rohit Sant edited IDIV
Logical OR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Home
Arithmetic
Instructions
AAA Jan 13, 2014, 2:06 PM Rohit Sant created IDIV
AAD Jan 13, 2014, 11:17 AM Rohit Sant edited DIV
AAM Jan 13, 2014, 11:01 AM Rohit Sant created DIV
AAS Jan 13, 2014, 10:59 AM Rohit Sant edited AAM
ADC Jan 12, 2014, 11:45 AM pratik gangwal edited DAS
ADD Jan 12, 2014, 11:41 AM pratik gangwal edited DAS
CMP Jan 12, 2014, 11:38 AM pratik gangwal edited DAS
DAA Jan 12, 2014, 11:38 AM pratik gangwal created DAS
DAS Jan 12, 2014, 11:36 AM pratik gangwal edited AAS
DEC Jan 12, 2014, 11:31 AM pratik gangwal edited AAS
DIV Jan 12, 2014, 11:27 AM pratik gangwal created AAS
IDIV Jan 12, 2014, 11:26 AM pratik gangwal edited DEC
Jan 12, 2014, 11:26 AM pratik gangwal edited DAA

IMUL
Jan 12, 2014, 11:24 AM pratik gangwal edited DEC
INC
MUL
NEG
SBB
Jan 12, 2014, 11:21 AM pratik gangwal created DEC
SUB
Jan 12, 2014, 11:20 AM pratik gangwal edited CMP
XADD
Jan 12, 2014, 11:08 AM pratik gangwal created DAA
Bit Manipulation
Jan 12, 2014, 11:07 AM pratik gangwal edited AAA
Instructions
Jan 12, 2014, 10:54 AM pratik gangwal created AAA
BSWAP
Jan 12, 2014, 10:53 AM pratik gangwal edited SUB
Logical AND
Jan 12, 2014, 10:45 AM pratik gangwal created SUB
Logical NOT
Jan 12, 2014, 10:40 AM pratik gangwal edited INC
Logical OR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Home
Arithmetic
Instructions
AAA Jan 12, 2014, 10:34 AM pratik gangwal edited SBB
AAD Jan 12, 2014, 10:32 AM pratik gangwal edited SBB
AAM Jan 12, 2014, 10:30 AM pratik gangwal edited CMP
AAS Jan 12, 2014, 10:26 AM pratik gangwal created INC
ADC Jan 12, 2014, 10:25 AM pratik gangwal edited ADC
ADD Jan 12, 2014, 10:20 AM pratik gangwal created ADC
CMP Jan 12, 2014, 10:16 AM pratik gangwal edited SBB
DAA Jan 12, 2014, 10:16 AM pratik gangwal edited ADD
DAS Jan 12, 2014, 10:16 AM pratik gangwal edited NEG
DEC Jan 12, 2014, 10:16 AM pratik gangwal edited CMP
DIV Jan 12, 2014, 10:14 AM pratik gangwal created CMP
IDIV Jan 12, 2014, 10:13 AM pratik gangwal edited SBB
Jan 12, 2014, 10:13 AM pratik gangwal edited NEG

IMUL
INC
MUL
Jan 12, 2014, 10:06 AM pratik gangwal created NEG
NEG
Jan 12, 2014, 10:03 AM pratik gangwal edited SBB
SBB
Jan 12, 2014, 9:49 AM pratik gangwal edited SBB
SUB
Jan 12, 2014, 9:45 AM pratik gangwal created SBB
XADD
Jan 11, 2014, 5:43 PM pratik gangwal created ADD
Bit Manipulation
Jan 10, 2014, 9:09 PM Rohit Sant edited AAM
Instructions
Jan 10, 2014, 8:11 PM Rohit Sant created AAM
BSWAP
Jan 10, 2014, 7:50 PM Rohit Sant edited IMUL
Logical AND
Jan 10, 2014, 7:35 PM Rohit Sant created IMUL
Logical NOT
Jan 10, 2014, 7:34 PM Rohit Sant edited MUL
Logical OR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Home
Arithmetic
Instructions
AAA Jan 10, 2014, 7:11 PM Rohit Sant created MUL
AAD Jan 10, 2014, 7:07 PM Rohit Sant edited OUTS/OUTSB/OUTSW
AAM Jan 10, 2014, 5:53 PM Rohit Sant edited OUTS/OUTSB/OUTSW
AAS Jan 10, 2014, 5:44 PM Rohit Sant created OUTS/OUTSB/OUTSW
ADC Jan 10, 2014, 5:42 PM Rohit Sant edited INS/INSB/INSW
ADD Jan 10, 2014, 5:18 PM Rohit Sant created INS/INSB/INSW
CMP Jan 9, 2014, 7:13 PM Rohit Sant edited STOS/STOSB/STOSW
DAA Jan 9, 2014, 6:00 PM Rohit Sant created STOS/STOSB/STOSW
DAS Jan 9, 2014, 5:56 PM Rohit Sant edited LODS/LODSB/LODSW
DEC Jan 9, 2014, 5:36 PM Rohit Sant created LODS/LODSB/LODSW
DIV Jan 9, 2014, 5:35 PM Rohit Sant edited SCAS/SCASB/SCASW
IDIV Jan 9, 2014, 5:35 PM Rohit Sant edited SCAS/SCASB/SCASW
Jan 9, 2014, 5:18 PM pratik gangwal edited RCL

IMUL
Jan 9, 2014, 5:18 PM pratik gangwal edited RCR
INC
MUL
NEG
Jan 9, 2014, 5:13 PM pratik gangwal created RCR
SBB
Jan 9, 2014, 5:12 PM pratik gangwal edited RCL
SUB
Jan 9, 2014, 5:07 PM Rohit Sant created SCAS/SCASB/SCASW
XADD
Jan 9, 2014, 4:51 PM pratik gangwal created RCL
Bit Manipulation
Jan 9, 2014, 4:48 PM pratik gangwal edited ROL
Instructions
Jan 9, 2014, 4:48 PM pratik gangwal edited ROR
BSWAP
Logical AND
Logical NOT
Jan 9, 2014, 4:42 PM pratik gangwal created ROR
Logical OR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Home
Arithmetic
Instructions
AAA Jan 9, 2014, 4:06 PM pratik gangwal edited SHL/SAL
AAD Jan 9, 2014, 4:05 PM pratik gangwal edited ROL
AAM Jan 9, 2014, 4:04 PM pratik gangwal edited SHL/SAL
AAS Jan 9, 2014, 4:01 PM pratik gangwal edited ROL
ADC Jan 9, 2014, 3:58 PM pratik gangwal edited SAR
ADD Jan 9, 2014, 3:58 PM pratik gangwal edited ROL
CMP Jan 9, 2014, 3:56 PM pratik gangwal created SHL/SAL
DAA Jan 9, 2014, 3:55 PM pratik gangwal created ROL
DAS Jan 9, 2014, 3:52 PM pratik gangwal edited Logical XOR
DEC Jan 9, 2014, 3:52 PM pratik gangwal edited SAR
DIV Jan 9, 2014, 3:51 PM pratik gangwal edited SAR
IDIV Jan 9, 2014, 3:44 PM pratik gangwal created Logical XOR
Jan 9, 2014, 3:39 PM pratik gangwal edited SHR

IMUL
Jan 9, 2014, 3:38 PM pratik gangwal created SAR
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Jan 9, 2014, 3:19 PM pratik gangwal edited Logical OR
Logical OR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Home
Arithmetic
Instructions
AAA Jan 9, 2014, 3:16 PM pratik gangwal edited SHR
AAD Jan 9, 2014, 3:12 PM pratik gangwal created SHR
AAM Jan 9, 2014, 3:10 PM pratik gangwal edited Logical OR
AAS Jan 9, 2014, 3:10 PM pratik gangwal created Logical OR
ADC Jan 9, 2014, 3:03 PM pratik gangwal edited Logical NOT
ADD Jan 9, 2014, 2:50 PM pratik gangwal edited Logical AND
CMP Jan 9, 2014, 2:49 PM pratik gangwal edited Logical AND
DAA Jan 9, 2014, 2:43 PM pratik gangwal edited Logical AND
DAS Jan 9, 2014, 2:25 PM pratik gangwal created Logical AND
DEC Jan 9, 2014, 2:24 PM pratik gangwal edited Logical NOT
DIV Jan 9, 2014, 2:22 PM pratik gangwal edited Logical NOT
IDIV Jan 9, 2014, 9:55 AM pratik gangwal created Logical NOT
Jan 9, 2014, 9:47 AM pratik gangwal edited Bit Manipulation Instructions

IMUL
Jan 9, 2014, 9:41 AM pratik gangwal created Bit Manipulation Instructions
INC
Jan 8, 2014, 9:24 AM Rohit Sant edited CMPS/CMPSB/CMPSW
MUL
Jan 8, 2014, 9:08 AM Rohit Sant created CMPS/CMPSB/CMPSW
NEG
Jan 8, 2014, 8:54 AM Rohit Sant edited MOVS/MOVSB/MOVSW
SBB
Jan 8, 2014, 8:50 AM Rohit Sant edited REPE/REPNE/REPZ/REPNZ
SUB
Jan 8, 2014, 8:47 AM Rohit Sant edited MOVS/MOVSB/MOVSW
XADD
Jan 8, 2014, 8:32 AM Rohit Sant created MOVS/MOVSB/MOVSW
Bit Manipulation
Jan 6, 2014, 10:59 PM Rohit Sant edited REPE/REPNE/REPZ/REPNZ
Instructions
Jan 6, 2014, 10:39 PM Rohit Sant edited REPE/REPNE/REPZ/REPNZ
BSWAP
Jan 6, 2014, 10:17 PM Rohit Sant created REPE/REPNE/REPZ/REPNZ
Logical AND
Jan 6, 2014, 10:15 PM Rohit Sant edited REP
Logical NOT
Jan 4, 2014, 9:33 PM Rohit Sant edited REP
Logical OR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Home
Arithmetic
Instructions
AAA Jan 4, 2014, 8:33 PM Rohit Sant created REP
AAD Jan 4, 2014, 8:31 PM Rohit Sant edited String Instructions
AAM Jan 4, 2014, 8:26 PM Rohit Sant created String Instructions
AAS Dec 24, 2013, 2:16 PM Rohit Sant edited Arithmetic Instructions
ADC Dec 24, 2013, 2:14 PM Rohit Sant edited Arithmetic Instructions
ADD Dec 24, 2013, 2:13 PM Rohit Sant created Arithmetic Instructions
CMP Dec 14, 2013, 5:03 PM Rohit Sant edited LDS/LES
DAA Dec 14, 2013, 4:47 PM Rohit Sant created LDS/LES
DAS Dec 14, 2013, 4:36 PM Rohit Sant edited LEA
DEC Dec 14, 2013, 4:27 PM Rohit Sant edited LEA
DIV Dec 14, 2013, 4:19 PM Rohit Sant created LEA
IDIV Dec 14, 2013, 4:15 PM Rohit Sant edited XLAT(B)
Dec 14, 2013, 2:55 PM Rohit Sant edited XLAT(B)

IMUL
Dec 14, 2013, 2:31 PM Rohit Sant created XLAT
INC
Dec 14, 2013, 2:25 PM Rohit Sant edited XCHG
MUL
Dec 14, 2013, 2:15 PM Rohit Sant created XCHG
NEG
Dec 14, 2013, 1:07 PM Rohit Sant edited MOVSX [386+]
SBB
Dec 14, 2013, 1:05 PM Rohit Sant edited MOVSX [386+]
SUB
Dec 14, 2013, 12:05 PM Rohit Sant created MOVSX
XADD
Dec 14, 2013, 11:59 AM Rohit Sant edited MOVS
Bit Manipulation
Dec 14, 2013, 11:20 AM Rohit Sant created MOVS
Instructions
Dec 13, 2013, 5:42 PM Rohit Sant edited Move
BSWAP
Logical AND
Logical NOT
Logical OR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
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Arithmetic
Instructions
AAA Dec 13, 2013, 5:28 PM Rohit Sant edited Move
AAD Dec 13, 2013, 5:25 PM Rohit Sant edited Move
AAM Dec 13, 2013, 2:36 PM Rohit Sant edited Move
AAS Dec 10, 2013, 11:12 PM Rohit Sant edited Home
ADC Dec 10, 2013, 11:06 PM Rohit Sant edited Home
ADD Dec 10, 2013, 11:02 PM Rohit Sant edited Home
CMP Dec 10, 2013, 11:01 PM Rohit Sant edited Home
DAA Dec 10, 2013, 10:58 PM Rohit Sant edited Home
DAS Dec 10, 2013, 10:35 PM Rohit Sant edited Move
DEC Dec 10, 2013, 10:25 PM Rohit Sant created Move
DIV Dec 10, 2013, 10:24 PM Rohit Sant edited Data Transfer
IDIV Dec 10, 2013, 10:23 PM Rohit Sant created Data Transfer
Dec 10, 2013, 10:22 PM Rohit Sant deleted Data Transfer Instructions
IMUL
Dec 10, 2013, 10:21 PM Rohit Sant created Data Transfer Instructions
INC
Dec 10, 2013, 10:20 PM Rohit Sant edited Home
MUL
NEG
older | newer
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

Home
Arithmetic
Page not found
Instructions
AAA
AAD
AAM
AAS
ADC
ADD
CMP
DAA
DAS
DEC
DIV
IDIV
IMUL
INC
MUL
NEG
SBB
SUB
XADD
Bit Manipulation
Instructions
BSWAP
Logical AND
Logical NOT
Logical OR
Logical XOR
RCL
RCR
ROL
ROR
SAR
SHL/SAL
SHR
https://sites.google.com/...roprocessorsbits/system/errors/NodeNotFound?suri=wuid:gx:5a35d5d6f746ce51[3/9/2019 9:52:01 PM]

SHRD/SHLD
Data Transfer
CMPXCHG
LAHF
LAR
LDS/LES
LEA
MOV
MOVS
MOVSX [386+]
MOVZX
SAHF
XCHG
XLAT(B)
Miscellaneous
BT
CBW
CDQ
CWD
CWDE
Processor
Control
Instructions
CLC
CLD
CLI
CMC
ESC
LOCK
NOP
STC
STD
STI
WAIT
Program
Execution
Transfer
Instructions
CALL

ENTER
INT
INTO
IRET
JA/JNBE
JAE/JNB
JB/JNAE/JC
JBE/JNA
JC
JCXZ
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JMP
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
LEAVE
LOOP
LOOPE/LOO…
LOOPNE/LO…
TEST
Stack
Instructions
POP
POPA/POPAD
POPF/POPFD
PUSH
PUSHA/PUS…
PUSHF/PUS…
RET
String
Instructions

CMPS/CMP…
INS/INSB/IN…
LODS/LODS…
MOVS/MOV…
OUTS/OUTS…
REP
REPE/REPN…
SCAS/SCAS…
STOS/STOS…
Sitemap

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with the sum stored in the same memory location.

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ADD BX,[SI+2];The word contents of the data segment memory

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SUB accum,immed 4 3 2 1 2-3

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