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A high precision method for measuring very small capacitance changes

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REVIEW OF SCIENTIFIC INSTRUMENTS VOLUME 70, NUMBER 8 AUGUST 1999

A high precision method for measuring very small capacitance changes

Ashkan Ashrafi and Hossein Golnabi
Institute of Water and Energy, Sharif University of Technology, 8639 Tehran, Iran
共Received 26 January 1999; accepted for publication 5 May 1999兲
A novel method for measuring very small capacitance changes based on capacitance-to-phase angle
conversion is introduced in this article. This new method is the improved or linearized version of the
nonlinear capacitance-to-phase angle conversion method. The main features of this scheme are the
very good linearity, extremely high stray immunity and a very high resolution. The experimental
results of the prototype version of this scheme have also been reported. By using this prototype and
a simple capacitive transducer, a minimum detectable distance of about 16 nm can be achieved. This
means that a capacitance change of about 0.7 fF (0.7⫻10⫺15 F) in a capacitance of 22 pF can be
resolved, so the minimum resolvable relative capacitance is about 32 ppm. By the theory it can be
seen that the minimum resolvable relative capacitance of 2 ppm could be achieved by this method.
© 1999 American Institute of Physics. 关S0034-6748共99兲03808-3兴

I. INTRODUCTION 共2兲 The input impedance of the charge amplifier used in

During the past years capacitive transducers have found
many applications. For measuring a very small capacitance
change there is a demand for a reliable high precision read-
out circuit. In principle, measuring small capacitance change
is not a new problem. Several attempts have been made in
order to achieve high resolution measurement. These at-
tempts are generally based on: the ac bridge method,1
capacitance-to-frequency conversion,1,2 and charge and dis-
charge methods.3,4 Also, recently the new methods based on
the switched-capacitor technique5,6 and capacitance-to-phase
angle conversion7 have been reported.
In this article a new method based on a linear
capacitance-to-phase angle conversion is introduced. The
main idea has been described previously,7 but the technique
that has been developed has several limitations and disad-
vantages. At first, we make some comments on these disad-
vantages and then describe the modifications that have led to
the new method. By this method very small capacitance
changes can be measured with the extremely high immunity
to grounded stray capacitances. In the following sections,
first the theoretical description of the proposed method is
presented. Then, the experimental results of a prototype ver-
sion are given in order to demonstrate the practical imple-
mentation of the new method. Ultimately, we discuss the
practical limitations that can somehow restrict the perfor-
mance of the readout circuit.
II. THEORETICAL ANALYSIS
A. Comments on the previous scheme
Figure 1 shows the scheme offered in the previous
work.7 This scheme has three major drawbacks, which are
described as follows:
共1兲 The relationship between the output phase and the
input capacitance changes is nonlinear. This relationship is in
the form of tan⫺1 as given in Ref. 7.
Ref. 7 is not low enough for high stray-immune measure-
ments. By assuming R f C f ␻ Ⰷ1 and ␻ Ⰷ ␣ the input imped-
ance of the charge amplifier shown in Fig. 1 can be written
as
1 1 1
Z in⫽ ⫽ ⬇ , 共1兲
A 共 ␻ 兲 •C f S G GC f
•C f S
S⫹ ␣
where ␣ is the first pole of the op-amp, G is the gain-
bandwidth product of the op-amp, and R f and C f are the
feedback resistor and capacitor, respectively. In order to de-
crease Z in , according to Eq. 共1兲 we need to increase the
product value of GC f , which can be done by increasing
either G or C f . But any increase in the value of C f causes a
decrease in the output signal level. On the other hand to
increase G we are forced to use a high frequency op-amp.
共3兲 The reported charge amplifier, as it is shown in Fig.
1, produces a constant phase shift in the output signal that
causes an extra nonlinear relation between the generated out-
put phase angle tangent and the input capacitance changes.
This phase shift depends on the frequency characteristic of
the op-amp and its value only can be reduced by using a high
frequency op-amp.
B. The new scheme
For overcoming the second and the third problems of the
pervious scheme, a simple parallel R – C circuit in front of a
buffer amplifier is suggested 关Fig. 2共a兲兴. The buffer amplifier
must produce no phase shift.8 In order to achieve such a
characteristic the active feedback scheme shown in Fig. 2共b兲
is used to design a buffer amplifier.9 Calculations show that
if the two op-amps used for constructing the buffer amplifier
are closely matched, the resulting phase shift could be writ-
ten as9
⌬ ␪ ⫽⫺ 冉冊␻
G
3
, 共2兲

0034-6748/99/70(8)/3483/5/$15.00 3483 © 1999 American Institute of Physics

3484 Rev. Sci. Instrum., Vol. 70, No. 8, August 1999 A. Ashrafi and H. Golnabi

FIG. 1. The schematic diagram of a capacitance-to-phase angle converter

reported in Ref. 7.

where by choosing low frequency signal, the disturbing

phase shift could be considerably decreased.
By assuming ␻ R T C T Ⰷ1, according to Fig. 2共a兲, we can
write
FIG. 3. The block diagram of the phase-sensitive detectors and monitoring
C 0B
V 0⫽ •sin共 ␻ t⫹ ␲ ⫺ ␺ 兲 circuit.
C T ⫹C 0 ⫹C X
C XA tude of the output signal. Therefore, we can argue that this
⫹ •sin共 ␻ t 兲 , 共3兲
C T ⫹C 0 ⫹C X scheme has an extreme stray immunity from side 2 of the
CX .
where C 0 is the reference capacitor, C X is the measured ca-
For producing two input signals, A sin(␻t) and B sin(␻t
pacitor, C T is the voltage dividing capacitor, and A,B are the
⫹␲⫺␺), the circuit which is shown in Fig. 2共c兲 is used. In
amplitudes of the two sinusoidal signals. By using the gen-
this circuit, first a sinusoidal signal is produced by an oscil-
eral formula for the summation of two sinusoidal functions,
lator. This sinusoidal signal is used for generating two bal-
Eq. 共3兲 can be simplified as
anced signals with 180° phase difference. This is accom-
C 0 B•sin ␺ plished by employing two matched op-amps.10 Then the
V 0⫽ •sin共 ␻ t⫹ ␸ 兲 共4兲
共 C T ⫹C 0 ⫹C X 兲 •sin ␸ phase of one of the signals is shifted by R 1 and C 1 by the
amount of ␺ 关 ␺ ⫽tan⫺1(R1C1␻)兴. At the end, we get two sig-
and nals defined as A sin(␻t) and B sin(␻t⫹ ␲ ⫺ ␺ ), where A and
C XA B are the signal’s amplitudes.
cot共 ␸ 兲 ⫽ ⫺cot共 ␺ 兲 . 共5兲 In spite of the mentioned advantages, the nonlinear be-
C 0 B•sin共 ␺ 兲
havior is still present in the new scheme. This problem can
Figure 2共a兲 shows the possible stray capacitance, C S2 , be overcome by using a conventional quadrature phase sen-
appearing between plate 2 of the measurand capacitor and sitive detector 共PSD兲 that provides the cotangent of the out-
ground that is added to C T . On the other hand, it is apparent put phase. By this configuration one can construct a linear
from Eqs. 共4兲 and 共5兲 that the value of C T has no effect on relationship between the input capacitance and the output of
the phase of the output signal and it only changes the ampli- the PSD. The overall block diagram of this design is shown
in Fig. 3. By using switching multipliers11,12 the two dc out-
puts become
2KC 0 B•sin共 ␺ 兲
V C⫽ •cot共 ␸ 兲 共6兲
␲CS
and
2KC 0 B•sin共 ␺ 兲
V S⫽ , 共7兲
␲CS
where C S is defined as a total capacitance (C S ⫽C T ⫹C 0
⫹C X ), and K is the gain of arbitrary ac amplifier which may
be used for increasing the amplitude of V O 共the output of the
capacitance-to-phase angle converter兲. The two reference
signals for the quadrature switching PSD have been provided
by converting sin(␻t) and cos(␻t) to square waves. This con-
version is accomplished by using two voltage comparators as
shown in Fig. 3. By dividing Eq. 共6兲 by Eq. 共7兲 it is evident
FIG. 2. The proposed scheme for the capacitance-to-phase angle conver- that
sion. 共a兲 The modified capacitance-to-phase angle converter (C S1 and C S2
show the possible stray capacitances兲. 共b兲 The buffer amplifier. 共c兲 The VC
circuit design for producing the two signals with an appropriate phase dif- cot共 ␸ 兲 ⫽ . 共8兲
ference ( ␲ ⫺ ␺ ). VS
Rev. Sci. Instrum., Vol. 70, No. 8, August 1999 Small capacitance changes 3485

For dividing V C by V S , first, two analog-to-digital con- C. Calculation of resolution

verters 共ADCs兲 convert these signals to digital numbers and
then they are conveyed to a microcomputer, where the divi-
sion process is performed.
The reference voltages used for the ADCs are V RC and
V RS corresponding to V C and V S , respectively. If the ADCs
have m-bit outputs, it can be written
VC
D C ⫽2 m , 共9兲
V RC
VS
D S ⫽2 m , 共10兲
V RS
where D C and D S are the digital outputs of the converters
corresponding to V C and V S , respectively. From these as-
sumptions and using Eqs. 共5兲, 共8兲, 共9兲, and 共10兲 a linear re-
Because of the normalized output, it is more appropriate
to develop the resolving formula for the relative capacitance
measurements. The resolvable relative capacitance could be
then derived from Eq. 共16兲. As it can be inferred from Eq.
共16兲, variations of the parameters ␺, n, and the resolution of
the ADC’s outputs (D C /D S ) could affect the overall resolv-
able relative capacitance. The ␺ variations could be mini-
mized by using a stable phase shifter, and its variations can
be corrected by recording ␺ for each measuring step. By
choosing a single temperature compensated voltage reference
for both DACs, the variations of V RS and V RC due to the
temperature changes is extremely low and can be ignored.
By considering the mentioned descriptions the resolvable
relative capacitance can be derived by differentiating Eq.
共16兲, which results in:

冉 冊
lationship can be derived between the measurand capacitor
tan共 ␺ 兲 DC
C X and D C /D S . Equation 共5兲 then becomes ⌬D OUT⫽ •⌬ . 共17兲
n DS
D C V RC C XA
cot共 ␸ 兲 ⫽ • ⫽ ⫺cot共 ␺ 兲 . 共11兲 The only parameter that remains effective on the resolvable
D S V RS C 0 B•sin共 ␺ 兲
relative capacitance is the resolution of the ADCs. If each
It can be seen from Eq. 共11兲 that A,B, ␺ and C 0 are the only ADC generates an error of ⫾1 least significant bit, then
parameters contributing to the output results. ⌬D C ⫽⌬D S ⫽1, and for the worst case D C ⫽D S we have
Let C X0 be a reference value for C X and consider the
measurand of interest to be the deviation from this reference
value, named C X1 , so that
⌬ 冉 冊
DC
DS
⫽
2
DS
. 共18兲

For achieving the highest possible resolution, D S must be as

C X ⫽C X0 ⫹C X1 . 共12兲
large as possible. Therefore, our program is arranged in such
By substituting Eq. 共12兲 into Eq. 共11兲, the linear relationship a way that D S becomes the maximum achievable value by
converted to controlling V RS via digital to-analog converter 共DAC兲1 共Fig.
3兲, such as an autoranged ADC. For the ADC’s with the m
DC 1 bit resolution, the maximum value of D S equal to 2 m then
cot共 ␸ 兲 ⫽ •
DS n can be written as

⫽
C X0 •A
C 0 B•sin共 ␺ 兲
⫺cot共 ␺ 兲 ⫹
C X1 A
C 0 B•sin共 ␺ 兲
, 共13兲 ⌬ 冉 冊
DC
DS 2
1
⫽ m⫺1 . 共19兲

where n⫽V RS /V RC . By adjusting A, so that it satisfies the If we consider 12-bit ADCs, then the achievable resolution
following relationship: of dividing V C by V S is 1000 ppm 共full scale D C /D S ⫽1)
according to Eq. 共19兲. By substituting Eq. 共19兲 into Eq. 共17兲
C X0 A⫽C 0 B•cos共 ␺ 兲 , 共14兲 we will have
Eq. 共13兲 can be written as ⌬C X1 tan共 ␺ 兲
⫽⌬D OUT⫽ . 共20兲
D C 1 C X1 C X0 n•2 m⫺1
• ⫽ •cot共 ␺ 兲 . 共15兲
D S n C X0 Although the maximum achievable resolution from ADCs in
the dividing process is 1000 ppm, according to Eq. 共20兲 the
By defining C X1 /C X0 共the normalized capacitance ratio兲 as
overall resolution of the system can be further improved by
the output (D OUT), it can be written
considering ␺ and n. On the other hand, increasing the reso-
C X1 tan共 ␺ 兲 D C lution will decrease the dynamic range. In order to achieve
D OUT⫽ ⫽ • . 共16兲 the optimum performance one has to compromise between
C X0 n DS
the resolvable relative capacitance and the dynamic range.
Equation 共16兲 is the main relationship between the normal-
ized capacitance ratio and the output number D OUT , which is
computed by a microcomputer via a proper program. Under
D. Noise analysis
the condition given in Eq. 共14兲 the effects of A, B, and C 0
can be eliminated. Equation 共14兲 also establishes the calibra- The main internal noise source is the buffer amplifier.
tion condition for the measurements. When Eq. 共14兲 is satis- Considering the input referred noise voltages and currents of
fied, the related output D OUT for C X1 ⫽0 will be zero, so this the two matched op-amps E n and I n , the rms value of the
relation is referred to as the ‘‘zero adjustment condition.’’ output noise can be calculated as
3486 Rev. Sci. Instrum., Vol. 70, No. 8, August 1999
冋
E 20 ⫽ 2E 20 ⫹
4kT
␻ 2 C 2S R T
⫹
I 2n R T2
共 R T C S ␻ ⫹1 兲 2 册 •⌬ f .
By using LF353, according to its data sheet the noise voltage
and current of this op-amp is 25 nV/冑Hz and 0.01 pA/冑Hz,
respectively. By choosing the values: R T ⫽22 M⍀, C S
⫽25 pF, ␻ ⫽2 ␲ 10 000 rad/s, at room temperature and at the
bandwidth of 1.5 Hz 共corresponding to the bandwidth of the
low pass filters used in synchronous detector兲 the rms value
of the output noise will be 48 nV.
III. EXPERIMENTAL RESULTS
A prototype version of the described scheme has been
constructed by using commercial components such as the
LF353 as op-amp, ICL7109 as ADCs, and the 4053 analog
switch as switching multipliers. The operating frequency was
chosen at 10 kHz.
For testing the prototype circuit, we constructed a simple
capacitive transducer with a Kelvin guard ring.13 It is de-
signed so that the distance between its plates 共X兲 is much
smaller than the radius of the plates. In this configuration the
well known relationship of the parallel plates capacitor is
valid:
Ae
C⫽ ⑀ • , 共22兲
X The nonlinearity of the curve shown in Fig. 4 is less than
where A e is the effective area of the two plates, and ⑀ is the
permeability of the dielectric material between the two plates
共air兲.
To control the distance X precisely and to scan this trans-
ducer smoothly a high resolution stepping motor 共800 steps
per revolution兲 was coupled to a microscrew that was driving
one of the capacitor’s plates. The microscrew has a pitch of
2 turns/mm, which results a displacement of 0.625 ␮m for a
single step of the motor.
In order to obtain a linear relationship between D OUT
and X, we need to exchange the position of C X and C 0 in the
circuit depicted in Fig. 2共a兲. It is assumed that X⫽X 0 ⫹X 1 ,
where X 0 is the distance in which zero adjustment has been
made and X 1 is the deviation from X 0 . Therefore Eq. 共16兲
becomes
X1
D OUT⫽ . 共23兲
X0
As mentioned, Eq. 共23兲 represents the calibration curve
of the transducer that can be obtained experimentally by
changing X 1 from the initial value of X 0 and recording
D OUT . The result of such measurements has been shown in
Fig. 4. This curve has been obtained by setting X 0
⫽0.5 mm. The slope of this line has been calculated by the
least square method which is 2.06⫻10⫺3 / ␮ m. For a com-
parison the slope is also obtained by the theory (1/X 0 ) that is
2⫻10⫺3 / ␮ m. As can be seen there is a very good agreement
between the theory and the experiment. However, a little
difference between the theoretical and experimental results
may be due to the existence of the stray capacitances be-
tween the two plates of the capacitive sensor. This effect is
A. Ashrafi and H. Golnabi
共21兲
FIG. 4. 共Top兲 Shows the variation of the normalized capacitance of the
constructed transducer as a function of positive displacements between its
plates (X 1 ). 共Bottom兲 Shows the percentage of nonlinearity of the related
displacements.
probably caused by the type of connections arranged for the
junctions of the plates of the capacitive sensor and the fring-
ing effect near the edges of the sensor.
In this computations we set: ␺ ⫽3.7°, n⫽1 and m⫽12
共number of bits of the ADCs兲. By substituting these values
into Eq. 共20兲 the minimum resolvable relative capacitance of
32 ppm is calculated. According to the resolvable relative
capacitance of about 32 ppm, the minimum detectable dis-
placement is about 16 nm.
0.5%, which mainly depends on the fluctuations of the me-
chanical scanning system.
The minimum measurable displacement in the capacitive
sensor is the displacement which results from a voltage
change equal to the rms noise voltage in the bandwidth of the
electronic circuit. By choosing B⫽10 V, C 0 ⫽12 pF, C S
⫽25 pF and ␺ ⫽3.7° according to Eq. 共6兲, 共16兲 and 共21兲,
⌬ cotg共␸兲 will be 48 nV/0.2 V⫽2.4⫻10⫺7 . Considering Eqs.
共16兲 and 共23兲 it can be seen that ⌬X 1 /X 1 ⫽tan(␺)
⫻⌬ cotg( ␸ )⫽1.5⫻10⫺8 or the minimum measurable dis-
placement is 7.7⫻10⫺12 m. This value is much less than the
minimum resolvable relative displacement achievable by the
systematic error of the system. The lower limit of the mini-
mum resolvable relative capacitance is achieved by choosing
n⫽15 so that it will be 2 ppm. The low noise performance of
the readout circuit permits high precision in such measure-
ments.
IV. DISCUSSION
In Sec. II the systematic error for the readout circuit has
been described. Along with systematic error, there are some
practical limitations that may affect the performance of the
readout system. However, the overall performance of the
transducer is controlled in part by the measuring circuit and
by the sensor as well. Therefore, some limitations are due to
sensor characteristics and some are due to the readout circuit.
In our case, the resolution and the overall performance of the
transducer were mainly limited by the mechanical drive sys-
Rev. Sci. Instrum., Vol. 70, No. 8, August 1999
tem of the capacitive sensor. Practically, to meet and mea-
sure such a high resolutions one has to take advantage of the
small value of capacitance changes in the integrated circuit
sensors. The resolution of the readout circuit was estimated
to be about 0.044 fF 共2 ppm兲, however for the present sys-
tem, our resolution is limited to only 0.7 fF 共32 ppm兲. The
practical limitations of the reported readout system and the
ways to minimize those can be classified as follows:
共1兲 Amplitude variations of the main oscillator cause the
same variations on the two output voltages of the PSDs (V C
and V S ). Since these two voltages are divided by each other,
the amplitude variations of he main oscillator do not affect
the output.
共2兲 Phase jitters of the main oscillator degrade the sta-
bility of the output. This effect can be decreased primarily by
using a very stable oscillator. Besides, output oversampling
leads to a very stable output.
共3兲 Since the measurand quantity converts to the phase
angle difference between the two signals, the effects of am-
plitude noise and disturbances will be very small on the out-
put signal of the capacitance-to-phase angle converter. Along
with this intrinsic behavior, the phase-sensitive detectors
eliminate the noise significantly. This elimination is due to
PSD’s narrow pass bands around the main 共fundamental兲 fre-
quency and its odd harmonics.12 The nonfundamental pass
bands may cause an error due to the odd harmonics of the
input sinewave but, by designing a low distortion oscillator
this effect can be minimized.
共4兲 The only stage which can increase the output noise
and unstability is ADC, since it has a dc gain. This effect
causes a limitation on n. This limitation strongly depends on
the ADC performance and the PCB design.14,15 For further
decrease of the output noise, special program is prepared to
oversample the outputs of the ADCs and averaging them.
This method can improve the signal-to-noise ratio but, slow
down the speed of the measurements. Noise reduction ob-
tained by this method is proportional to the square root of the
number of oversamplings. For achieving a good performance
one has to compromise between the output noise reduction
and the response time of the scheme.
共5兲 The dielectric absorption of the capacitor may cause
a phase error.16 This phenomena causes a nonlinear relation
between the output and the capacitance changes. For mini-
mizing this effect capacitances with low dielectric absorption
must be used as C T and C 0 . The sensing capacitor must have
a low dielectric absorption as well; therefore using the air
dielectric for the sensor is the best choice.
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Small capacitance changes 3487
共6兲 In spite of the good stray immunity of the readout
circuit, the stray capacities between the plates of the sensor
and the ground may affect the performance. For connecting
the transducer to the readout circuit, two coaxial cables have
been used so that their outer conductors have been driven, at
low impedance, with a potential essentially equal to the volt-
age of the inner conductor 共active guarding兲. This arrange-
ment significantly reduces the effects of grounded stray ca-
pacities. Stray capacities between the two plates of the sensor
also affect the measurements, but there is no easy method to
reduce its effects on the readout circuit except by reducing its
value. In order to reduce its value, proper connections must
be arranged between the plates of the sensor and the coaxial
cables, and such proper connections must be made between
the coaxial cables and the input of the readout circuit as well.
On the whole this source of noise is the main source of
instability of the output readout that degrades the resolution.
Considering the sources of noise and disturbances and
taking all the necessary precautions, the output fluctuations
have been reduced to ⫾5 ppm which is less than the effect of
the minimum resolvable relative capacitance 共32 ppm兲.
These fluctuations manifest themselves as the instability of
the output.
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