DEMULTIPLEXER 1

DEMULTIPLEXER
MINI PROJECT
Submitted to
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
in partial fulfillment of requirements for the award of the Degree of
BACHELOR OF TECHNOLOGY
In
ELECTRONICS AND COMMUNICATION ENGINEERING
submitted by

RACHAGORLA REDDAIAH
20001A0457

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

JNTUA COLLEGE OF ENGINEERING, ANANTHAPURAMU
ANDHRA PRADESH-INDIA
2021- 2022
 DEMULTIPLEXER 2

JNTU COLLEGE OF ENGINEERING, ANANTHAPURAMU

ANDHRA PRADESH-INDIA
2021- 2022

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE
This is to certify that the project report
DEMULTIPLEXER
a record of mini-project work done and
submitted by

RACHAGORLA REDDAIAH
20001A0457

for the partial fulfillment of the requirements for the award of

BACHELOR OF TECHNOLOGY
In
ELECTRONICS AND COMMUNICATION ENGINEERING
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

GUIDE HEAD OF THE DEPARTMENT

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TABLE OF CONTENTS
Chapter Page
Description
No. No.

1 INTRODUCTION
1.1 An introduction to demultiplexer 6
1.2 What is demultiplexer? 6-7
1.3 Types of demultiplexer 7
2 PROJECT DETAILS
2.1 1-to-2 Demultiplexer 8-10
2.2 1-to-4 Demultiplexer 10-13
2.3 1-to-8 Demultiplexer 13-16
2.4 1-to-16 Demultiplexer 16-19
2.5 Which IC works as an Demultiplexer? 20
2.6 Behavioral code for 1-to-4 Demultiplexer 20-21
3 IMPLEMENTATION
3.1 Software Implementation (code) 22-31
4 ADVANTAGES & DISADVANTAGES 32
5 APPLICATIONS 33
6 CONCLUSION 34
REFERENCES 34

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LIST OF FIGURES

FIGURE DESCRIPTION PAGE

NO. NO.

1.2.1 Demultiplexer or Demux 7

2.1.1 1 to 2 Demux block diagram 8

2.1.2 1 to 2 Demux logic diagram 10

2.2.1 1 to 4 Demux block diagram 10

2.2.2 1 to 4 Demux logic diagram 12

2.3.1 1 to 8 Demux block diagram 13

2.3.2 1 to 8 Demux logic diagram 15

2.4.1 1 to 16 Demux block diagram 16

2.4.2 1 to 16 Demux logic diagram 19

3.1.1 Hardware schematic of demultiplexer 20

3.1.2 Output simulation waveforms of demultiplexer 31

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ACKNOWLEDGEMENT

It is a great pleasure in expressing deep sense of gratitude and veneration to our

guide Smt. K.MAMATHA in department of Electrical and Electronics
Engineering We are greatly indebted to Dr.D.VISHNU VARDHAN Head of
Department for his valuable guidance. His advice, assistance and patience are
greatly appreciated .Electronics and Communication Engineering Department
for providing outstanding facilities for completion of project. We also express our
sincere thanks to principal of JNTUA College of engineering Ananthapur
Dr.P.SUJATHA, for her encouragement and for providing the required
computational facilities throughout the project. We would like to thank all the
teaching and non-teaching staff of Electronics and Communication Engineering
department for their excellent monitoring and their suggestions that helped in
successful completion of our socially relevant project. Above all, we thank our
parents and almighty, whose divine grace provided us the opportunity to do Our
project work according to our wish.

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CHAPTER 1

INTRODUCTION

1.1 An introduction to demultiplexer

A Demultiplexer is also called Demux or data distributor and its operation is quite opposite
to a multiplexer because it is an inverse to the multiplexer. The multiplexer is a many-to-
one circuit whereas the Demultiplexer is a one-to-many circuit. By using Demultiplexer,
the transmission of data can be done through one single input to a number of output data
lines.

Generally, Demultiplexers are used in decoder circuits and Boolean function generators.
There are different I/O configurations De-multiplexers are available in the single ICs form.
In addition, there is a cascading facility for two or above two DEMUX circuits for
producing several output de-multiplexers. This article discusses an overview of a
demultiplexer and its working.

1.2 What is a Demultiplexer?

A Demultiplexer (Demux) is a combinational logic circuit that includes single input and an
‘n’ number of outputs. The data which is obtained by a single input line can be transmitted
to the ‘n’ number of output lines. So the function of a demultiplexer is quite opposite to a
multiplexer. Multiplexers are called Data Selectors whereas Demultiplexers are Data
Distributors because they transmit similar information which is obtained at the input to
various outputs.

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Fig1.2.1 :Demultiplexer or Demux

A Demux is a 1-to-n device, whereas the Mux is an n-to-1 device. The demultiplexer block
diagram is shown below which includes a single input line, ’m’ select lines, and ‘n’ output
lines. Here ‘m’ select lines are mainly used to generate 2m output lines. For instance, a 1-
4 Demux needs 2 select lines for controlling the 4 o/p lines. In order to choose a particular
output, a set of select lines need to use for controlling the specific output line which is
connected to the input.

1.3 Types of Demultiplexer

There are different types of demultiplexers available depending on the different output
configurations like 1 to 2, 1 to 4, 1 to 8 & 1 to 16. These Demultiplexers are available in
various IC packages. Some of them are; 74139 IC is a dual 1 to 4 Demux, 74138 IC is a 1
to 8 Demux, 74237 IC is a 1 to 8 Demux including address lines, 74154 IC is a 1 to 16
Demux and 74159 IC is a 1 to 16 open collector Demux. So, the Demux ICs are also known
as Decoder ICs.

• 1-to-2 Demultiplexer
• 1-to-4 Demultiplexer
• 1 to 8 Demultiplexer
• 1-to-16 Demultiplexer

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CHAPTER-2
PROJECT DETAILS

2.1 1-to-2 Demultiplexer

A 1-to-2 demultiplexer (Demux) includes single input & two output lines with 1 select line.
The select line signal assists to control the input to one of the 2 outputs. The block diagram
of a 1-to-2 demultiplexer including an enable input is shown below.

Fig 2.1.1 :1 to 2 Demultiplexer Block Diagram

In the above diagram, the input to output lines can be connected through two methods, so
a single select signal is simply sufficient to perform the operation of demultiplexing.

Once the select input is 0 or LOW, then it will be supplied to ‘X0’ & if it is 1 is HIGH or
1, then the input will be supplied to X1. The 1-to-2 demultiplexer truth table is shown
below, where the input is connected to X0 & X1 based on the select input value ‘S’.

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For the outputs X0, X1, select input ‘S’, data input ‘D’, the Boolean expression is;

If S D = 0 1, then the expression for X0 = S’ D

If S D = 1 1, then the expression for X1 = S D

From the above 1-2 Demux truth table, the Boolean algebra Expressions can be derived but
its logic diagram can be designed through 2-AND gates & 1- NOT gates. Once the select
line is zero, then the primary AND gate is enabled whereas the next AND gate are disabled.

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Fig 2.1.2 :1-to-2 Demux Logic Diagram

After that, the input data can be supplied toward the o/p line ‘X0’. Likewise, once the select
line is 1, then the secondary AND gate will be enabled while the primary AND gate is
disabled, so data can be supplied toward the output line ‘X1’.

2.2 1-to-4 Demultiplexer

A 1-4 Demux includes a single input like D, 2-selection lines like S1 & S0 & 4 outputs like
X0, X1, X2 & X3. The data at input transmits to any one of the outputs in a specified time
for a specific arrangement of select lines. The 1:4 Demux block diagram and its truth table
are shown below.

Fig 2.2.1 :1 to 4 Demultiplexer Block Diagram

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From the below truth table, we can conclude that once both the select inputs are 0 & 1, the
data input can be connected to output X0. Similarly, once selection lines S0 & S1 are 0 &
1, then data input can be connected to X1 output.

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Likewise, the remaining outputs will be connected toward the input for the other two select
lines combinations. So, the Boolean expression for the outputs can be derived by using the
above truth table.

• X0 = S1’ S0’ D

• X1 = S1’ S0 D

• X2 = S1 S0’ D

• X3 = S1 S0 D
In the above expression, the input data is ‘D’, output lines are X0, X1, X2 & X3 and select
lines are S0 & S1. By using the above Boolean expressions, the implementation of a 1-4 Demux
can be done with 4 AND gates & 2 NOT gates.

Fig 2.2.2:1 to 4 Demux Logic Diagram

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By using the above Boolean expressions, the implementation of a 1-4 Demux can be done
with 4 AND gates & 2 NOT gates. The two select lines like S0 & S1 will allow a specific
AND logic gate at a time. In addition, there is a Strobe input or an Enable pin which works
as a universal enable input which means when the enable bit is high then the outputs are
active. So based on the combination of the select inputs, input data can be transmitted using
the selected gate toward the associated output.

2.3 1 to 8 Demultiplexer
The 1-8 demultiplexer block diagram is shown below which includes one input ‘D’, 3-
select inputs like S0, S1 & S2 & 8 outputs like X0, X1, X2¸ X3, X4¸ X5¸ X6 & X7. This
type of Demux is also called 3-8 Demux because of the 3 select input lines & 8 output lines.

Fig 2.3.1 :1 to 8 Demultiplexer Block Diagram

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It transmits one input line toward one of the eight output lines based on the select inputs
combinations like input ‘D’ is connected to one of the outputs from X0 to X7 depending
on the S0, S1 & S2 select lines. The truth table of 1 to 8 Demux is shown below.

Based on the above-mentioned truth table, for all the outputs, the Boolean expression can
be written like the following

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• X0 = S2’ S1’ S0’ D

• X1 = S2’ S1’ S0 D

• X2 = S2’ S1 S0’ D

• X3 = S2’ S1 S0 D

• X4 = S2 S1’ S0’ D

• X5 = S2 S1’ S0 D

• X6 = S2 S1 S0’ D

• X7 = S2 S1 S0 D

From the above Boolean equations, a 1 to 8 demultiplexer logic diagram can be designed
through 8 four-input AND logic gates & 3 NOT logic gates as shown in the following logic
diagram.

Fig 2.3.2 :1-to-8 Demux Logic Diagram

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One AND gate can be activated through different select lines combinations in a specified
time so that input data will come out at the equivalent output.

2.4 1 to 16 Demultiplexer
The 1-16 demultiplexer block diagram is shown below which includes one data input bit
‘D’, four control bits S0 to S3 & 16 output bits from Xo to X15. This type of DEMUX is
used to transmit a single input line to one of the output lines from X0 to X15 based on the
four select lines.

Fig 2.4.1 :1 to 16 Demux Block Diagram

The truth table of 1 to 16 Demux is shown below.

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From the above tabular form, the Boolean expressions can be formed like the following.

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• X0= S0′.S1′.S2′.S3′ D

• X1= S0′.S1′.S2′.S3 D

• X2=.S0′.S1′.S2.S3′ D

• X3= S0′.S1′.S2.S3 D

• X4= S0′.S1.S2′.S3′ D

• X5= S0′.S1.S2′.S3 D

• X6= S0′.S1.S2.S3′ D

• X7= S0′.S1.S2.S3 D

• X8 = S0.S1′.S2′.S3′ D

• X9 = S0.S1′.S2′.S3

• X10 = S0.S1′.S2.S3′ D

• X11= S0.S1′.S2.S3 D

• X12 = S0.S1.S2′.S3′ D

• X13= S0.S1.S2′.S3 D

• X14= S0.S1.S2.S3′ D

• X15= S0.S1.S2′.S3 D

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From the above Boolean equations, a 1 to 16 demultiplexer logic diagram can be designed
through 16 AND logic gates & 4 NOT logic gates as shown in the following logic diagram.
Here, one AND logic gate can be enabled through various select lines combinations within
a particular time so that input data will appear at the output.

Fig 2.4.2 :1 to 16 Demultiplexer Logic Diagram

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2.5 Which IC Works as a Demultiplexer?

There are different Demultiplexer ICs available like
1-4 Demux is 74139 IC
1-to-8 demultiplexers are 74237 IC, 74138 IC
1-16 Demux is 74154 IC
4-16 line Decoder IC like 74159.

2.6 BEHAVIORAL VERILOG CODE FOR 1-TO-4 DEMULTIPLEXER

Here we are going to work with 1-to-4 demultiplexer. A 1-to-4 demultiplexer consists of
one input data line,four outputs, andtwo control lines to make selections.
The below diagram shows the circuit of the 1-to-4 demultiplexer. Here a1 and a0 are control
or select lines y0, y1, y2, y3 are outputs, and Din is the data line.

Fig 2.6.1 :logic diagram 1:4 demultiplexer

Now, let’s observe its truth table –

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Fig 2.6.2 :Truth table of demultiplexer

The values of a1a0 determine which of the outputs are set to the value of Din. When Din=0, all
the outputs are set to 0, including the one selected by the valuation of a1a0. When Din=1, the
valuation of a1a0 sets the appropriate output (anyone from y0, y1, y2, y3) to 1.

Now that we have thoroughly understood the concepts of the demultiplexer, let’s dive directly
into the Verilog code for the demultiplexer.

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CHAPTER-3
IMPLEMENTATION

3.1 SOFTWARE IMPLEMENTATION(CODE)

Different methods used in behavioral modeling of a demultiplexer

There are various styles of writing Verilog code in behavioral modeling for this circuit.

1. case statements
2. assignment statements
3. if-else statements
Here we will be elaborating on the first two. Along the way, we would also emphasize some
common design errors.

Verilog code for demultiplexer – Using case statements

The basic building block in Verilog HDL is a module, analogous to the ‘function’ in C. The
module declaration is made as follows:

module Demultiplexer_1_to_4_case (output reg [3:0] Y, input [1:0] A, input din);

For starters, module is a keyword. It is followed by an identifier. Identifier=name of the

module. After naming the module, in a pair of parentheses, we specify:

• the direction of a port as input, output or inout.

• Port size, and
• port name.
Taking into consideration the first line of the code, Demultiplexer_1_to_4_case is the identifier,
the input is called port direction. If a port has multiple bits, then it is known as a vector. Hence,
[1:0] states that the port named as A is a vector with MSB = 1 and LSB = 0.

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The reg data object holds its value from one procedural assignment statement to the next and
means it holds its value over simulation data cycles.

Another style of declaration in the port list is to declare the port size and port direction after
the module declaration.

module Demultiplexer_1_to_4_case (Y, A, din);

output reg [3:0] Y;
input [1:0] A;
input din;

[3:0] here signifies that the output is of 4 bits. Next up, since its behavioral modeling style,
here comes the always statement.
always @(Y, A) begin

Using the always statement, a procedural statement in Verilog, we will run the program
sequentially. (Y, A) is known as the sensitivity list or the trigger list. The sensitivity list includes
all input signals used by the always block. It controls when the statements in the always block
are to be evaluated. @ is a part of the syntax, used before the sensitivity list. In Verilog, begin
embarks and end concludes any block which contains more than one statement in it.

Note that the always statement always @(Y, A) could be written as always @ *. * would mean
that the code itself has to decide on the input signals of the sensitivity list.

Then inside always block we write,

case (A)

The case statement in Verilog is analogous to switch-case in C language. First, let us see the
general format to write a case statement in Verilog.

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case (<expression>)
case_item1 : <single statement>
case_item2 : <single statement>
case_item3 : begin
<multiple statements>
end
default : <statement>
endcase

If the expression corresponds to any of the case_item, then those design statements are
executed. Otherwise, the default case is executed. So, now we can write
case (A)
2'b00 : begin
Y[0] = din; Y[3:1] = 0;
end
2'b01 : begin
Y[1] = din; Y[0] = 0;
end
2'b10 : begin
Y[2] = din; Y[1:0] = 0;
end
2'b11 : begin
Y[3] = din; Y[2:0] = 0;
end
endcase

As we see here in the first case, 2'b00 represents the case when the input A is 2'b00. These
cases indicate that, according to the value of A, one of the four statements is selected. The
colon then marks the end of a case item and starts the action that must happen in that particular
case. The terms begin and end are part of the Verilog syntax if you are writing more than one
statement in that block. After this, those statements are mentioned, such as the output port Y[0]
should be attached to the din, Y[3:0] to 0, and so on, according to the truth table.

This modeling is based on the behavior of the circuit; hence it is called behavioral modeling.
Observe that we are not specifying the structure of the circuit, we are only creating the logic of
the circuit which can implement that hardware.

Here is the full code:

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module Demultiplexer_1_to_4_case (output reg [3:0] Y, input [1:0] A, input din);

always @(Y, A) begin
case (A)
2'b00 : begin Y[0] = din; Y[3:1] = 0; end
2'b01 : begin Y[1] = din; Y[0] = 0; end
2'b10 : begin Y[2] = din; Y[1:0] = 0; end
2'b11 : begin Y[3] = din; Y[2:0] = 0; end
endcase
end
endmodule

Verilog code for demultiplexer – Using assignment statement

First of all, we initiate by module and port declaration following the same syntax. We assign
identifier as Demultiplexer_1_to_4_assign, input as A, din and output as Y.

module Demultiplexer_1_to_4_assign(output [3:0] Y, input [1:0] A, input din);

We also set up the size and type of the port, which can only be either input, outputs, or inout.

Then we assign the output as the logical and operation of the select lines and data line. assign
is a keyword in which the expression or the signal on the right-hand side is evaluated and
assigned to the expression on the left side.

assign Y[0] = din & (~A[0]) & (~A[1]);

assign Y[1] = din & (~A[1]) & A[0];
assign Y[2] = din & A[1] & (~A[0]);
assign Y[3] = din & A[1] & A[0];

A[0] means that we are addressing the zeroth bit of the multi-bit bus, similar goes for Y[1], we
are accessing the first bit of Y vector. & stands for and operation, ~ is for not operation.

We give all the possible conditions as per our truth table of the demultiplexer.

This is also behavioral modeling as we are not identifying the circuitry, we are only assigning
the outputs to bitwise and of data and select lines.

endmodule

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This marks the end of the module. You may view the complete code here.

module Demultiplexer_1_to_4_assign(output [3:0] Y, input [1:0] A, input din);

assign Y[0] = din & (~A[0]) & (~A[1]);
assign Y[1] = din & (~A[1]) & A[0];
assign Y[2] = din & A[1] & (~A[0]);
assign Y[3] = din & A[1] & A[0];
endmodule

Hardware schematic for the demultiplexer

Here is the Hardware schematic which you may develop using Xilinx for demultiplexer.

Fig 3.1.1 : Hardware schematic of demutiplexer

Simulation log for the demultiplexer

Simulation log relating to our truth table.

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Fig 3.1.2 :output simulation waveforms of demultiplexer

We can observe that din is always 1; all combinations of A are made, the output can be verified
easily. For example- A[0] = 0, A[1] = 0, see that the waveform of Y[0] is high.

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CHAPTER-4
ADVANTAGES & DISADVANTAGES
Advantages & Disadvantages

The advantages of Demultiplexer include the following.

• The efficiency of the communication system can be improved with the help of the
Multiplexer & Demultiplexer combination
• A demultiplexer separates back the mutual signals into streams.
• Its function is quite opposite to multiplexer
• It can be used as a decoder in the security systems
• The combination of Mux & Demux is used for the transmission of Audio or Video
signals.

The disadvantages of demultiplexer include the following.

• Bandwidth wastage can be occured

• Delays can be occurred due to the synchronization of the signal

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CHAPTER-5
APPLICATIONS

Where is Demultiplexer Used?

The applications of Demultiplexer include the following.

• Demultiplexers are used in control systems, microprocessors to enable or select a

single signal from a number of signals
• Demux is used to choose several IO devices’ data routing.
• Selecting different banks for memory decoding.
• Implementation of a Boolean function
• To enable various functional units
• Used in synchronous systems for data transmission
• Data acquisition systems
• It enables several rows in memory chips based on the address
• Designing of combinational circuits
• Monitoring systems for security
• Automatic test equipment systems
• Demultiplexers are used within CLK data recovery solutions.
• Applicable in wavelength routers.
• Used in the communication system for transmission of data
• Used like a serial to parallel converter.
• These are used in the broadcasting of ATM packets
• The ALU output is stored within particular registers with the help of Demux

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CHAPTER-6
CONCLUSION
A DEMULTIPLEXER (DEMUX) basically reverses the multiplexing function.
It takes data from one line and distributes them to a given number of output
lines. For this reason, the demultiplexers is also known as a data distributor.A
multiplexer takes several inputs and transmits one of them to the output.A
demultiplexer(DEMUX) performs the reverse operation ; it takes a single input
and distributes it over several outputs.

REFERENCE:

1.Thomas L. Floyd, “Digital Fundamentals”, Pearson, 11th edition, 2015.

2Zainalabdien Navabi, “Verliog Digital System Design”,TMH, 2nd Edition.
3.John. F. Wakerly, “Digital design principles and practices”, Pearson
publishers, 3rd Edition.

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