HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY

FACULTY OF ELECTRICAL ELECTRONICS ENGINEERING

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FINAL REPORT

COURSE: Microprocessor(Lab)

CLASS: TT03

INSTRUCTOR: Dr. Nguyễn Trung Hiếu

HO CHI MINH CITY, March 2022

1 Overview
In this project, we have created a sine function calculator using VHDL. In order to use
this device, user will input a binary string of 17 bits to the x register. Then setting the
reset register to 0, and setting start register to 1. Once the start register is set to 1, the
calculator will run until it finished, at which point it sets the done register to 1, and
returns the result to y register.
We use sign-magnitude form to represent x and y. Each number is a 17 bits fixed
point binary number: [Sign (17)] [Integral (16:13)] [Fractional (12:0)]
The sine function is approximated by the Maclaurin-Taylor series, which to its fourth
term, is:
x3 x 5 x 7
( )
sin x =x− + −
3! 5! 7!
−π π
With x is the angle in radian, and x should stay between the range [ ;
2 2
] for better
accuracy.

Figure 1. System RTL

Figure 2. Control_state diagram

2 Design explanation
Generally, the sign bit of x will be assigned to the sign bit of y (sin(-x) = - sin(x)).
Other bits, which represent the magnitude, will go to the components, and return as
the magnitude of y. The aforementioned process takes begin when the reset is 0 and
start is 1. Only if reset is 1, or the calculation stage is done should the system state
comes back to “idle”. Moreover, start is 1 will set trigger to 1, so start state after that
is “don’t care”. The done register is set to 1 after the y register is set with the result.
To calculate, we break the formula down into subpart:
- Calculate x^3 by two consecutive “mult” components, taking x magnitude as
the first input value.
- Calculate x^5 by two consecutive “mult” components, taking x^3 as the first
input value.
- Calculate x^7 by two consecutive “mult” components, taking x^5 as the first
input value.
3
x
- Calculate by connecting div2 component to div 3 component.
3!
x5
- Calculate by connecting three consecutive div2 components to div 3
5!
component, then to div 5 component.
7
x
- Calculate by connecting four consecutive div2 components, to two
7!
consecutive div 3 components, then to div 5 component, then to div 7
component.
- Taking the sum of the three aforementioned steps, with the sign in the formula.
Component mult: takes two 16 bits number, and produce a 16 bits number. This is
done by temporary create 32 bits signals to sum up the result of each multiplication
step (including shifting bits). Then cut the most significant half (from 31st bit to 16th
bit), round the number based on the 15th bit, and return as the result in 16 bits format.
Component div2: right shifting the 16 bits input number, round the number base on
the original MSB.
Component div3, div5, div7: takes one 16 bits input number, and produce a 16bits
numbers. The division is performed as follow:
- Storing the temporary quotient (into tmp1). For div3 that is the three bits to be
subtracted by “11”. For div5 and div7, that is the four bits to be subtracted by
“101” and “111” respectively.
- Storing the number to be “borrow” (into tmp2). That is the remaining bits from
the input value (aside from the bit already assign to tmp1 at the beginning). The
tmp2 is used to store both the “borrow” and the result.
- Assign MSB of tmp2 to LSB of tmp1, left shifting tmp2 by one bit.
- If tmp1 >= denominator, tmp1 minus the denominator, set MSB of tmp2 to 1.
 - Repeat until “borrowed” all bit from original tmp2.
- If tmp1 >= denominator, the remainder is significant but not enough bit to store
the result so set the remainder flag to 1.
- Assemble the result and round.
Component control_state: has four states
- Idle: does nothing, waiting for start flag. Write your input value during this
state.
- Calculate: assigns value from x register to x_temp. Protect the input value from
changes (if any) during calculation.
- Read_output: assigns the output value to y register.
- Finish: turns on done flag.

3 Simulation

Case 1:
- Real value of x: 0.78
- Binary input: 0[0000.110001111010]
- Binary output: 0[0000.110001111001]
- Expected real value: 0.703
- Result real value: 0.779
Case 2:
- Real value of x: - 0.3
- Binary input: 1[0000.0100110011]
- Binary output: 1[000 0.0100110011]
- Expected real value: -0.296
- Result real value: -0.299