Professional Documents
Culture Documents
Physical Only Cells
Physical Only Cells
Tap cells:
A tap cell is a special nonlogic cell with a well tie, substrate tie, or both.
Tap cells are placed in the regular intervals in standard cell row and distance
between two tap cells given in the design rule manual.
These cells are typically used when most or all of the standard cells in the library
contain no substrate or well taps.
Generally, the design rules specify the maximum distance allowed between every
transistor in a standard cell and a well or substrate tap.
Before global placement (during the floorplanning stage), you can insert tap cells
in the block to form a two-dimensional array structure to ensure that all standard cells
placed subsequently comply with the maximum diffusion-to-tap distance limit.
command in ICC: create_tap_cells, specify the name of the library cell to use for
tap cell insertion (-lib_cell option) and the maximum distance, in microns, between tap
cells (-distance option)
icc2_shell>create_tap_cells -lib_cell myreflib/mytapcell -distance 30
fig1: TAP Cells and END CAP Cells
what is latch-up the problem: it is the condition when low impedance path gets formed
between VDD and GND terminal and there is direct current flow from VDD to GND
which might result in a complete failure of chip.while the formation of CMOS INVERTER
we saw the formation of PN junctions and because of these PN junctions there may be
formation of parasitics elements like diode and transistors.
Tie high cells: initially we directly connect VDD to the gate of transistor now we connect
the output of these cells to the gate of the transistor if any fluctuations in VDD due to
ESD then PMOS circuit pull it back to the stable state. PMOS should be ON always, the
input of the PMOS transistor is coming from the output of NMOS transistor and here in
NMOS gate and drain are shorted and this is the condition of saturation (NMOS) and
NMOS will act as pull-down and always give a low voltage at the gate of PMOS. now
PMOS will on and gives stable high output and this output is connected to the gate of
transistor
we know nwell is tap to VDD and P substrate is tap to VSS to prevent latchup problem.
now if there is a discontinuity in nwell it will not find well tap cells, so we have placed
well tap cells explicitly, therefore it will increase the area explicitly, hence we have filler
cells so no need to place well tap cells.
now if the voltage drop is greater than Noise margin(NM) of the inverter then it might
lead to improper functionality. Let's say NM is 0.4 now 1-0.4=0.6v (anything less than
0.6 will consider as 0 by this inverter)
now let's say voltage drop is 0.5 i.e 1-0.5=0.5v now this will consider as 0 therefore it
will lead to improper functionality. now we have seen voltage drop > NM so here de-cap
cells comes into picture so these cells are capacitor that holds the reservoir of charges
and these cells are placed near to the power-hungry cells, so whenever these cells
switch the de-cap cells starts discharging themselves and provided the required voltage
to the particular cells and keep the power supply constant to all the elements in the
design.
With increasing clock frequency and decreasing supply voltage as technology scales,
maintaining the quality of power supply becomes a critical issue. Typically, decoupling
capacitors (de-caps) are used to keep the power supply within a certain percentage
(e.g., 10%) of the nominal supply voltage. De-caps holds a reservoir of charge and are
placed close to the power pads and near any large drivers. When large drivers switch,
the de-caps provide instantaneous current to the drivers to reduce IR drop and Ldi/dt
effects, and hence keep the supply voltage relatively constant. A standard de-cap is
usually made from NMOS transistors in a CMOS process. At the 90nm technology node,
the oxide thickness of a transistor is reduced to roughly 2.0nm. The thin oxide causes
two new problems: possible electrostatic discharge (ESD) induced oxide breakdown and
gate tunneling leakage. Potential ESD oxide breakdown increases the likelihood that an
integrated circuit (IC) will be permanently damaged during an ESD event and hence
raises a reliability concern. Higher gate tunneling leakage increases the total static
power consumption of the chip. As technology scales further down, with a thinner
oxide, the result is an even higher ESD risk and more gate leakage. The standard de-cap
design experiences these two problems for more please visit the link below.
http://www.ece.ubc.ca/~xmeng/Files/01613147.pdf
Before placing the standard cells, we can add boundary cells to the block.
Boundary cells consist of end-cap cells, which are added to the ends of the cell rows and
around the boundaries of objects such as the core area, hard macros, blockages, and
voltage areas, and corner cells, which fill the empty space between horizontal and
vertical end-cap cells. (fig1)
End-cap cells are typically nonlogic cells such as a decoupling capacitor for the
power rail. Because the tool accepts any standard cell as an end-cap cell, ensure that
you specify suitable end-cap cells.
Boundary cells include both end-cap cells placed on the left, right, top, and
bottom boundaries, and inside and outside corner cells and.
To know the end of the row and at the edges, endcap cells are placed to avoid
the cell's damages at the end of the row to avoid the wrong laser wavelength for correct
manufacturing.
Boundary cells protect your design from external signals.
These cells ensure that gaps do not occur between the well and implant layer and
to prevent from the DRC violations.
When you insert these at the end of the placement row, these will make sure
that these cells properly integrated to the design and will have a clean unwell, other
DRC clean, hence next block will abut without any issues.