Microprocessor programming & Interfacing

CS-430

Course Teacher : Sumayya Zafar

Class : BE EE

Lecture 9
8088/8086 Microprocessor I/O Interfacing

Fall Semester 2020 1

 Recap
• 74138 Decoder As An Address Decoder
• Examples
• 74139 Decoder As An Address Decoder
• Examples

Fall Semester 2020 2

 Input/Output Interface
• Input/output devices or peripherals provides microcomputer the means of communication
with the outside world. This is accomplished using I/O ports.
• There are two basic techniques of interfacing I/O devices with 8088/8086 microprocessor.
• Memory Mapped I/O
• Isolated I/O
• These I/O methods differ in how I/O ports are mapped into 8088/8086 address space.

Fall Semester 2020 3

 Memory Mapped I/O
• I/O devices can be placed in the memory address space of the
microcomputer as well as in the independent address space. FFFFF
Memory
• A portion of real memory (1MB) is reserved for interfacing I/O
Address
devices.
Space
• Microprocessor looks at the I/O port as though it is a storage
location in memory. The instructions used for accessing memory are
employed for accessing input and output devices. 6FFFF
I/O Ports
• 20-bit address is decoded for accessing I/O devices. 60000
• 𝐼𝑂/𝑀ഥ signal will be at logic 0 when accessing I/O devices.
+ Memory transfer instruction can access the I/O device.
- Portion of memory system is used as the I/O map, reducing available
memory.
00000

Fall Semester 2020 4

 Memory Mapped I/O
Example:

MOV DX, 6000H

MOV DS , DX
MOV AL , [0100H] ; (AL)  (DS:[0100H]), PA = 6000*10H + 0100H = 60100H
MOV AX , [0150H] ; (AX)  (DS:[0150H]), PA = 60150H
MOV [2000H] , AL ; (DS:[2000H])  (AL) , PA = 62000H
MOV [2050H] , AX ; (DS:[2050H])  (AX) , PA = 62050H

Fall Semester 2020 5

 Isolated I/O
• The most common I/O transfer technique used in the Intel-based system is isolated I/O.
• In isolated I/O, addresses called ports, are separate from memory addresses.
• Because the ports are separate, the user can expand the memory to its full size without using
any of memory space for I/O devices.
• In isolated I/O is the data transferred between I/O and microprocessor must be accessed by the
I/O (IN, OUT) instructions.
• 16 bit address is decoded in case of variable address instructions.
• 8 bit address is decoded in case of fixed address instructions.
• 𝐼𝑂/𝑀ഥ is at logic 1 during execution of isolated I/O instructions.

Fall Semester 2020 6

 Isolated I/O

Example: (Variable address Instructions)

IN AL , DX ; DX is having 16-bit port address from where a byte is inputted into AL

IN AX , DX ; DX is having 16-bit port address from where 2 bytes are inputted into AX
OUT DX , AL ; DX is having 16-bit port address to which a byte is outputted from AL
OUT DX , AX ; DX is having 16-bit port address to which 2 bytes are outputted from AX

Fall Semester 2020 7

 Isolated I/O

Examples: (Fixed address Instructions)

IN AL , 60H ; Instruction is having 8-bit port address from where a byte is inputted into AL
IN AX , 60H ; Instruction is having 8-bit port address from where 2 bytes are inputted into AX
OUT 70H , AL ; Instruction is having 8-bit port address to which a byte is outputted from AL
OUT 70H , AX ; Instruction is having 8-bit port address to which 2 bytes are outputted from AX

Fall Semester 2020 8

 Input/Output Data Transfer
• Instructions that transfer data between an I/O device and the microprocessor’s accumulator (AL or AX)
are called IN and OUT.
• I/O transfers can be either byte wide or word wide.
• The I/O address is stored in register DX as a 16-bit address or in the byte (p8) immediately following the
opcode as an 8-bit address.
• The 8-bit form (p8) is called a fixed address because it is stored with the instruction.
• The 16-bit address is called a variable address because it is stored in a DX, and then used to address the
I/O device.

Fall Semester 2020 9

 Basic Input Interface
• The basic input device is a set of tri-state buffers.
• Tri-state buffers are used to construct the 8-bit input
port.
• External TTL data are connected to the inputs of the
buffers while buffer outputs connect to the data bus.
• The circuit allows the processor to read the contents of
the eight switches that connect to any 8-bit section of
the data bus when the select signal becomes a logic 0.
• When the IN instruction executes, contents of the
switches copy to the AL register.

Fall Semester 2020 10

 Basic Output Interface
• The basic output device is a set of data latches.
• Receives data from the processor and usually holds it
for some external device.
• Latches or flip-flops, like buffers in the input device, are
often built into the I/O device.
• The latch stores the number output by the
microprocessor from the data bus so that the LEDs can
be lit with any 8-bit binary number.
• Latches hold the data because when the processor
executes an OUT, data are only present on the data bus
for very short duration.
• When the output instruction is executed, data from the
AL register appear on the LEDs.

Fall Semester 2020 11

 Handshaking
• I/O devices are typically slower than the microprocessor.
• Handshaking is used to synchronize I/O with the microprocessor.
• A device indicates that it is ready for a command or data (through some I/O pin or port).
• The processor issues a command to the device, and the device indicates it is busy (not
ready).
• The I/O device finishes its task and indicates a ready condition, and the cycle continues.
• There are two basic mechanisms for the processor to service a device.
• Polling - Processor initiated. Device indicates it is ready by setting some status bit and the
processor periodically checks it.
• Interrupts - Device initiated. The act of setting a status bit causes an interrupt, and the
processor calls an ISR to service the device.

Fall Semester 2020 12

 Handshaking
• An example is a parallel printer that prints a few
hundred characters per second (CPS).The processor can
send data much faster.
• ASCII data are placed on D7 – D0 , and a pulse is then
applied to the STB connection.
• The strobe (STB) signal sends or clocks the data into the
printer so that they can be printed.
• As the printer receives data, it places logic 1 on the
BUSY pin, indicating it is printing data.
• The software polls or tests the BUSY pin to decide
whether the printer is busy.
• If the printer is busy, the processor waits.
• If not, the next ASCII character goes to the printer.
• This process of interrogating the printer, or any
asynchronous device like a printer, is called handshaking
or polling.
Fall Semester 2020 13
 I/O Port Addressing
• For memory-mapped I/O, decoding is identical to memory decoding.
• In isolated I/O, address bits from 𝐴15 − 𝐴0 are decoded and 𝐴19 − 𝐴16 are not
used .
• For fixed port addressing, upper half of address is kept 0.

Fall Semester 2020 14

 74138

𝑨𝟎
𝑨𝟕 𝑨𝟔 𝑨𝟓 𝑨𝟒 𝑨𝟑 𝑨𝟐 𝑨𝟏 𝑨𝟎 Address 𝑬𝟖
𝑨𝟏 𝑬𝟗
1 1 1 0 1 0 0 0 E8 𝑨𝟐
𝑬𝑨
1 1 1 0 1 0 0 1 E9 𝑬𝑩

1 1 1 0 1 0 1 0 EA 𝑨𝟒
𝑬𝑪
𝑨𝟓
1 1 1 0 1 0 1 1 EB 𝑨𝟔 𝑬𝑫
𝑨𝟕 𝑬𝑬
1 1 1 0 1 1 0 0 EC 𝑨𝟑
𝑬𝑭
1 1 1 0 1 1 0 1 ED
1 1 1 0 1 0 1 1 EE
1 1 1 0 1 1 1 1 EF

Fall Semester 2020 15

 Methods of Parallel Data Transfer
• Simple I/O – used for simple devices which are always present and ready. E.g. when a data is
read from a simple switch, such as thermostat, into microprocessor, all we have to do is
connect the switch to an I/O port line and read the port.
• Likewise, when we need to output data to simple display device, such as LED, all we have to
do is connect the input of the LED buffer on an output port pin and output the logical level
required to turn on the light.

• The timing waveform represents the situation where the crossed lines on the waveform
represent the time at which a new data byte becomes valid on the output lines of the port.
• The absence of other waveforms indicates that this output operation is not directly dependent
on any other signal.

Fall Semester 2020 16

 Methods of Parallel Data Transfer
• Simple Strobed I/O - In many applications, valid data is present on an external device only at
a certain time, so it must be read in at that time. E.g. the ASCII-encoded keyboard. When a
key is pressed, circuitry on the keyboard sends out the ASCII code for the pressed key on
eight parallel data lines, and then sends out a strobe signal on another line to indicate that
valid data is present on the eight data lines.

• The strobe signal can be either polled by the processor (programmed IO) or connected to
interrupt request line of the microprocessor (interrupt driven IO).
• The data transfer is time dependent.

Fall Semester 2020 17

 Methods of Parallel Data Transfer
• Single Handshake I/O - For low rates of data transfer, such as from a keyboard to a microprocessor, a simple strobe
transfer works well. However, for higher speed data transfer, this method does not work because there is no signal
which tells the sending device when it is safe to send the next data byte. The sending system might send data bytes
faster than the receiving system could read them.
• To prevent this problem, a handshake(two way signaling) data transfer scheme is used.

• It shows the timing waveform for a handshake data transfer from a peripheral device to a microprocessor.
• The peripheral outputs some parallel data and sends an 𝑆𝑇𝐵 signal to the microprocessor.
• The microprocessor detects the asserted 𝑆𝑇𝐵 signal on a polled or interrupts basis and reads in the bytes of data.
• Then, the microprocessor sends 𝐴𝐶𝐾 (acknowledge) signal to the peripheral to indicate that the data has been read
and that the peripheral can send next byte of data.
• E.g. Printer interface , where microprocessor sends a byte/block of data and asserts a 𝑆𝑇𝐵 signal. When the printer
receives that data it sends 𝐴𝐶𝐾 to processor.
Fall Semester 2020 18
 Methods of Parallel Data Transfer
• Double Handshake I/O - For data transfer where even more coordination is required between the
sending system and the receiving system, a double handshake is used.
• The sending (peripheral) device asserts its 𝑆𝑇𝐵 line low to ask the receiving device whether it is ready or
not for data reception.
• The receiving system raises its 𝐴𝐶𝐾 line high to indicate that it is ready.

• The peripheral device then sends the byte of data and raises its 𝑆𝑇𝐵 line high to assure that the valid
data is available for the receiving device (microprocessor).
• When microprocessor reads the data, it drops its 𝐴𝐶𝐾 line low to indicate that it has received the data
and requests the sending system to send next byte of data.
• E.g. Speech Synthesizer systems are connected in this manner.
Fall Semester 2020 19
 8255A Programmable Peripheral Interface
• 8255A is an LSI peripheral designed to permit easy implementation
of parallel I/O in the 8088 and 8086 microprocessor systems.
• 8255A manages most of the signaling automatically relieving
processor. Processor is only interrupted, proper timings of 𝑆𝑇𝐵 and
𝐴𝐶𝐾 are managed by 8255A PPI.

Fall Semester 2020 20

 8255A Programmable Peripheral Interface
• 8255A programmable peripheral interface (PPI) is a popular, low-
cost interface component found in many applications.
• The 8255 requires wait states if operated with a processor using
higher than an 8 MHz clock.
• 8255 is used for interface to the keyboard and parallel printer port
in many PCs.
• 8255 provides main features such as single-bit, 4-bit, and byte-
wide input and output ports ; level-sensitive inputs, latched
outputs, strobed inputs or outputs; and strobed bidirectional
inputs/outputs.
• These features are selected under software control.
Fall Semester 2020 21
 8255A Programmable Peripheral Interface
• 8255A is available in 40-pin DIP.
• 8 bit bidirectional data bus 𝐷0 − 𝐷7
• Three byte-wide I/O ports:
• Port A 𝑃𝐴7 − 𝑃𝐴0
• Port B 𝑃𝐵7 − 𝑃𝐵0
• Port C 𝑃𝐶7 − 𝑃𝐶0
• Registers select 𝐴1 − 𝐴0
𝑨𝟏 𝑨𝟎 Function
0 0 Port A
0 1 Port B
1 0 Port C
1 1 Control Register

• Read/write control 𝑅𝐷 , 𝑊𝑅
• Reset and chip select RESET , 𝐶𝑆
• VCC and GND
Fall Semester 2020 22
 8255A Programmable Peripheral Interface
• Three byte-wide I/O ports are divided into two
groups.
• Group A – Port A(𝑃𝐴7 − 𝑃𝐴0 ) and upper part
of Port C (𝑃𝐶7 − 𝑃𝐶4 )
• Group B – Port B (𝑃𝐵7 − 𝑃𝐵0 ) and lower part
of Port C (𝑃𝐶3 − 𝑃𝐶0 )
• These two groups can be programmed in three
different modes.
• Mode 0,
• Mode 1 and
• Mode 2
• Each of the three ports can be configured an input
or output ports.
• 8255 initializes when microprocessor is reset.
Initializing the device causes all ports to be set up as
simple input ports using mode 0 operation.

Fall Semester 2020 23

 8255 Operating Modes
• 8255 operates in three modes:
• Mode 0 – Simple I/O – ports can be configured as level-sensitive inputs or latched outputs. Port A and port B can be
configured as 8-bit input or output ports and port C can be configured for operation as two independent 4-bit input or
output ports.
• Mode 1 – Strobed I/O - port A and port B are configured as two independent byte-wide I/O ports. Allows external data
to be stored into the port until the microprocessor is ready to retrieve it or internal data to be outputted in the port
until the I/O device is ready to get it. Port C pins are also used not for data, but for control or handshaking signals that
help operate either or both port A and port B as strobed input or output ports.
• Mode 2 – Strobed Bidirectional I/O - Only Group A works in this mode. Port A is used to work in bidirectional data
transfer. Port B may be initialized to work in Mode 0 or 1 operation. Port C is used to exchange handshaking signals
with I/O device.

Mode 0 Mode 1 Mode 2

𝑃𝐴7 − 𝑃𝐴 0 I/O I/O Bidirectional
𝑃𝐵7 − 𝑃𝐴0 I/O I/O Not Used
𝑃𝐶7 − 𝑃𝐶4 I/O Handshaking Handshaking
𝑃𝐶3 − 𝑃𝐶0 I/O Handshaking Handshaking

Fall Semester 2020 24

 Programming the 8255 PPI
• The Internal command register can be used as command byte A or command byte B.
• Command byte A programs ports A, B and C as input or output ports in mode 0.
• Command byte B sets (1) or reset (0) bits of ports C only if 8255 in mode 1 or mode 2.

Fall Semester 2020 25

 8255 Command Byte A

Group – A Group – B
7 6 5 4 3 2 1 0
1 Mode A PA PC upper Mode B PB PC lower

0 0 ----- Mode 0
0 1 ----- Mode 1
1 x ----- Mode 2
0 --- Output
1 --- Input
0 --- Output
1 --- Input

Fall Semester 2020 26

 8255 Command Byte B

7 6 5 4 3 2 1 0
0 X X X

Selects a bit of Port C

0 = Reset bit
1 = Set bit

Fall Semester 2020 27

 Summary
• I/O Interface
• Memory Mapped I/O
• Isolated I/O
• I/O Data Transfer
• Basic I/O interface
• Handshaking
• I/O Port Addressing
• Methods of Parallel Data Transfer
• 8255 PPI
• Block diagram & Pin Functions
• Operating Modes
• Programming

Fall Semester 2020 28

 Questions?

Spring Semester 2020 29