3_8 decoder

module decoder3_8(din,dout);

input [3:0]din;

output [7:0]dout;

reg [7:0]dout;

always@ (din)begin

case (din)

0: dout[0]=8'b0000_0001;

1: dout[1]=8'b0000_0010;

2: dout[2]=8'b0000_0100;

3: dout[3]=8'b0000_1000;

4: dout[4]=8'b0001_0000;

5: dout[5]=8'b0010_0000;

6: dout[6]=8'b0100_0000;

7: dout[7]=8'b1000_0000;

endcase

end

endmodule

verilog code of encoder3_8

module encoder3_8(din,dout);

input [7:0]din;

output[2:0]dout;

reg[7:0]dout;

always@(din)
case(din)

8'h01:dout=3'b000;

8'h02:dout=3'b001;

8'h04:dout=3'b010;

8'h08:dout=3'b011;

8'h10:dout=3'b100;

8'h20:dout=3'b101;

8'h40:dout=3'b110;

8'h80:dout=3'b111;

default:dout=3'bxxx;

endcase

endmodule

mux2_1

module mux2_1(a,b,sel,out);

input a,b,sel;

output out;

reg out;

always@ (a or b or sel)begin

if(sel)

out=a;

else

out=b;

end

endmodule
demux2_1

module demux2_1(a,sel,y1,y2,y3,y4);

input [3:0]a;

input[1:0]sel;

output y1,y2,y3,y4;

reg y1,y2,y3,y4;

always@(a or sel)begin

case(sel)

2'b00:y1=a[0];

2'b01:y2=a[1];

2'b10:y3=a[2];

2'b11:y4=a[3];

endcase

end

endmodule

module demux2_1(a,sel,out);

input a sel;

output [1:0]out;

reg [1:0]out;

always@ (a or sel)begin

case(sel)

1'b0:begin out[0]=a;out[1]=1'b0 ; end

1'b1:begin out[1]=a; out[0]=1'b0; end

default:out[1:0]=2'bxx;
end

endcase

endmodule

comparator

module compp2(a,b,l,e,g);

input [3:0]a,b;

output l,e,g;

reg l,e,g;

always@ (a,b)

begin

if(a>b)

begin

g=1'b1;l=1'b0;e=1'b0;

end

else if (a<b)

begin

g=1'b0;l=1'b1;e=1'b0;

end

else

begin

g=1'b0;l=1'b0;e=1'b1;

end

endmodule

d flip flop got simulation results

module df0(d,clk,q,qb);
input clk,d;

output q,qb;

reg q,qb;

always@ (posedge clk)

begin

q<=d;

qb<=!d;

end

endmodule

simulation results got for srff

module srff5(sr,clk,q,qb);

input[1:0]sr;

input clk;

output q,qb;

reg q,qb;

always@(posedge clk)

begin

case(sr)

2'b00:q=q;

2'b01:q=0;

2'b10:q=1;

2'b11:q=1'bz;

endcase

assign qb=~q;

end
endmodule

sr flipflop test bench

module srtb5_tb;

reg sr,clk;

wire q,qb;

srtb5 uut(.sr(sr),.clk(clk),.q(q),.qb(qb))

intial clk=0;

always #10 clk=~clk;

intial begin

sr=00;clk=0;

#100;

sr=01;

#100;

sr=10;

#100;

sr=11;

#100;

end

endmodule

jk flip flop got simulation results

module jkff5(j,k,clk,q,qb);

input j,k,clk;

output q,qb;

reg q,qb;

always@ (posedge clk)

begin

case({j,k})

2'b00:q<=q;

2'b01:q<=0;

2'b10:q<=1;

2'b11:q<=qb;

endcase

assign qb=~q;

end

endmodule

module jkff5_tb

reg j,k;

wire q,qb;

jkff5 uut(.j(j),.k(k),.q(q),.qb(qb));

intial begin

j=0;k=0;clk

#100

j=0;k=1;

#100

j=1;k=0;

#100

j=1;k=1;

#100

end

endmodule
t flip flop got result

module tff5(clk,reset,t,q);

input clk,reset,t;

output q;

reg q;

always@(negedge clk)

if(!reset)

q<=1'b0;

else if (t)

q<=~q;

endmodule
1) What is FPGA ?
2) A testbench is simply a Verilog module. But it is different from the Verilog code we write
for a DUT. Since the DUT's Verilog code is what we use for planning our hardware, it
must be synthesizable. Whereas, a testbench module need not be synthesizable. We
just need to simulate it to check the functionality of our DUT.

3) Variable and signal which will be Updated first?

Signals
4)  Difference between Verilog and vhdl?
5) Compilation
VHDL. Multiple design-units (entity/architecture pairs), that reside in the same
system file, may be separately compiled if so desired. However, it is good
design practice to keep each design unit in it's own system file in which case
separate compilation should not be an issue.

Verilog. The Verilog language is still rooted in it's native interpretative mode.
Compilation is a means of speeding up simulation, but has not changed the
original nature of the language. As a result care must be taken with both the
compilation order of code written in a single file and the compilation order of
multiple files. Simulation results can change by simply changing the order of
compilation.
6) Write a Verilog code for synchronous and asynchronous reset?

Synchronous reset, synchronous means clock dependent so reset must not be

present in sensitivity disk eg:
always @ (posedge clk )

begin if (reset)
. . . end
Asynchronous means clock independent so reset must be present in sensitivity
list.
Eg
Always @(posedge clock or posedge reset)
begin
 if (reset)
. . . end

 What is Verilog?
Verilog is a Hardware Description Language (HDL) used for describing a digital system
such as a network switch, a microprocessor, a memory, or a flip-flop. Verilog is mainly
used to verify analog circuits, mixed-signal circuits, and the design of genetic circuits. It
is also used in the design and verification of digital circuits at the register-transfer level
of abstraction.

Verilog supports a design mainly at the following three levels of abstraction:

o Behavioral level
o Register-transfer level
o Gate level

 What is VHDL? / What is the full form of VHDL in VLSI?

VHDL is an acronym that stands for Very high-speed integrated circuit Hardware
Description Language. It is a programming language used to describe circuits in digital
systems and model the digital system by using dataflow, behavioral and structural style
of modeling.

What are the main usages of VHDL?

Following are the main usages of VHDL:

o VHDL is hardware describing language used to describe the behavior of electronic

circuits, most commonly digital circuits.
o It is mainly used to design hardware and create test entities to verify the behavior of that
hardware.
o It is used as a design entry format by various EDA tools, such as synthesis tools,
simulation tools, and formal verification tools.
Are Verilog and VHDL the same?
Verilog and VHDL are not identical. They are different, and the main difference between
Verilog and VHDL is that Verilog is based on C language while VHDL is based on Ada
and Pascal languages.

What are the main differences between Wire and Reg?

Key differences between Wire and Reg

Wire Reg

The wire is used to assume value. Reg is used to hold value.

Wire requires drivers to get output values. Reg does not need a driver to get output.

The wire elements can only be used to model The reg elements can also be used for com
combinational logic. sequential logic.

We can use wire at the left-hand side of an assigned We cannot use reg on the left-hand side of an as
statement.

What does the timescale 1 Ns/ 1 Ps signify in a Verilog code?

The timescale directive is a compiler directive used to measure simulation time or delay
time. The timescale / reference_time_unit specifies the unit of measurement for times
and delays. The time_precision specifies the precision to which the delays are rounded
off.

7)