Diode Bridge Rectifier with Improved Power
Quality Using Capacitive Network
Sagar Gupta
Cypress Semiconductor Technology India Pvt. Ltd.
Karnataka, India
Email: sagar.gupta.2410@gmail.com
Abstract—Widely distributed single-phase power electronic
rectifier loads are increasing source of harmonics in power distri-
bution system. These harmonics have many well known adverse
impacts on the power system. So it is necessary to improve the
power quality of the rectifiers. This paper presents a novel single
phase rectifier in which capacitors are used in parallel with
diodes in one leg of the rectifier. A general analytical model of
the proposed topology is obtained. The closed form expressions
for the rectifier waveforms helps in parameter selection that
leads to optimal performance in terms of input current THD.
A comparative study of different topologies of rectifiers are done
in terms of input voltage, current waveform distortion, output
dc voltage ripple, and desired target for dc output voltage. The
proposed topology reduces the total harmonic distortion from
145 percent in normal rectifier to 63 percent while maintaining
voltage ripple less then 0.3 percent. The proposed topology keeps
dc bus ripple small while simultaneously providing better THD.
The passive components considered for improving harmonic
injection are 2 small capacitors. The additional cost required
for the proposed rectifier is low, the proposed rectifier also has
a higher efficiency than the other commonly used topologies.
I. I NTRODUCTION
Non-linear loads such as controlled and uncontrolled, single
phase and three phase rectifiers injects considerable amount of
lower order harmonics into the grid and distorts the voltage
at point of common coupling [1], [2]. Harmonics cause ex-
cessive heating, pulsating and reduced torque in motors and
generators, increased heating and voltage stresses in capacitor,
malfunction of switch gears and relays and reduces the life of
products [3], [4]. It is therefore necessary to reduce harmonic
in electric power system. Also in case of dc loads it is
important to get low ripple in output dc voltage for its proper
functioning [5]. So it is necessary to provide dc output at
low ripple keeping the harmonics injected in the line to a
reasonable low value.
Passive Front End (PFE) rectifiers followed by Power Factor
Correction (PFC) stage, and Active Front End (AFE) rectifiers
maintains dc bus voltage at desired level and harmonics
injected, at switching frequency, can be filtered out using
first order filters [6], [7], [8]. Using the above mentioned
topologies, for low power applications such as LED lighting,
increases the cost as it requires active switches such as MOS-
FET or IGBT and additional sensors, for controlling dc bus
This work was supported by CPRI, Ministry of Power, Government of India,
under the project Power conversion, control, and protection technologies for
microgrid.
978-1-4673-8888-7/16/$31.00 © 2016 IEEE
Nimesh V, Vinod John
Department of Electrical Engineering
Indian Institute of Science Bangalore, Karnataka, India
Email: nimesh@ee.iisc.ernet.in, vjohn@ee.iisc.ernet.in
(a) (b)
(c)
Fig. 1. Rectifier topologies (a) Diode rectifier with capacitive output filter
(b) Voltage doubler rectifier (c) Split capacitor full bridge rectifier.
TABLE I
IEC 61000-3-2 H ARMONIC L IMITS FOR C LASS C EQUIPMENTS FOR
INPUT POWER < 25 W
Harmonic (n) Limit(% of the fundamental input current)
3 86
5 61
voltage and input current[9]. So for lower power applications
PFE rectifier circuits, diode rectifier with capacitive filter, as
shown in Fig. 1(a), and voltage doubler rectifier with two
split capacitances, as shown in Fig. 1(b), are preferred. It
is well known that diode rectifier with capacitive filter, as
shown in Fig. 1(a), has negligible output voltage ripple but
injects significant amount of lower order harmonics into the
grid. Voltage doubler, shown in Fig. 1(b), has low harmonic
injection when Cs is kept small but ripple in output voltage
is considerably high.
According to IEC 61000-3-2, equipments are classified in
4 categories, Class A, Class B, Class C and Class D. Lighting
equipments, whose front end is a rectifier, falls into Class C
and harmonic standards for these equipments is summarized in
Table I. In this paper a new Split Capacitor Full Bridge (SCFB)
rectifier is proposed. The proposed SCFB rectifier shown in
Fig. 1(c) is suited for low power applications. SCFB rectifier
is a combination of diode rectifier with capacitive filter and
voltage doubler topology. Initial simulation studies comparing
the three topologies shown in Fig. 1 is summarized in section
 TABLE II
VALES AND PARAMETERS CONSIDERED FOR THE STUDY ( A ) BASE positive half cycle of vg . Conducting elements of in each
VALUES ( B ) R ECTIFIER PARAMETERS mode is shown as dark black shade and the non-conducting
elements are in light black shades, as shown in Fig. 2. The
main assumptions for this analysis are:
Parameter Base Value
Vb 340 V Parameter Value(per unit) 1) Diodes are assumed ideal.
Pb 25 W Vg 240 V (0.71) 2) ESR of the capacitances have been ignored.
fb 50 Hz Po 25 W (1)
3) Ratio ∆ Vo /Vo  1.
Ib 73.53 mA RL 5 kΩ (1.08)
Zb 4624 Ω L 2 mH (136 µ)
A. Mode-I from t1 < t < t2
Lb 14.7 H Rg 5 Ω (1.08 m)
Cb 688.9 nF
(b) In Mode-I, during positive half cycle of the grid supply
(a) diode D1 starts conducting, at t = t1 . At t = t1 , vc1 (t1 ) =
V1 = Vg (t1 ), vc2 (t1 ) = V2 , iL (t1 ) = 0 and v0 (t) = vc1 (t) +
vc2 (t). The governing equations for circuit shown in Fig. 2(a)
II. The analytical closed form expressions for waveforms are can be written as,
covered in section III and Appendix. The equations for wave- diL 1
Z
forms of SCFB rectifier that are derived in this paper are used vg (t) = iL Rg + L + i1 dt + V1 (1)
dt Z Cs
for circuit optimization. This leads to circuit parameters that 1
meet tight dc voltage ripple requirement while simultaneously v0 (t) = iR RL = ic dt + V1 + V2 (2)
CL
having minimum input voltage distortion. Section IV details
analytical, simulation and experimental results. This section During this mode, upper split capacitor (vc1 (t)) charges from
also covers the effects of line inductance and load capacitance grid and lower split capacitor(vc2 (t)) discharges into load and
in optimal values split capacitor and THD of line current grid. This mode ends when either diode D1 stops conducting,
drawn, section V concludes the paper. current drawn from grid goes to zero, or vc2 (t) has fallen to
zero.
II. S IMULATION S TUDIES
B. Mode-II from t2 < t < t3
Initially simulations on all three topologies, shown in Fig. 1
was carried to check the performance of the proposed model. Mode-II starts at t2 when diode D2 starts conducting that
Per unit values and design specifications of the converter used is vc2 (t2 ) = 0 and D1 is already conducting. Let vc1 (t2 ) =
for simulation are given in Table II(a) and II(b) respectively. VmII1 and iL (t2 ) = IL0 . Fig. 2(b) shows the equivalent circuit
Po , Vg , fs = 50 Hz, RL Lg , Rg are rated power, grid and the equations for this mode can be written as,
voltage rms, grid frequency, line impedance and load resis- diL 1
Z
tance, respectively. With line impedance neglected, effects vg (t) = iL Rg + L + i1 dt + VmII1 (3)
dt Z Cs
of variations in values of load capacitance, CL , and split 1
capacitance, Cs , in grid current THD and ripple in output v0 (t) = iR RL = ic dt + VmII1 (4)
CL
voltage is studied. Summary of the results in tabulated in
Table. III. It can be observed that the proposed SCFB topology As diode D2 is conducting, this ensures that the lower split
has the advantages of both the normal rectifier with low capacitor does not charge in opposite direction, so vC2 (t) in
output voltage ripple, and voltage doubler circuit with lesser this mode will remain zero. This mode ends when diode D1
distortion in line current drawn. stops conducting, that is current drawn from the grid dies down
to zero.
III. A NALYSIS OF SCFB R ECTIFIER
C. Mode-III from t3 < t < t4
Fig. 2 shows the split capacitor full bridge (SCFB) rectifier
and its operating modes. The grid is modeled as a sinusoidal Mode-III occurs when the current iL reaches zero at the
voltage source vg in series with line impedance consisting of end of Mode-I with vc1 (t2 ) and vc2 (t2 ) > 0. In this case time
Rg and L in series. The load is modeled as a resistor(RL ). t3 equals to the instant t2 which is the end of Mode-I. In this
For modeling of the topology different modes of operation mode, no diodes are conducting, therefore the current from
are identified and the governing equations of these modes the grid is zero and load is supplied by the energy stored
are covered in this section. The analysis is carried out for in capacitors, CL Cs . At t = t3 , let vC1 (t3 ) = VmIII1 and

TABLE III
C OMPARISON OF STANDARD RECTIFIER , VOLTAGE DOUBLER AND SCFB RECTIFIER WITH VARIATION OF Cs AND CL

Topology 1(Normal Rectifier) Topology 2(Voltage Doubler) Topology 3 (SCFB Rectifier)

Cs (µF)(pu) CL (µF)(pu) Vo (V)(pu) ∆V (V)(pu) THD(%) Vo (V)(pu) ∆V (V)(pu) THD(%) Vo (V)(pu) ∆V (V)(pu) THD(%)
222 (322.6) 222 (322.6) 338 (1.0) 2.9 (8.5 m) 357 72 (0.3) 104 (0.3) 4.6 339 (1.0) 3.5 (0.01) 338
470 (666.7) 470 (666.7) 339 (1.0) 1.4 (4.1 m) 386 137 (0.4) 178 (0.5) 8.1 310 (1.0) 2.0 (5.9 m) 341
1000 (1.5 k) 1000 (1428.6) 340 (1.0) 0.8 (7.5 m) 394 224 (0.7) 235 (0.7) 20 340 (1.0) 1.4 (4.1 m) 263
2000 (3.3 k) 2000 (29.1) 340 (1.0) 0.3 (0.9 m) 395 313 (1.0) 230 (0.7) 33 340 (1.0) 1.6 (4.7m) 65
2x106 (3.3 M) 222 (322.6) 338 (1.0) 2.9 (8.5 m) 357 679 (2.0) 1.4 (4.0 m) 438 679 (2.0) 1.3 (3.8 m) 458
 (a) (b)

(c) (d)
Fig. 2. Different modes of operation for the SCFB rectifier (a) Mode-I, (b) Mode-II, (c) Mode-III, and (d) Mode-IV.

(a) (b) (c)

Fig. 3. Circuit performance as a function of load capacitance and split capacitance showing (a) Percentage total harmonic distortion (b) Output voltage ripple
∆Vo and (c) Average output voltage Vo .

vC2 (t3 ) = VmIII2 . Equivalent circuit for this mode is shown parameters. All remaining voltages and currents in the circuit
in Fig. 2(c), governing equations for this mode is, can be obtained from these capacitor voltages.
For an input voltage of Vg = 240 V and load resistance
v0 (t) = iR RL = vC1 (t) + vC2 (t) (5)
of RL = 5 kΩ(load power of around 22 W), the effect of
(t−t3 )/τ1
v0 (t) = (VmIII1 + VmIII2 )e (6) variations in CL and Cs on THD, Vo and ∆ Vo is shown in
CL + Cs /2 Fig. 3. From these results it is seen that minimum THD is
τ1 = (7) obtained when Cs = 1.647 µ F for a particular value of CL
RL
T and the value of CL is chosen such that ∆ Vo is less than 1 V
D. Mode-IV from t4 < t < 2 + t1 and it is 470 µ F . It can also be observed, from Fig. 3(a) that
Mode-IV occurs at the end of Mode-II when iL reaches 0 the minimum of the THD is not significantly affected by CL .
with vC2 (t) = 0. Hence time t4 matches with time t3 of It can also be seen from Fig.3(b) that low values of CL leads
Mode-II. In this diode D2 is conducting and load is supplied to high ripple in the dc bus voltage. Also Fig. 3(c) shows that
by energy stored in capacitors CL Cs . Let Mode-IV start at larger values for Cs lead to increase in the average dc bus
t4 and vC1 = VmIV1 , the equivalent circuit is shown in Fig. voltage.
2(d) and the governing equations are given by, From Fig. 3(a), it can be concluded that by choosing a
specific value of split capacitance(Cs ),minimum THD injec-
v0 (t) = iR RL = vC1 (t) (8)
t−t4
tion can be obtained of a particular load. Also Fig. 3(b)
v0 (t) = VmIV1 e τ (9) shows that output voltage ripple are mainly controlled by load
CL + Cs capacitance(CL ), so THD and output voltage ripple can be
τ= (10) controlled independently.
RL
The solutions of above mentioned differential equations for 1) For small value of split capacitor(Cs < 2 µF ), vc2 (t)
mode-I and mode-II is given in the Appendix. Analytical falls to zero before diode D1 stops conducting in positive
expressions in (6), (9), (11), (16) and (18) provide expressions half cycle of supply then we get Mode-I followed by
for the capacitor voltage waveforms in terms of the circuit Mode-II and finally Mode-IV. In this case Mode I starts
at t1 = 0. For this mode, vg and iL , vc1 and vc2 , and
 (a) (b) (c)

(d) (e) (f)

Fig. 4. Analytical Results for different modes of operation, Cs = 1 µF (a, b, c) and for Cs = 3 µF (d, e, f): (a, d) Grid voltage, vg and current drawn
from grid, iL (t), in per unit. (b, e) Voltage across upper split capacitor, vc1 (t) and lower split capacitors, vc2 (t). (c, f) Output voltage Vo .

(a) (b) (c)

Fig. 5. Comparison of input voltage and current waveforms (a) Results from analytical model (b) Results obtained from simulation (c) Experimental
measurements: Grid voltage(CH2: 2 V/div, 50:1 probe) and current(CH1: 20 mA/div).

TABLE IV
Vo are shown in Figs. 4(a), (b), (c), respectively. H ARMONIC A NALYSIS OF L INE C URRENT OF SCFB R ECTIFIER FOR
2) For large value of split capacitor(Cs > 2 µF ), diode D1 Pout = 23 W
stops conducting before vc2 (t) falls to zero in positive
Harmonic Order Analytical Experimental
half cycle of supply. In this case Mode-I followed by Fundamental(50 Hz) 100 (0.156A) 100 (0.1575A)
Mode-III. Also, in this case the start of Mode-I is at 3rd 41 45.7
t1 6= 0. For this case, vg and iL , vc1 and vc2 , and Vo 5th 26.9 21.4
are shown in Figs. 4(d), (e), (f), respectively. 7th 8.9 11.6
9th 19.4 23.5
It is observed from analysis, simulation and experiments that 11th 5.33 2.9
selection of capacitance parameters such that the initiation of 13th 15.3 17.4
Mode-III immediately after Mode-I leads to minimum source 15th 5.3 6.3
current THD. Fig. 5 shows the supply voltage and supply 17th 12.4 1.4
current for L = 2mH Rg = 5Ω Cs = 1.65µF CL = 19th 5.6 6.2
470µF RL = 5000Ω. For RL = 5000Ω, Cs = 1.65µ is Total THD 66.7 62.48
the lowest point of THD injection.
IV. A NALYTICAL , S IMULATION AND E XPERIMENTAL results, shown in Fig. 5(b), and experimental results, shown
R ESULTS in Fig. 5(c), matches closely. THD of the current drawn
Analysis, simulation and detailed experimental studies are from the grid for analytical, simulation and experimental are
performed the proposed topology shown in Fig. 1(c). Design 66.7%, 66.7% and 62.5% respectively. Table. IV summarizes
ratings of the converter are covered in section II. Effects of the harmonics, up to 950 Hz. This meets the IEC 61000-3-
line inductanceL and load capacitance CL in optimal split 2 requirements specified in Table. I. The small deviation in
capacitance Cs and THD in line current is also discussed in experimental measured THD is due to the non zero resistances
this section. Fig. 5 shows the grid voltage and current drawn of the diodes and rectifier, which also shows in terms of
from the grid. Analytical results, shown in Fig.5(a), simulation the reduced oscillations in the waveform. Efficiency of SCFB
 100 100 2 100
80 80
1.5 80
60 60
60
40 40 1
40
20 20 0.5
20
0 0
2 4 6 8 10 2 4 6 8 10 0 1000 2000 3000 4000 0 1000 2000 3000 4000

(a) (b) (c) (d)

Fig. 6. (a) Variation of Cs with L, (b) Variation of THD with L, (c) Variation of Cs with CL , (d) Variation of THD with CL .

rectifier is measured to be 99.36% and that of diode rectifier A. Mode-I from t1 < t < t2
in Fig. 1(a) is 98.29% in experimental studies. The equations (1) & and (2) in Section III A form a fourth
A. Effect of Line Inductance order system. The roots of the characteristic equation are
solved assuming well separated circuit poles[5].
Values of line inductance(L) varies from few µH to few
mH. Effect of variations in L on Cs is shown in Fig. 6(c). It 0 C4
vc2 (t0 ) = −Vm ωn2 y[A4 e−yt + B4 cosωt0 + sinωt0 +
can be seen that values Cs decreases with increase in L. For a ω
!
particular value of Cs0 = 1.65µF , effect of L on line current −D4 E4
−ξωn t0 0
THD is shown in Fig. 6(b). In the circuit shown in Fig.1(a), e p sin(ωd t + φ) + sinωd t0 ]
2
1−ξ 2 ωd
line current THD decreases with increase in L, but in SCFB !
rectifier the increase in L affects slowly and increase in THD −yt0 0 0 −B5
level. +V2 e −yωn2 V1 [A5 e−yt +e−ξωn t p 0
sin(ωd t + φ)
2
1 − ξ2
B. Effect of Load Capacitance C5
+ sinωd t0 ] (11)
The ripple in output voltage decreases as the optimal load ωd
capacitance CL increases. Effect of variations in CL on Cs is where,
shown in Fig. 6(c). It can be seen that this value of Cs remains s
a constant for CL greater than 10 µF . For a particular value of RL (Cs + CL ) + 2Cs Rg
Cs0 = 1.65µF , the effect of CL in line current THD is shown ωn = (12)
RL LCs (Cs + 2CL )
in Fig. 6(d). As opposed the topology shown in Fig. 1(a), in
SCFB rectifier the line current THD remains almost a constant 1
y= (13)
for higher values of load capacitance CL . So the value of CL RL (Cs + CL ) + 2Cs Rg
is chosen to be 470 µF to so that voltage ripple is within a
desirable limit. 2LCs + RCs Rg (Cs + 2CL )
ξ= p
V. C ONCLUSION 2 LCs RL (Cs + 2CL )[RL (Cs + 2CL ) + 2Cs Rg ]
p (14)
In this paper a SCFB rectifier is proposed to reduce the p
2 −1
2
1 − ξ 2
harmonic injection in the line by using capacitive components. ωd = ωn 1 − ξ 2 , φ = tan (15)
ξ
Two capacitances(X rated) are used to affect the input line
current so that input line current harmonics are reduced. The and,    
A4 0
analytical modeling of the new topology is systematically  B4   0 
performed. The results are verified with simulation results  C4  = P −1 
   
C R
L L sinωt1

and experimental results. The analytical model is used to  
D4 
 
CL RL ωcosωt1 + sinωt1 
find the value of capacitances(Cs ) for which minimal line
E4 ωcosωt1
current THD can be obtained for a particular load. Also it    
is shown that ripple in output voltage can be independently A5 0
controlled by load capacitance(CL ). The proposed rectifier B5  = N −1  LCs 
circuit also operates with a higher efficiency compared to C5 Cs Rg − CL RL
standard rectifiers.
A PPENDIX
For a rectifier most important thing to be known are its
output voltage for it output characteristics, and line current to
know it input performance. Equations which are obtained by
analysis in Mode-I and Mode-II are solved here to get V0 and
iL .
 where,
0 C1 L + RL Rg (CL + Cs )
v0 (t0 ) = RL Cs Vm ωn2 y[A1 e−yt + B1 cosωt0 + sinωt0 + p= +
! ω 2LRL (CL + Cs )
−D1 E1
0
s
e−ξωn t p sin(ωd t0 + φ) + sinωd t0 ] L + RL Rg (CL + Cs ) 2 RL + Rg
2
1−ξ 2 ωd ( ) −
" # 2LRL (CL + Cs ) LRL (CL + Cs )
0 0 −B 2 C2
+V1 A2 e−yt + e−ξωn t p sin(ωd t0 + φ) + sinωd t0
2
1 − ξ2 ωd L + RL Rg (CL + Cs )
" # q= −
−B2 C2 2LRL (CL + Cs )
−yt0 −ξωn t0 0 0
+V2 A2 e +e p sin(ωd t + φ) + sinωd t s
2
1 − ξ2 ωd L + RL Rg (CL + Cs ) 2 RL + Rg
( ) −
(16) 2LRL (CL + Cs ) LRL (CL + Cs )
where,
   
A6 0
B6 0
  = Q−1 × 
     
A1 0  C6   sinωt2 

 B1   0 
 C1  = P −1  sinωt1 
    D6 ωcosωt2
   
D1  ωcosωt1  where,  
E1 0 1 0 1 1
p + q 1 q p 
where Q= 2

 
 pq p+q ω ω2 
1 1 0 1 0 0 pq 2 ω 2 q ω 2 p
 2ξωn 2ξω n + y 1 y 1 
 2 2 2
 di(t00 )
P = ω + ω2n ωn + 22ξωn y 2ξωn + y ω2 y  iL (t00 )Rg + L = vg (t00 ) − vo (t00 ) (19)
 2ξωn ω ωn y ωn2 + 2ξωn y ωn2 y ω 2 
 dt00
ωn2 ω 2 0 ωn2 y 0 ωn2 y Knowing the grid voltage and Vo (t) in (18), the input current
    iL (t) is solved in Mode-II. The expressions for source current
A2 1 and output voltage are used to obtain THD and voltage design
B2  = N −1 2ξωn − 2LCs ωn2 y 
trade off relationship shown in Fig. 3.
C2 ωn2 (1 − 2yCs Rg )
    R EFERENCES
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 
2Rg
00
 e−pt + e−qt 00
− (p + q)  00

00 
 + L e−pt − e−qt   (18)
 2 2(q − p)