Performance Evaluation of FinFET-Based FPGA

Cluster Under Threshold Voltage Variation

Mohamed Mohie El-Din1 , Hassan Mostafa2,3 , Hossam A. H. Fahmy2 , Yehea Ismail3 , Hamdy Abdelhamid3
1
Mentor Graphics Corporation
2
Electronics and Communications Engineering Department, Cairo University, Giza 12613, Egypt
3
Center for Nano-electronics & Devices, American University in Cairo & Zewail City for Science and Technology, Cairo, Egypt

Abstract—The performance of FinFET-based FPGA cluster is
evaluated with technology scaling for channel length from 20nm
down to 7nm showing the scaling trends of basic performance
metrics. The impact of threshold voltage variation, considering
die-to-die variations, on the delay, power, and power-delay prod-
uct is reported after the simulation of a 2-bit adder benchmark.
Simulation results show an increasing trend of the average power
and power-delay product variations with threshold voltage as we
go down with technology node. On the contrary, the delay is
showing the least percentage of variations with threshold voltage
at the most advanced node of 7nm.
Index Terms—Nano-scale FinFET, FPGA cluster, Technology
scaling, threshold voltage variations
I. I NTRODUCTION
ri-Gate FinFET has been deployed in production as a
T mature, multi-gate MOS solution to be considered as
one of the most compelling alternatives to the conventional
planar transistor for sub 22nm technology nodes. This is due
to its high current drive capability by extending the effective
channel width in a third dimension, higher transistor density,
superior sub-threshold leakage control, and reduced power
supply voltage while maintaining superior speed. This, in com-
bination with reduced leakage current, results in substantial
power savings [1], [2], [3]. For the long term projections by the
International Technology Roadmap of Semiconductors (ITRS-
2013) [4], there are several emerging new devices are on the
horizon. However, the multi-gate structures are the only viable
solution to effectively scale the channel length with controlling
the short channel effects. To what extent these devices are
really scalable still is an open research. Therefore, a rigorous
investigation of the performance of Tri-gate FinFET along the
scaling roadmap in basic circuit blocks is essential.
In order to sustain reprogrammable and easily recon-
figurable designs with flexible prototyping capabilities and
enhanced performance, taking advantage of hardware par-
allelism, FPGAs are being used in production as reliable
candidates in electronic design in terms of performance, time
to market, and long-term maintenance. In addition, FPGA-
based hardware solutions are considered the most cost-aware
when it comes to decreasing nonrecurring engineering (NRE)
expenses. This is due to the continuous change in system
requirements and design specifications over time, compared to
custom ASIC designs which endures far larger NRE expenses
of respinning.
For FPGA users, the key performance advantages posed by
FinFETs in production, as the continuation of Moore’s law
in the march of improvements in transistor density, perfor-
mance, control over static and active dissipation, and cost-per-
transistor, make the programmable logic that advances to 14nm
technology and beyond power competitive with ASIC design
solutions on available competing design nodes, with even more
significant advantages in programmability, performance, and
flexibility [5].
The targeted FPGA used in our study is an Island-style
FPGA which consists of 2 dimensional array of repeated tiles,
each consists of a logic cluster block, routing channels to
connect inputs/outputs to the clusters, and Inter-cluster routing
to connect clusters with each other as shown in Fig.1.

Table I
T HE SIMULATED DEVICE PARAMETERS

Device TG-FinFET
L (nm) 20 16 14 10 7
Tf in (nm) 15 12 10 8 6.5
Hf in (nm) 28 26 23 21 18
VDD (V) 0.9 0.85 0.8 0.75 0.7

978-1-4799-8893-8/15/$31.00 ©2015 IEEE Figure 1. Island-style FPGA

 Some previous work was done to study different config-
urations of FinFET-based FPGA Lookup tables (LUTs) [6]
implemented using 16nm technology and simulated using
HSPICE. The metrics used to evaluate the different candidate
LUTs were the delay, energy, and the layout area.
In this work, we have built FinFET-based FPGA logic
cluster for evaluation as shown in Fig. 2. It consists of three
basic logic elements (BLE), each encapsulates a LUT, shown
in Fig. 3, with size of 4 (four inputs), D-Flip-Flop, and 2-
to-1 multiplexer to select either the registered or unregistered
LUT output. Both of cluster size, N and LUT size, K have
been obtained by experimentally deriving the relationship
between the number of cluster logic block inputs required to
achieve 98% utilization as a function of K and N [7]. This
is I = K 2 × (N + 1)where I is the number of distinct cluster
inputs ( 8 in our case ). All in all, we have in our design Figure 2. Structure of (a) Basic Logic Element (BLE) and (b) Logic Cluster
11 inputs to the logic cluster, eight of them are distinct inputs
while the other three are the outputs for the three LUTs which
make the output of each LUT for direct connection to one of
the inputs of the neighboring LUTs in the same cluster which
implies the “fully connected” approach; this means that all I
cluster inputs and N outputs can be programmably connected
to each of the K inputs on every LUT. This, in turns, increases
the FPGA speed by saving the number of inputs and bypassing
the long capacitive routing channels.
The FPGA cluster built for this work has been configured
to build 2-bit adder benchmark circuit by programming the
SRAM cells in LUTs accordingly and configuring the selection
lines of the multiplexers to allow fully-connecting the BLEs. Figure 3. Lookup table with 4 inputs and 16 SRAM cells
This paper is organized as follows: Section II states the sim-
ulation setup and methodology, Section III presents the results The performance metrics used to evaluate the cluster per-
and discussions, some design insights and recommendations formance under threshold voltage variation are the average
are given at Section IV, and finally the conclusion and future power, delay, and power-delay product (PDP). Average power
work are discussed at Section V. is calculated by multiplying the average of the current drawn
from the source by the value of the supply voltage. Delay is
II. SIMULATION METHODOLOGY calculated by considering the most critical path from the input
In this work, we have used the predictive technology model source to the output from the third BLE which represents the
for multi-gate transistors (PTM-MG) [8] starting from 20nm carry output resulting from the 2-bit addition operation. And
down to 7nm technology nodes for low-standby power devices the PDP is the multiplication of both the average power and
(LSTP) which are based on BSIM-CMG (short for Berkeley delay. This is being calculated for each technology node start-
Short-channel IGFET Common Multi-Gate) compact models. ing from 20nm down to 7nm. And for each technology node,
PTM-MG models follow the scaling approach of not only we studied the performance metrics with threshold voltage
scaling the channel length (L) but also the supply voltage variations within range ±18% with 6% step of the nominal
(VDD ), fin thickness (Tf in ), and fin height (Hf in ) as reported threshold voltage of this technology node. The simulated
in Table I. Hence, the FinFET is used such that the effective values are reported in Table II. The FPGA cluster building
channel width (Wef f = 2Hf in + Tf in ) . is done using Cadence Virtuoso ADE and all the simulations
are done using Virtuoso ADE XL simulator.
Table II
T HRESHOLD VOLTAGE VARIATIONS III. RESULTS AND DISCUSSIONS
A. Average Power
Node(nm) Threshold voltage (mv)
Nominal % change values (of nominal) The simulation results showed that the average power vari-
±6% ±12% ±18% ation percentages with threshold voltage variation increase as
7 268 16 32 48
10 292 17.5 35 52.2
we scale down the FinFET technology node. Fig.4 shows the
14 311 18.6 37.3 55.9 chart for percentages of average power variation with three
16 320 19.2 38.4 57.6 different change percentages for threshold voltage for all the
20 330 20 40 60 technology nodes included in the study. For each node, the
Figure 4. Power variation percentages with threshold voltage variation for
various technology nodes
Figure 5. Delay variation percentages with threshold voltage variation for
various technology nodes
percentages variation of average power decrease as we
increase the threshold voltage change percentages from -18%
till -6% as the current value decreases with increasing the
threshold voltage value.
B. Delay
Concerning the simulation results for delay variation with
threshold voltage, it turns out to be that 7nm node gets
the least delay variation percentages with threshold voltage
variation compared to the other technology nodes, as shown
in Fig.5. For the other technology nodes, the percentages of
delay variation are almost comparable. Also, for each node,
the delay percentage increases as we increase the threshold
voltage percentage from 6% to 18%.
C. Power-Delay Product
Variation percentages of PDP with threshold voltage vari-
ation are reported in Fig.6. PDP variation percentages with
threshold variations increase with down scaling of FinFET
technology nodes. The PDP chart is following the same trend
as the power variation percentage with technology nodes.
Hence, the power variation percentages are considered the
Figure 6. PDP variation percentages with threshold voltage variation for
various technology nodes
dominant contributor in the PDP equation compared to
delay due to the larger variation percentages of the average
power. Also, the percentages variation of PDP decrease as we
increase the threshold voltage change percentages from -18%
till -6%.
IV. D ESIGN I NSIGHTS
For the work to be more meaningful and beneficial, we came
up with some design insights and recommendations based on
our simulation results. In our study, we defined a targeted
yield percentage of 99.87% for which we determine the design
constraints of different performance metrics based upon. This
targeted yield percentage represents the 3-sigma value, or three
standard deviations of the mean, for a particular technology
node; The mean value here is the nominal value (the metric
value at zero percentage change in the threshold voltage for
this node), and the sigma here is calculated by dividing the
largest metric’s variation percentage of that metric, which is
considered as the 3-sigma value, by three. Figures 7 to 9
show the design constraints values for average power, delay,
and PDP for all the technology nodes at the extreme points
of threshold voltage variation percentages (18% and -18%)
respectively. So, the design constraints allowed for each metric
is calculated as µ ± 3σ where µ is the mean value. The
outlier points plotted in the power and PDP curves for 7n node
justify the large power variation percentages at this node as
stated previously, which demonstrates the large gap between
the constraints boundary of 18% and -18% of threshold voltage
at this node.
V. C ONCLUSION AND F UTURE W ORK
The performance of FinFET-based FPGA cluster is evalu-
ated with technology scaling by configuring the cluster to be
2-bit adder as a benchmark. The impact of a given range of
threshold voltage variations on basic performance metrics is
reported. The results show that the average power variations
and the PDP variations with threshold voltage variation are
increasing as we scale down the technology node, while the
delay variation with threshold voltage variation is not
 following a certain trend with the technology scaling but it’s
with the least values at 7nm node. Design constraints values
are reported for each performance metric for all the technology
nodes included in this study to give the designers some useful
insights and recommendations.
Finally, our work suggests two future directions: building
an FPGA tile that utilizes the cluster we have designed and
evaluated in our work, with the associated routing channels
and Inter-cluster routing to be considered in simulations, and
adding the leakage and dynamic power to the metrics used in
the performance evaluation.
ACKNOWLEDGEMENT
This research was funded by NTRA, ITIDA, Cairo Univer-
sity, Zewail City of Science and Technology, AUC, the STDF,
Intel, Mentor Graphics, and MCIT.
Figure 7. Power constraints with threshold voltage for various technology
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Figure 9. PDP constraints with threshold voltage for various technology nodes