Experiment 1: A submission template

YASH Roll Number 200070092

EE-214, WEL, IIT Bombay
27 september,2021

Overview of the experiment:

Objective
• The purpose of this experiment was to make given Arithmetic Logic Unit using Quartus
software ,simulate the design usnig RTL and Gate level Simulation and check our design using
scanchain

Approach to the experiment:

Describe the approach you have used to complete the assignment. You must draw a schematic/block
diagram of the design (hand-drawn/software).

Design document and VHDL code if relevant:

1
You should give a brief description of whatever designs you have constructed and a sketch (architecture
of main logic) of the code you have written as part of the experiment.

library ieee;
use ieee.std_logic_1164.all;

entity Beh_modelling is
generic(
operand_width : integer:=4;
sel_line : integer:=2
);
port (
A: in std_logic_vector(operand_width-1 downto 0);
B: in std_logic_vector(operand_width-1 downto 0);
sel: in std_logic_vector(sel_line-1 downto 0);
op: out std_logic_vector((operand_width*2)-1 downto 0)
);
end Beh_modelling;

architecture a1 of Beh_modelling is
function add(A: in std_logic_vector(operand_width-1 downto 0); B: in
std_logic_vector(operand_width-1 downto 0))
return std_logic_vector is
variable sum : std_logic_vector(3 downto 0) := (others => '0');
variable carry : std_logic_vector(3 downto 0) := (others => '0');
-- Declare "sum" and "carry" variable
-- you can use aggregate to initialize the variables & signals as shown below
-- variable variable_name : std_logic_vector(3 downto 0) := (others => '0');
begin
-- write logic for addition
-- Hint: Use for loop
Parity: for i in 0 to 3 loop
sum(i):= A(i) xor B(i) xor carry(0);
carry(0):= (A(i) and B(i)) xor ((A(i) xor B(i)) and carry(0));
end loop;
return carry(0) & sum;
end add;

begin
alu : process( A, B, sel )
begin
-- complete VHDL code for various outputs of ALU based on select lines
-- Hint: use if/else statement

if sel = "00" then

op <= A & B;
elsif sel = "01" then
op <= "000" & add(A,B) ;
elsif sel = "10" then
op <= "0000" & (A xor B);
else
op <= "000" & add(A,A);
end if;

--
-- add function usage :
-- signal_name <= add(A,B)
-- variable_name := add(A,B)
--
2
-- concatenate operator usage:
-- "0000"&A
end process ; -- alu
end a1 ; -- a1
RTL View:
Attach screen-shot of the RTL view generated by Quartus.

DUT Input/Output Format:

3
Mention the format (LSB/MSB of input and output) and few test cases from trace-file.
Input LSB-A0,B0
Input MSB-A3,B3
Output LSB-Y0
Output MSB-Y7
Input format:
S1 S0 A3 A2 A1 A0 B3 B2 B1 B0
Output format:
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
Test cases from Tracefile
1001000100 00000000 11111111
1001000101 00000001 11111111
1001000110 00000010 11111111
1001000111 00000011 11111111
1001001000 00001100 11111111
1001001001 00001101 11111111
1001001010 00001110 11111111
1001001011 00001111 11111111
1001001100 00001000 11111111
1001001101 00001001 11111111
1001001110 00001010 11111111
1001001111 00001011 11111111
1001010000 00000101 11111111
1001011000 00001101 11111111

RTL Simulation:

4
Attach the clearly visible screen-shot of RTL simulation waveforms.

Gate-level Simulation:
Attach the clearly visible screen-shot of Gate-level Simulation.

Krypton board*:
5
 Map the logic circuit to the Krypton board and attach the images of the pin assignment and output
observed on the board (switches/LEDs).

Observations*:
You must summarize your observations, either in words, using figures and/or tables.
1100100001 00000100 Success
1100100010 00000100 Success
1100100011 00000100 Success
1100100100 00000100 Success
1100100101 00000100 Success
1100100110 00000100 Success
1100100111 00000100 Success
1100101000 00000100 Success
1100101001 00000100 Success
1100101010 00000100 Success
1100101011 00000100 Success
1100101100 00000100 Success
1100101101 00000100 Success
1100101110 00000100 Success
1100101111 00000100 Success
1100110000 00000110 Success
1100111111 00000110 Success
1101000000 00001000 Success

References:
You may include the references if any.

* To be submitted after the tutorial on ”Using Krypton.