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NCL30086BH Analog/Digital Dimmable Power Factor Corrected Quasi-Resonant Primary Side Current-Mode Controller For LED Lighting
NCL30086BH Analog/Digital Dimmable Power Factor Corrected Quasi-Resonant Primary Side Current-Mode Controller For LED Lighting
Analog/Digital Dimmable
Power Factor Corrected
Quasi-Resonant Primary
Side Current-Mode
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Controller for LED Lighting
The NCL30086BH is a controller targeting isolated and
non−isolated “smart−dimmable” constant−current LED drivers.
Designed to support flyback, buck−boost, and SEPIC topologies, its SOIC−10
proprietary current−control algorithm provides near−unity power CASE 751BQ
factor and tightly regulates a constant LED current from the primary
side, thus eliminating the need for a secondary−side feedback circuitry MARKING DIAGRAM
or an optocoupler.
Housed in the SOIC10 which has the same body size as a standard
SOIC8, the NCL30086BH is specifically intended for very compact L30086BH
ALYW
space−efficient designs. The device is highly integrated with a G
minimum number of external components. A robust suite of safety
protections is built in to simplify the design. To ensure reliable
operation at elevated temperatures, a user configurable current L30086BH = Specific Device Code
foldback circuit is also provided. In addition, it supports analog and A = Assembly Location
PWM dimming with a dedicated dimming input intended to control L = Wafer Lot
the average LED current. Y = Year
Pin−to−pin compatible to the NCL30086, the NCL30086BH W = Work Week
G = Pb-Free Package
provides the same benefits with in addition, an increased resolution of
the digital current−control algorithm for a 75% reduction in the LED
PIN CONNECTIONS
current quantization ripple.
DIM 1 NC
Features ZCD VCC
• Quasi−resonant Peak Current−mode Control Operation VS DRV
• Valley Lockout Optimizes Efficiency over the Line/Load Range COMP GND
• Constant Current Control with Primary Side Feedback SD CS
• Tight LED Constant Current Regulation of ±2% Typical (Top View)
• Power Factor Correction
• Analog or PWM dimming ORDERING INFORMATION
See detailed ordering and shipping information in the package
• Line Feedforward for Enhanced Regulation Accuracy dimensions section on page 29 of this data sheet.
• Low Start−up Current (10 mA typ.)
• Wide Vcc Range
• 300 mA / 500 mA Totem Pole Driver with 12 V Gate ♦ Current Sense (CS) Short Detection
Clamp ♦ User programmable NTC Based Thermal Foldback
• Robust Protection Features ♦ Thermal Shutdown
.
Aux
. .
VDIM NCL30086BH
1 10
2 9
3 8
4 7
5 6
Rsense
.
Aux
VDIM NCL30086BH
1 10
2 9
3 8
4 7
5 6
Rsense
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NCL30086BH
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NCL30086BH
Enable V DD V REF
STOP
Over Voltage Protection
(Auto−recovery or Latched) Aux_SCP OFF
VCC
Fault UVLO
VCC Management
Management
Over Temp. Protection Latch
(Auto−recovery or Latched)
Internal
Thermal VCC_max VCC Over Voltage
SD
Thermal Shutdown Protection
Foldback V TF WOD_SCP
BO_NOK
DRV FF_mode
V VS
VCC
Zero Crossing Detection Logic FF_mode
Aux_SCP
ZCD (ZCD Blanking, Time−Out, ...)
Valley Selection Clamp
Circuit
Aux. Winding Short Circuit Prot. Frequency Foldback
DRV
S
Q
CS_ok
V VS Q
Line R
DIM_disable
feed−forward STOP VVS V REFX
GND
CS Leading Power Factor and CS_reset
Edge Constant−Current Maximum
Blanking Control on time
Ipkmax STOP
DIM_disable
t on,max
COMP
V DIM
REFX
Winding and Dimming
WOD_SCP control
Output diode
Short Circuit
Protection
VTF
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NCL30086BH
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V,
VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V)
Description Test Condition Symbol Min Typ Max Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage V
Startup Threshold VCC rising VCC(on) 16.0 18.0 20.0
Minimum Operating Voltage VCC rising VCC(off) 8.2 8.8 9.4
Hysteresis VCC(on) – VCC(off) VCC falling VCC(HYS) 8 − −
Internal logic reset VCC(reset) 4 5 6
VCC Over Voltage Protection Threshold VCC(OVP) 25.5 26.8 28.5 V
VCC(off) noise filter tVCC(off) − 5 − ms
VCC(reset) noise filter tVCC(reset) − 20 −
Startup current ICC(start) − 13 30 mA
Startup current in fault mode ICC(Fault) 58 75 mA
Supply Current mA
Device Disabled/Fault VCC > VCC(off) ICC1 0.8 1.0 1.2
Device Enabled/No output load on DRV pin Fsw = 65 kHz ICC2 – 2.6 4.0
Device Switching CDRV = 470 pF, Fsw = 65 kHz ICC3 − 3.0 4.5
CURRENT SENSE
Maximum Internal current limit VILIM 0.95 1.00 1.05 V
Leading Edge Blanking Duration for VILIM tLEB 240 300 360 ns
Propagation delay from current detection to gate tILIM − 100 150 ns
off−state
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30086BH
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V,
VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V)
Description Test Condition Symbol Min Typ Max Unit
CURRENT SENSE
Maximum on−time ton(MAX) 26 36 46 ms
Threshold for immediate fault protection activation VCS(stop) 1.35 1.50 1.65 V
Leading Edge Blanking Duration for VCS(stop) tBCS − 150 − ns
Current source for CS to GND short detection ICS(short) 400 500 600 mA
Current sense threshold for CS to GND short de- VCS rising VCS(low) 30 65 100 mV
tection
GATE DRIVE
Drive Resistance W
DRV Sink RSNK − 13 −
DRV Source RSRC − 30 −
Drive current capability mA
DRV Sink (Note 6) ISNK − 500 −
DRV Source (Note 6) ISRC − 300 −
Rise Time (10% to 90%) CDRV = 470 pF tr – 40 − ns
Fall Time (90% to 10%) CDRV = 470 pF tf – 30 − ns
DRV Low Voltage VCC = VCC(off)+0.2 V VDRV(low) 8 – − V
CDRV = 470 pF, RDRV = 33 kW
DRV High Voltage VCC = VCC(MAX) VDRV(high) 10 12 14 V
CDRV = 470 pF, RDRV = 33 kW
ZERO VOLTAGE DETECTION CIRCUIT
Upper ZCD threshold voltage VZCD rising VZCD(rising) − 90 150 mV
Lower ZCD threshold voltage VZCD falling VZCD(falling) 35 55 − mV
ZCD hysteresis VZCD(HYS) 15 − − mV
Propagation Delay from valley detection to DRV VZCD falling TDEM − 100 300 ns
high
Blanking delay after on−time VREFX > 30% VREF TZCD(blank1) 1.12 1.50 1.88 ms
Blanking delay at light load VREFX < 25% VREF TZCD(blank2) 0.56 0.75 0.94 ms
Timeout after last DEMAG transition TTIMO 5.0 6.5 8.0 ms
Pulling−down resistor VZCD = VZCD(falling) RZCD(PD) − 200 − kW
CONSTANT CURRENT AND POWER FACTOR CONTROL
Reference Voltage at TJ = 25°C VREF 245 250 255 mV
Reference Voltage TJ = 25°C to 100°C VREF 242.5 250.0 257.5 mV
Reference Voltage TJ = −40°C to 125°C VREF 240 250 260 mV
Current sense lower threshold VCS falling VCS(low) 20 50 100 mV
Vcontrol to current setpoint division ratio Vratio − 4 − −
Error amplifier gain VREFX = VREF GEA 40 50 60 mS
Error amplifier current capability VREFX = VREF (no dimming) IEA ±60 mA
VREFX = 25%* VREF ±240
COMP Pin Start−up Current Source COMP pin grounded IEA_STUP 140 mA
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30086BH
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V,
VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V)
Description Test Condition Symbol Min Typ Max Unit
LINE FEED FORWARD
VVS to ICS(offset) conversion ratio KLFF 18 20 22 mS
Line feed−forward current on CS pin DRV high, VVS = 2 V IFF 35 40 45 mA
Offset current maximum value Ioffset(MAX) 80 100 120 mA
VALLEY LOCKOUT SECTION
Threshold for high− line range (HL) detection VVS rising VHL 2.28 2.40 2.52 V
Threshold for low−line range (LL) detection VVS falling VLL 2.18 2.30 2.42 V
Blanking time for line range detection tHL(blank) 15 25 35 ms
FREQUENCY FOLDBACK
Minimum additional dead time in frequency fold- tFF1LL 1.4 2.0 2.6 ms
back mode
Fault detection level for OTP (Note 7) VSD falling VOTP(off) 0.47 0.50 0.53 V
SD pin level for operation recovery after an OTP VSD rising VOTP(on) 0.66 0.70 0.74 V
detection
OTP blanking time when circuit starts operating tOTP(start) 250 370 ms
(Note 8)
SD pin voltage where thermal fold−back starts VTF(start) 0.94 1.00 1.06 V
(VREF is decreased)
SD pin voltage at which thermal fold−back stops VTF(stop) 0.64 0.69 0.74 V
(VREF is clamped to VREF50)
VTF(start) over IOTP(REF) ratio (Note 7) TJ = +25°C to +125°C RTF(start) 10.8 11.7 12.6 kW
VTF(stop) over IOTP(REF) ratio (Note 7) TJ = +25°C to +125°C RTF(stop) 7.4 8.1 8.8 kW
VOTP(off) over IOTP(REF) ratio (Note 7) TJ = +25°C to +125°C ROTP(off) 5.4 5.9 6.4 kW
VOTP(on) over IOTP(REF) ratio (Note 7) TJ = +25°C to +125°C ROTP(on) 7.5 8.1 8.7 kW
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30086BH
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V,
VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V)
Description Test Condition Symbol Min Typ Max Unit
FAULT PROTECTION
VREFX @ VSD = 600 mV (as percentage of VREF) SD pin falling (no OTP VREF(50) 40 50 60 %
detection)
BROWN−OUT
Brown−Out ON level (IC start pulsing) VS rising VBO(on) 0.95 1.00 1.05 V
Brown−Out OFF level (IC shuts down) VS falling VBO(off) 0.85 0.90 0.95 V
BO comparators delay tBO(delay) 30 ms
Brown−Out blanking time tBO(blank) 15 25 35 ms
VS pin Pulling−down Current VS = VBO(on) IBO(bias) 50 250 450 nA
DIMMING SECTION
DIM pin voltage for zero output current VDIM falling VDIM0 0.66 0.70 0.74 V
(OFF voltage)
DIM pin voltage for maximum output current VDIM rising VDIM100 − 2.45 2.60 V
(VREFX = VREF)
DIM pin voltage for 50% output current VDIM rising or falling VDIM50 1.35 1.57 1.75 V
(VREFX = 125 mV)
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NCL30086BH
TYPICAL CHARACTERISTICS
20.0 9.4
9.3
19.5
9.2
19.0 9.1
9.0
18.5
VCC(on) (V)
VCC(off) (V)
8.9
18.0 8.8
8.7
17.5
8.6
17.0 8.5
8.4
16.5
8.3
16.0 8.2
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 4. VCC Start−up Threshold vs. Figure 5. VCC Minimum Operating Voltage vs.
Temperature Temperature
11.5 6.0
11.0 5.8
5.6
10.5
5.4
VCC(reset) (V)
VCC(hys) (V)
10.0 5.2
9.5 5.0
9.0 4.8
4.6
8.5
4.4
8.0 4.2
7.5 4.0
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Hysteresis (VCC(on) − VCC(off)) vs. Figure 7. VCC(reset) vs. Temperature
Temperature
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NCL30086BH
TYPICAL CHARACTERISTICS
28.0 40
27.8
35
27.6
27.4 30
27.2
ICC(start) (mA)
VCC(ovp) (V)
25
27.0
26.8 20
26.6
15
26.4
26.2 10
26.0
5
25.8
25.6 0
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 8. VCC Over Voltage Protection Figure 9. Start−up Current vs. Temperature
Threshold vs. Temperature
150 2.0
1.8
125
1.6
100
ICC(sfault) (mA)
1.4
ICC1 (mA)
75 1.2
1.0
50
0.8
25
0.6
0 0.4
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Start−up Current in Fault Mode vs. Figure 11. ICC1 vs. Temperature
Temperature
3.8 5.0
3.6
4.5
3.4
3.2 4.0
3.0
2.8 3.5
ICC2 (mA)
ICC3 (mA)
2.6
3.0
2.4
2.2 2.5
2.0
1.8 2.0
1.6 1.5
1.4
1.2 1.0
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 12. ICC2 vs. Temperature Figure 13. ICC3 vs. Temperature
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NCL30086BH
TYPICAL CHARACTERISTICS
1.05 400
1.04 380
1.03 360
1.02 340
1.01 320
TLEB (ns)
VILIM (V)
1.00 300
0.99 280
0.98 260
0.97 240
0.96 220
0.95 200
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 14. Maximum Internal Current Limit vs. Figure 15. Leading Edge Blanking vs.
Temperature Temperature
150 50
140
48
130
120 46
110
44
100
TON(max) (ms)
90 42
TILIM (ns)
80
40
70
60 38
50
36
40
30 34
20
10 32
0 30
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 16. Current Limit Propagation Delay vs. Figure 17. Maximum On−time vs. Temperature
Temperature
1.60 220
1.58 210
1.56 200
1.54 190
180
VCS(stop) (V)
1.52
TBCS (ns)
170
1.50
160
1.48
150
1.46
140
1.44 130
1.42 120
1.40 110
1.38 100
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 18. VCS(stop) vs. Temperature Figure 19. Leading Edge Blanking Duration for
VCS(stop) vs. Temperature
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NCL30086BH
TYPICAL CHARACTERISTICS
600 100
580 90
560
80
540
VCS(low) (mV)
ICS(short) (mA)
520 70
500 60
480 50
460
40
440
420 30
400 20
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 20. ICS(short) vs. Temperature Figure 21. VCS(low), VCS Rising vs.
Temperature
20 40
38
18
36
16 34
32
14
30
12 28
RSRC (W)
RSNK (W)
26
10
24
8 22
20
6
18
4 16
14
2 12
0 10
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 22. Sink Gate Drive Resistance vs. Figure 23. Source Gate Drive Resistance vs.
Temperature Temperature
50 50
45 45
40 40
35 35
30 30
tF (ns)
tr (ns)
25 25
20 20
15 15
10 10
5 5
0 0
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 24. Gate Drive Rise Time vs. Figure 25. Gate Drive Fall Time
Temperature (CDRV = 470 pF) vs. Temperature
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NCL30086BH
TYPICAL CHARACTERISTICS
9.8 15.0
9.6 14.5
14.0
9.4
13.5
VDRV(high) (V)
VDRV(low) (V)
9.2 13.0
9.0 12.5
8.8 12.0
11.5
8.6
11.0
8.4 10.5
8.2 10.0
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 26. DRV Low Voltage vs. Temperature Figure 27. DRV High Voltage vs. Temperature
150 80
140 75
130
70
120
65
VZCD(falling) (mV)
VZCD(rising) (mV)
110
100 60
90 55
80 50
70
45
60
40
50
40 35
30 30
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 28. Upper ZCD Threshold Voltage vs. Figure 29. Lower ZCD Threshold vs.
Temperature Temperature
50 2.0
45 1.9
40 1.8
35 1.7
VZCD(HYS) (mV)
tZCD(blank1) (ms)
30 1.6
25 1.5
20 1.4
15 1.3
10 1.2
5 1.1
0 1.0
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 30. ZCD Hysteresis vs. Temperature Figure 31. ZCD Blanking Delay vs.
Temperature
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NCL30086BH
TYPICAL CHARACTERISTICS
7.8 256
7.6 255
254
7.4
253
7.2
252
VREF (mV)
TTIMO (ms)
7.0 251
6.8 250
6.6 249
248
6.4
247
6.2
246
6.0 245
5.8 244
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 32. ZCD Time−out vs. Temperature Figure 33. Reference Voltage vs. Temperature
110 60
100 58
90 56
80
54
VCS(low) (mV)
70
GEA (mS)
52
60
50
50
48
40
30 46
20 44
10 42
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 34. Current Sense Lower Threshold Figure 35. Error Amplifier Trans−conductance
(VCS Falling) vs. Temperature Gain vs. Temperature
22.0 44
21.5 43
21.0 42
20.5 41
KLFF (mS)
IFF (mA)
20.0 40
19.5 39
19.0 38
18.5 37
18.0 36
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 36. Feedforward VVS to ICS(offset) Figure 37. Line Feedforward Current on CS
Conversion Ratio vs. Temperature Pin (@ VVS = 2 V) vs. Temperature
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NCL30086BH
TYPICAL CHARACTERISTICS
120 2.55
115
2.50
110
Ioffset(MAX) (mA)
2.45
105
VHL (V)
100 2.40
95
2.35
90
2.30
85
80 2.25
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 38. Ioffset(MAX) vs. Temperature Figure 39. Threshold for High−line Range
Detection vs. Temperature
2.60 40
2.55 38
36
2.50
34
THL(blank) (ms)
2.45 32
VLL (V)
2.40 30
2.35 28
26
2.30
24
2.25 22
2.20 20
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 40. Threshold for Low−line Range Figure 41. Blanking Time for Low−line Range
Detection vs. Temperature Detection vs. Temperature
1.20 115
1.15 110
1.10 105
VZCD(short) (V)
1.05 100
tOVLD (ms)
1.00 95
0.95 90
0.90 85
0.85 80
0.80 75
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 42. Threshold Voltage for Output Short Figure 43. Short Circuit Detection Timer vs.
Circuit Detection vs. Temperature Temperature
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NCL30086BH
TYPICAL CHARACTERISTICS
5.00 2.20
2.10
4.75
2.00
4.50 1.90
RSD(clamp) (kW)
1.80
4.25
Trecovery (s)
1.70
4.00 1.60
1.50
3.75
1.40
3.50 1.30
1.20
3.25
1.10
3.00 1.00
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 44. Auto−recovery Timer Duration vs. Figure 45. SD Pin Clamp Series Resistor vs.
Temperature Temperature
1.60 2.58
1.55 2.56
1.50 2.54
1.45
2.52
VSD(clamp) (V)
1.40
VOVP (V)
2.50
1.35
2.48
1.30
2.46
1.25
1.20 2.44
1.15 2.42
1.10 2.40
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 46. SD Pin Clamp Voltage vs. Figure 47. SD Pin OVP Threshold Voltage vs.
Temperature Temperature
38 91
90
36
89
34 88
87
IOTP(REF) (mA)
TSD(delay) (ms)
32
86
30 85
84
28
83
26 82
81
24
80
22 79
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 48. TSD(delay) vs. Temperature Figure 49. IOTP(REF) vs. Temperature
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NCL30086BH
TYPICAL CHARACTERISTICS
12.5 8.8
12.4 8.7
12.3
8.6
12.2
12.1 8.5
12.0 8.4
RTF(start) (kW)
RTF(stop) (kW)
11.9 8.3
11.8
8.2
11.7
11.6 8.1
11.5 8.0
11.4 7.9
11.3
7.8
11.2
11.1 7.7
11.0 7.6
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 50. RTF(start) vs. Temperature Figure 51. RTF(stop) vs. Temperature
6.4 8.8
6.3 8.7
8.6
6.2
8.5
6.1
8.4
ROTP(on) (kW)
ROTP(off) (kW)
6.0 8.3
5.9 8.2
5.8 8.1
8.0
5.7
7.9
5.6
7.8
5.5 7.7
5.4 7.6
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 52. ROTP(off) vs. Temperature Figure 53. ROTP(on) vs. Temperature
55 1.05
54 1.04
53 1.03
52 1.02
VREF(50) (%)
VBO(on) (V)
51 1.01
50 1.00
49 0.99
48 0.98
47 0.97
46 0.96
45 0.95
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 54. Ratio VREF(50) over VREF vs. Figure 55. Brown−out ON Level vs.
Temperature Temperature
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17
NCL30086BH
TYPICAL CHARACTERISTICS
0.95 35
34
0.94
33
0.93 32
31
0.92
30
tBO(blank) (ms)
VBO(off) (V)
0.91 29
28
0.90
27
0.89 26
25
0.88
24
0.87 23
22
0.86
21
0.85 20
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 56. Brown−out OFF Level vs. Figure 57. Brown−out Blanking Time vs.
Temperature Temperature
500
450
400
350
IBO(bias) (nA)
300
250
200
150
100
50
0
−50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 58. VS Pin Pulling−down Current vs.
Temperature
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18
NCL30086BH
Application Information
The NCL30086BH is a driver for power−factor corrected and second temperature thresholds depend on the
flyback and non−isolated buck−boost/ SEPIC converters. It NTC connected to the circuit SD pin. The SD pin
implements a current−mode, quasi−resonant architecture can also be used to shutdown the device by pulling
including valley lockout and frequency fold−back this pin below the VOTP(off) min level. A Zener
capabilities for maintaining high−efficiency performance diode can also be used to pull−up the pin and stop
over a wide load range. A proprietary circuitry ensures both the controller for adjustable OVP protection. When
accurate regulation of the output current (without the need triggered, both protections lead the controller to stop
for a secondary−side feedback) and near−unity power factor operating for the 4−s auto−recovery time.
correction. The circuit contains a suite of powerful ♦ Cycle−by−cycle peak current limit: when the
protections to ensure a robust LED driver design without the current sense voltage exceeds the internal threshold
need of extra external components or overdesign VILIM, the MOSFET is immediately turned off.
• Quasi−Resonance Current−Mode Operation: ♦ Winding or Output Diode Short−Circuit
implementing quasi−resonance operation in peak Protection: an additional comparator senses the CS
current−mode control, the NCL30086BH optimizes the signal and stops the controller for the 4−s
efficiency by turning on the MOSFET when its auto−recovery time if it exceeds 150% x VILIM for
drain−source voltage is minimal (valley). In light−load 4 consecutive cycles. This feature can protect the
conditions, the circuit changes valleys to reduce the converter if a winding is shorted or if the output
switching losses. For a stable operation, the valley at diode is shorted or simply if the transformer
which the MOSFET switches on remains locked until saturates.
the input voltage or the output current set−point ♦ Output Short−circuit protection: if the ZCD pin
significantly changes. voltage remains low for a 90−ms time interval, the
• Primary−Side Constant−Current Control with controller detects that the output or the ZCD pin is
Power Factor Correction: a proprietary circuitry grounded and hence, stops operation for the 4−s
allows the LED driver to achieve both near−unity auto−recovery time.
power factor correction and accurate regulation of the ♦ Open LED protection: if the VCC pin voltage
output current without requiring any secondary−side exceeds the OVP threshold, the controller shuts
feedback (no optocoupler needed). A power factor as down and waits 4 seconds before restarting
high as 0.99 and an output current deviation below ±2% switching operation.
are typically obtained. ♦ Floating or Short Pin Detection: NCL30086BH
• Linear or PWM dimming: the DIM pin allows protections aid in pass safety tests. For instance, the
implementing both analog and PWM dimming. circuit stops operating when the CS pin is grounded
or open.
• Main protection features:
♦ Over Temperature Thermal Fold−back/ Power Factor and Constant Current Control
Shutdown/Over Voltage Protection: the The NCL30086BH embeds an analog/digital block to
NCL30086BH features a gradual current foldback to control the power factor and regulate the output current by
protect the driver from excessive temperature down monitoring the ZCD, VS and CS pin voltages (signals ZCD,
to 50% of the programmed current. If the VS and VCS of Figure 59). This circuitry generates the
temperature continues to rise after this point to a current setpoint (VCONTROL/4) and compares it to the
second level, the controller stops operating. This current sense signal (VCS) to dictate the MOSFET turning
mode would only be expected to be reached under off event when VCS exceeds VCONTROL/4.
normal conditions if there is a severe fault. The first
COMP
DIM_disable
C1
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19
NCL30086BH
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20
NCL30086BH
VCC(on)
VCC
VCC(off)
(‧‧‧ ) (‧‧‧ )
AUX_SCPtrips time
as t 1 + t2 + t3 = tOVLD
DRV (tOVLD ^90 ms)
t1 t3 t1 t3 time
t2 t2
trecovery (^4 s ) trecovery (^4 s )
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21
NCL30086BH
t ZCD(blank1)
t ZCD(blank)
FF_mode
t ZCD(blank2)
ZCD
+
V ZCD(TH)
− Clock
Time−Out
+
V ZCD(short) +
−
−
S
Aux_SCP
Q
Q
90−ms Timer
R
4−s Auto−Recovery Timer
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22
NCL30086BH
If the ZCD pin or the auxiliary winding happen to be • After the appropriate number of “clock” pulses in
shorted, the time−out function would normally make the thermal foldback or dimming mode
controller keep switching and hence lead to improper LED
For an optimal operation, the maximum ZCD level
current value. The “AUX_SCP” protection prevents such a
should be maintained below 5 V to stay safely below the
stressful operation: a secondary timer starts counting that is
built in clamping voltage of the pin.
only reset when the ZCD voltage exceeds the VZCD(short)
threshold (1 V typically). If this timer reaches 90 ms (no Line Range Detection
ZCD voltage pulse having exceeded VZCD(short) for this time As sketched in Figure 62, this circuit detects the low−line
period), the controller detects a fault and stops operation for range if the VS pin remains below the VLL threshold (2.3 V
4 seconds. typical) for more than the 25−ms blanking time. High−line
The “clock” shown in Figure 61 is used by the “valley is detected as soon as the VS pin voltage exceeds VHL (2.4 V
selection frequency foldback” circuitry of the block diagram typical). These levels roughly correspond to 184−V rms and
(Figure 3), to generate the next DRV pulse (if no fault 192−V rms line voltages if the external resistors divider
prevents it): applied to the VS pin is designed to provide a 1−V peak value
• Immediately when the clock occurs in QR mode at low at 80 V rms.
line or valley 2 at high line (full load)
In the low−line range, conduction losses are generally efficiency over the line range by turning on the MOSFET at
dominant. Adding a dead−time would further increase these the first valley in low−line conditions and at the second
losses. Hence, only a short dead−time is necessary to reach valley in the high−line case. This is illustrated by Figure 63
the MOSFET valley. In high−line conditions, switching that sketches the MOSFET Drain−Source voltage in both
losses generally are the most critical. It is thus efficient to cases. In the event that thermal foldback is activated,
skip one valley to lower the switching frequency. Hence, additional valleys can be skipped as the power is reduced.
under normal operation, the NCL30086BH optimizes the
Figure 63. Full−load Operation − Quasi−resonant Mode in low line (left), turn on at valley 2 when in high line
(right)
Line Feedforward
To compensate for current regulation errors due to AC line current. By adding an external resistor in series between the
variation, the NCL30086BH includes a method to add line sense resistor and the CS pin, a voltage offset proportional
feedforward adjustment. As illustrated by Figure 64, the to the input voltage is added to the CS signal for the
input voltage is sensed by the VS pin and converted into a MOSFET on−time.
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23
NCL30086BH
Bulk rail
vDD
VS
I CS(offset) CS RCS
Rsense
Q_drv
In Figure 64, Q_drv designates the output of the PWM latch which is high for the on−time and low otherwise.
VDIM
VDIM100
VDIM0
time
Iout
Iout,nom
0A
time
Figure 65. Pin DIM Chronograms
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24
NCL30086BH
Notes:
• The current does not immediately reach its new target • If either the high−state (VDIM(high)) or low−state level
value when the PWM dimming signal state changes due (VDIM(low)) of the input or both are between VDIM0 and
to system time constants like the time necessary to VDIM100, the output current will be proportionally
charge or discharge the output capacitor to the required reduced as both analog and PWM dimming are
level. The output current settling time can hence affect simultaneous active, thus the output current will be:
the obtained output current, particularly if the PWM
signal frequency is high.
V DIM(high) * V DIM0
I out ^ d @ I out,nom if V DIM0 v V DIM(high) v V DIM100 and V DIM(low) v V DIM0
V DIM100 * V DIM0
I out ^ ǒ d)
V DIM(low) * V DIM0
V DIM100 * V DIM0
(1 * d) Ǔ I out,nom if V DIM(high) w V DIM100 and V DIM0 v V DIM(low) v V DIM100
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25
NCL30086BH
Q DRV
CS R
LEB1 +
PWMreset
+ STOP
Ipkmax
−
UVLO
V ILIMIT BONOK
TSD
SD Pin OVP
(OVP2)
LEB2 +
WOD_SCP 4−pulse
counter
−
OTP
S
OFF
VCS(stop) AUX_SCP Q
VCC(ovp) Q
Figure 66. Winding Short Circuit Protection, Max. Peak Current Limit Circuits
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26
NCL30086BH
Vdd
I OTP(REF)
SD Pin OVP (OVP2) DETECTION
VCC
−
V OVP
T SD(delay)
DZ
SD
S
Q OFF
OTP DETECTION
Q
−
NTC
+
R
T OTP(start)
V OTP(off) / V OTP(on)
4−s
auto−recovery
Timer
V TF
Thermal
Foldback
Rclamp
Clamp
Vclamp
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27
NCL30086BH
ǒ V OVP * V clamp
R clamp
Ǔ
that is
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28
NCL30086BH
ORDERING INFORMATION
Device Package Type Shipping
NCL30086BHDR2G SOIC−8 2500 / Tape & Reel
(Pb−Free/Halide Free)
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29
NCL30086BH
PACKAGE DIMENSIONS
SOIC−10 NB
CASE 751BQ
2X
ISSUE A NOTES:
0.10 C A-B 1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D 2. CONTROLLING DIMENSION: MILLIMETERS.
D 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A PROTRUSION. ALLOWABLE PROTRUSION
2X SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
0.10 C A-B F 4. DIMENSIONS D AND E DO NOT INCLUDE
10 6 MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
H E PER SIDE. DIMENSIONS D AND E ARE DE-
TERMINED AT DATUM F.
1
5. DIMENSIONS A AND B ARE TO BE DETERM-
5
L2 A3 INED AT DATUM F.
L SEATING 6. A1 IS DEFINED AS THE VERTICAL DISTANCE
C PLANE FROM THE SEATING PLANE TO THE LOWEST
0.20 C 10X b DETAIL A POINT ON THE PACKAGE BODY.
B
2X 5 TIPS 0.25 M C A-B D MILLIMETERS
DIM MIN MAX
TOP VIEW A 1.25 1.75
A1 0.10 0.25
10X h A3 0.17 0.25
X 45 _ b 0.31 0.51
0.10 C 0.10 C D 4.80 5.00
M E 3.80 4.00
e 1.00 BSC
H 5.80 6.20
h 0.37 REF
A L 0.40 1.27
e DETAIL A
A1 C SEATING L2 0.25 BSC
PLANE M 0_ 8_
SIDE VIEW END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
1.00
10X 0.58
PITCH
6.50
10X 1.18
1
DIMENSION: MILLIMETERS
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
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30