4

Monolithic IC Processes
The monolithic IC is one in which all circuit components are fabricated in a block of siJicon crystal which
is referred to as chip (or die). Interconnections between the components within the chip are made by means of
metallization (an IC processing step). The individual components 6fIC are not separable from the circuit.
The basic IC fabrication steps will be described in the following sections. Some of these steps may be
carried out several times, in different combinations and operating conditions during a complete fabrications
run. Before we go for detailed description, let us briefly explain each of the fabrication steps,
Wafer Preparation. The starting material is very high purity silicon. It is grown as a single crystal ingot
that appears as solid cylinder (steel gray colour) having IO to 30 cm diameter and about I meter length. This
ingot is sliced to produce wafers IO to 30 cm in diameter and 400 to 600 µm thick. These wafers are polished
to a merrier finish using chemical and mechanical polishing techniques.
Oxidation. This refers to silicon reacting with oxygen to form silicon dioxide, SiO 2. -The oxygen used
in the reaction is introduced either as a high-purity gas or as a water vapour. to speed up oxidation. The wafers
are heated to the 1000°C to 1200°C range. By diffusion of the appropriate dopants, pnjunction (diode) and
junction transistors are formed in monolithic form. Diffusion process is also used to form -conductors.
Ion Implantation. This is another method to introduce dopants into.silicon. The process employs an ion
implanter that produces dopants in ion form, accelerates them by an electric field and allows them to strike
the silicon wafer surface. The dopants become embedded in the silicon. This process is used when accurate
contro! of the dopant is essential for _device operation.· · - ·
Chemical Vap~ur Deposition (CVD). It is a process by which gases (or vapours) are chemically reacted,
resulting in the formation of a solid on a substrate. This process is used to deposit SiO2 on a Si-substrate. The
advantage of a CVD layer is that the oxide deposits at a faster rate and at lower temperature.
A special case of CVD is epitaxy. Using this process silicon layer can be deposited on the wafer. Such
epitaxial layer is of crystalline form. Epitaxy takes·place at higher temperature when we compare it with CVD.
Metallimtion. The purpose of metallization is to interconnect the various components of IC (transistors,
diodes, capacitors and resistors) to form the desired circuit. The process involves deposition of aluminium metal
over those surface areas where interconnection is desired. In addition to this, the process is used to produce bonding
pads around the periphery of the chip for the bonding of wire leads from the package to the chip.
Lithography. The IC fabrication requires the selective removal of the SiO2 layer to form openings
(windows) through which dopants may be diffused to produce various circuit components. The lithography
defines the surface geometry of these components. this process is analogous to the lithography of art world.
One of the kinds of lithography is photo lithography. To have high component density for VLSI/ULSI, the
component size should be reduced Photolithography imposes limit in the size reduction process. Therefore
fine line lithographic techniques ar~ employed since they provide high resolution . Fine line lithography
includes following processes: electron-beam lithography, X -ray lithography, and ion-beam lithography.
Packaging. There are several hundreds of finished circuits or chips in a finished silicon wafer. Each chip
9
may contain between IO and l 0 transistors. The chip is of rectangular shape, typically I and IO mm on each
 Integrated ,
78
tricell while still in w Cfrctifi. 79
. . .
ea{h other by dicin afer fonn. Bad .
edge. Each chip contain a co~plete c1rcu~t and is first testede~~~om and the &Ood Ch!Ps
Monolithic IC Processes
to interconnect the pf'
are marked for later identification. The chip~ are then s~parat used k . Id ns of the Pack Chips SiH4 +heat ~ Si + 2H2
(dies) are mounted in packages (headers). Fme gold wires are nd age (solid) (gas)
~ac age •~ _sea e u er vacuurn 10 (gas)
the bonding pads (metallized contact areas) on the die. Finally,dt~e or in an wi~ silane instead of trichlorosilane.
inert atmosphere . A brief description of packaging will be foun m
t e appen ix. In this process the CVD reactor is operated at about 900°C and supplied
harmful reaction byproducts.
The advantages of producing EGS from silane are lower cost and less
4.1. REFINING AND GROWTH OF SILICON CRYSTALS
nd sili~ates. At present, silicon. 1 4.1.2. Crystal Structure and Growing
The most commonly available natural sources of ~ii icon are silica a At the end of refining process we get highly refined silicon (EGS) but
it is still polycrystalline. What we need
already discussed the reasons t made
devices constitute over 95% of all semiconductor devices. We have In t~ section we shall, lherefo~ d_i~~u~s : :
or Using is a single crystal silicon as a starti~g material for fabrication of ICs.
silicon as a suitable material in chapter I. i ~rystal growth_process which is suit~
principle and practice of crystal growth. Present section covers Czochralsk
obtained. The quahty of bulk gro~n crySlals
4. 1.1. Productio n of Electronic Grade Silicon (EGS) for growth of bulk ingot A 150 mm diameter crystal ingot is commonly
~ this difficul~ is ~o use a polished slice
!s -grade silicon (EGS) . is not sufficiently good for direct device fabrication . One way of overcomin
The raw material for the preparation of single-~ry~tal sil!~on the electronic higher grade epitaxial layer for the actual
the EGS are boron, carbon and ~h1ch of bulk grown crystal as a foundation and to grow onto this surface a much
is a polycrystalline material of high purity. The maJor 1mpunt1es m
(ppb) range, and carb~n le residual
donors. Pure EGS should have doping elements in the parts per billion device structures.
docs not represent an ideal crystal due
parts per million (ppm). Production of EGS is a multistep process as
shown in Fig. 4.1 . ss than 2 The silicon wafer, as stated above, must be single crystal, but it
in an arc furnace which is charged with . to following reasons : .
First, a metallurgical-grade silicon (MGS) is produced are incompletely bonded as against those
and wood chips. The overal~Uartz!tc, (i) The wafer has finite boundaries ; th4s, atoms at the surfaces
a relatively pure form of sand (SiO 2), andcarbon in the form of coal, coke, reaction
in the furnace being in the bulk of the wafer material.
(ii) The atoms arc displaced from their ideal locations by
thermal agitation.
SiC + SiO2--- + Si + SiO + CO into four types : (I ) point_defect, (2 ) line defect
(solid) (Solid) (liquid) (gas) (gas) (iii) Real crystals have defects which are mainly classified
. The crystal defects influence the optical.
still not suitable for ma f: . (dislocation), (3) area or planar defect, and (4) volume defect
. The MGS is drawn off and solidified at a purity of 98%. This is nu actunng electrical, and mechanical properties of silicon.
semiconductor devices.
Si(MGS) HCI Point defect refers to following forms of defect :
. Next, the MGS is pulverized mechanically and reacted (i) A nonsilicon atom incorporated into the lattice at either
a s11bstit11tio11al or interstitial site : The
w_11h an~ydrous hydrogen chloride (HCI) lo form and the latter refers to ex isting
former refers to site produced by replacing a parent silicon atom
tnchloros1lane (SiHCl3), according to th.: reaction : l dopant as introduced by
· site between silicon atoms. The nonsilicon atom may be an intentiona
Hydroclorinatlon
Si + 3 HCI--+ SiHCli + Hi ot MGS diffusion process (to be discussed) or an unintentional impurity .
(solid) (gm) (gas) . (ps)
(ii) A vacancy in the lattice created due to missing atom
: this is also known as a Schottky def ect.
The _reaction takes place at a nominal temperature of SiHCl3 silicon atom in an interstitial lattice site with an associatt+l vacancy : this is also known as a
0 (iii) A
300 C usmg _a catal_yst Here silicon tetrachloride (SiC'4) SiCt, Frenkel defect.
and_ the c_hlondes of impurities are formed. At this point the low boiling on temperature . Point defects are
punficauon process occurs. Trichlorosilane is a liquid at Distillatio n Vacancies and interstitials have equilibrium concentrations that depend
of many impurities depends on the vacancy
roothm temperature , because its boiling point is 320c. Also ' Impurities important in the kinetics of diffusion and oxidation. The diffusion
Therefore purification is done bi~~~:::~~~ralure.
o er unwanted chlorides are Ii 'd
. a on.
conce.ntration, as docs the oxidation rate of silicon.
Dislocations form the second class of defects . There may be edge (line)
dislocation or screw dislocatio n.
The purified SiHCh is sub' plane of atoms . Crystals for IC usage are
deposition (CVD). The ~hemic~ected t~ ch~m1cal vapour The edge dislocation in a cubic lattice may be created by an extra
dislocation loops from excess point-defect
reduction of SiHCIJ. reaction 1s hydrogen
a generally grown free of edge dislocations, but may contain small
on of impurities such as oxygen and are
considerations. These defects act as a nuclei for the precipitati
2SiHC13 + 2H2--+ 2Si + 6HCL are generally undesirable, because they
responsible for a swirl pattern seen in wafers. Dislocations in devices
act as sinks for metallic impurities and alter diffusion profiles.
(Jas) (psJ (solid) (gas)
The reaction lakes place . The crystal on either side of the
11oooq in which a . ma CVD reactor (at about Area defects represent a large area discontinuity in the lattice.
Chlc-osila ne SiCt, are twin and grain boundarie s. Twinning
diameter), called a "slim~:::.~ance-hcatcd Si-rod (4 mm discontinuity may be otherwise perfect. Two typical area defects
recovery such that a certain symmetry , such as mirror
for the deposition of silicon ~rvcs as the nucleation point represents a change in the crystal orientation across a twin plane,
) . A grain boundary represents a transition
EGS w~ch are up 10 0_2 m (~r e P~c~s results in rods of image, exists across that plane. In silicon the twin plane is ( 111
H2 one another. Grain boundarie s separate grains
meters m length. EGS can be more)md1ame1erandsevera1 between crystals having no particular orientation relationship to
HCI defects are not used for IC manufacturing.
chunks or crushed into nuggc~.u1 from these rods as single of single crystal in polycrystalline silicon. Crystals having such area
Hydrogen and Precipitates of impurity or dopant atoms constitute the volume defects. Every impurity introduced imo
To achieve high lattice can accept in a solid solution of itself
feedback or recyclin overall _efficiency of the r HCI recovery the lattice has a solubility ; that is, a concentration that the parent
showninFig.4 I Th g ~f reac11onth byproducts is . p OCCss,
and the impurity. If an impurity is introduced (at a temperature 1
T ) at the maximum concentration allowed by
. . . cre1saJso Used as
EGS . then cooled to a lower temperatu re (say T2) , a supersaturated condition is said
in which silanc (Si"4) . ani. crproccssofproduc· its solubility, and the crystal is
IS su ~CCtcd lo py'rolysis. JDg an equilibrium state by precipitati ng the impurity atoms in excess of the solubilit y
to exist. The crystal achieves
HCI phase which is being a material of different compositi on and structure. For example, cxces~
level as a second
Fig. 4.1. Production ofEGS from MGS.
 Integrated C 81
. . . . ircu11i
80 irh silicon and form silicides ':"ithm the parent lattice. Precipitates are &erie Monolithic IC Processes I
:s
metallic impurities can rea~~ sires for dislocation generatJOn. . . .
srals involves a phase change from sohd, hqurd, or gas h
tali}
. . . . for commonly found impurities, and common y
rhe impurity or dopant atoms is below unity • this holds_good _ . t the interface are left in the hqu1d (melt) .
undesirable because rhey a . f used dopants in silicon . Therefore during growth , the u~punues ~ h d with impurity . i.e., extremely sm a ll
Crystal Growing. Grow~~t~ riZih is rhe pr~cess use~ to grow most of the crystals from Whith a~~s to Thus, as the crystal grows, the melt becomes progressively ennc e
81
crysrallinesolidphase. Czf ~!n crystal growth is a hqu1d-soh_d m~no component ~r~wth system. The 1ico0
impurities arc incorporated in the grown crystal. . d" . . th melt Rotation of a crystal
wa fers are produced. The 5 1 be discussed in rhe next section, involves the sohd1fication of at 0 growth
it
of a Czochralski (CZ) crysia
1
speed of rhe growth is determined by the number of sites on the t1s froni a The boundary layer thickness is a function of the convectmn con I iu~;: ~~nv:ction. forced by rotati o n is
in a melt (forced convection) produces a boundary layer. In large ~~ tst .n the crucible. Because the thermal
liquid phase al an m~erfa%1 al :ansfer al the interface. Fig. 4.2 shows the transport process and t ace of the
crystal and the s~c~cs: al ~ransfercondition about the interface can be modelled by the follow· emperature often secondary to the thermal convec~ion caused by temperat~:e !~afl~~7u:~es with time, resulting in a variable
grad1en1s involve . e e dm dT dT mg equation convection is a random proces_s, the thickness of the boundary n:al convection effects is an inhomogeneous
Hdr+<It dxM AM=<I, dxN AN value for boundary layer thickness. The net result of the d . lso a factor in determining the shape
...(4.1) distribution of dopant in the crystal on a microscale. Th~ ~ull ~pee ~s; to ensure the stability of the growth
where His rhe larenl heal of fusi~n , '!'nl
dt is t_he mass_s~lidification rate, Tis the temperature, Cit and
O
a. of the growing interface. A proper choice of these conditions ts nee e
the rherrnal conducrivities of rhe hq_uid and s?hd re~p~uvely, dTI dxM and dT/ dxN are the thennal gradie re process. . . · al ro erties of silicon wafers.
at poinr Mand N which ~e near rhe interface i_n the hqu1d and solid, respectively, and AM and AN are the ar:ls The crystal planes decide the processing characteristics and some maten p pt ·1 on these planes
of rhe isotherms al positions Man~ N ~especuvely._ From Eq. (4.1) the maximum pull rate of a crystal u . as The { 111} planes have the highest density of atoms on the surface, s~ cystal~ gro;.;o~;~~lof elasticity als~
rhe condwon of zero rhermal gradient m the melt, 1.e. , dTI dxM = O can be obtained The . . rider Mechanical properties such as tensile strength are hig~e~t for <11 > irec:wn_~ . e ·milarly orientation
. . • • maximum pull rate show an orientation dependence. Processing characteristics such as therma oxi auon are s i
Pmu.r IS given by de ndent For example { 111 J planes oxidize faster than { JOO} planes, because they hav_e more atoms per
p - ~ g_ unr::su,fa~e area available for the oxidation reaction to occur. Historically. bipolar transistor devices have
,,.,,..- Hd . dx preferred < J 11 > oriented material and MOS devices< I 00>. There are, of course, exceptions. .
...(4.2)
where P.,0 , is the maximum pull rate or pull speed and dis the density of solid silicon. After studying the crystal structure and its principle of growing, we now will study the crystal grow mg
practice.
; 4.1.3. Crystal Growth Apparatus
The highly refined silicon (EGS) though free from impurities, is still ~oly~rystall_ine. Hence it is to be

. No,~ : Posilions Mand N represent the location of isotherms

assoc1a1ed w11h Eq. (4 . 1). Impurity atoms are transported
i
t-
TM
Growth
axis
MELT CLIQUID) processed to become single crystal. The CZ crystal growth process shown m Fig. 4.3 1s the one most often
used for producing single-crystal silicon ingots.
Since monolithic ICs are usually fabricated on a substrate which is doped with impurity , the polycrys-
across rhe boundary layer (BL) and incorporated into the talline silicon with an appropriate amount of dopant is put into a quartz crucible, which is then placed inside
growing crysral interface. a crystal growth ·furnace. The material is then heated to a temperature that is slightly in excess of the silicon
melting point of 1420°C. A small single-crystal rod of silicon called a seed crystal is then dipped into the
silicon melt. The conduction of heat, up the seed crystal, will produce a reduction in the temperature of the
o Impurity atoms melt in contact with the seed crystal to slightly below the silicon melting point. The silicon will , therefore ,
• Silicon atoms freeze onto the end of the seed crystal, and as the seed crystal is slowly pulled up out of the melt it will pull

Fig 4 2 T M N
. . . em~ra!1~re gradients, solidification, and transport phenomen
• 0.
. Distance
up with it a solidified mass of silicon that will be a crystallographic continuation of the seed crystal. Both the
seed crystal and the crucible are rotated but in opposite directions during the crystal pulling process in order
to produce crystalline ingots of circular cross section.
encountered m s1hcon crystal gro th . a If the temperature and pulling rate are correctly chosen, the liquid solid interface remains near to the
The ll . w process. TM 1s the melting point.
pu rate affects the impurities goin into th . surface of the melt and a· long single crystal silicon is pulled from it. The diameter of the ingot is controlled
~enerally,. when the temperature gradient ingthe ~ ~rystal durmg growth and decides the defects generated. by the pulling rate and the melt temperature, with ingot diameters of about 100 to 200mm (4 to 8 inches) being ·
eat of fusion . Therefore, the pull rate eneral me _t is_ small, the heat transferred to the crystal is the latent the most common. The ingot length will generally be of the order of 3 meters, and several hours are required
obtained are 30 to 50% slower than theg . ly varth1es m~ersely with the diameter. In practice the pull rates for _the "pulling" of a complete ingot. The crystal pulling is done in an inert-gas atmosphere (usually argon or
Th maximum eorclJcal values helium), and sometimes a vacuum is used. This is done to prevent oxidation. .
. e growth rate or growth velocit f th . ."
instantaneous solidification rate. We shoul~ o t e crystal I~ very important growth parameter and is the The pull-rate_is closely related to the heat input and losses, crystal properties, anct dimensions. The
r:te. These two rates differ because of tempe:t e ~t pull ~te is the macroscopic indication of net solidification cond_itions f~r · crystal pulling are, therefore, carefully control~ed. For example, the melt temperature is
~ an the pull rate or even be negative at a . u~e uctuatJons near the interface. The growth rate can be more monitored with a thermocouple ~nd fee~back controller. Longer diameter crystals have commercial advantages
1 a~d can be grown. However, d1fficult1es may be encountered because of resistivity gradient across finished
~: ~e c!)' sta l dissolves back into the m:;~e; tim~. _When the gro~th _rate is negative, remelting occurs. That
:i im~na~on ~lso results in more uniformly d~~~e
Slnbution m the crystal on a macroscopic
:::l
~ust be ehmmated to remove crystal defects. This
ry · e growth rate affects the defect structure and dopant
shces.
. Some P~ctical _Aspects of_~rystal Gro~th Apparatus. The crystal growth apparatus in Fig. 4 .3,
E . sea~I
basically_, co~s1sts of(,) furnace, (11) crystal pulling mechanism, (iii) ambient control facility, and (iv) control
very 11i:i~urity has a solid solubility in silicon Th 1· · . system circuitry.
melt. The equ1hbrium segregation coefficient (ratio · f e '!1Pu~ty has a d1ffer~nt e~uilibrium solubility in the
0
, equilibrium concentrations m solid 10 that in liquid) of
 tntegratedc

r
ltt111i.
SZ 'blc suscepwr(crucible support) and rotational mechanism, heatin e '
Thefumaceconsisrs of cruc;hc ~rucible is rhe rn osl important compo~ent o_f the growth appara~
le~ent Monolithic IC Processes 83
r supply and chamber. . sho uld be chen11cally unreac11ve with molten silico
an d powe · crucible marcna 1 .. .
Us, sine
-1 contains ,he mcll. The . oi nl ihcmrnl siab11t1y, and hardness. The materials n. A.ls e
for cruc'b] . o, lhe Effects of Unintentional Impurities on Silicon Crystal Properties
~aierial should have high me/°ng ~iiride (S i1N4 ) and fused silica (SiO2) . The latter is mostly
~ e, Which Oxygen and carbon are the more common undesired impurities incorporal'i:d during.
sa tisfy rhese properiies, ari s'.,'.'~~ releasing ~ilicon and oxygen into the melt. In this process sil!c_on cry_stal
~ed. Fused
silica, however, reacrswi; si ~~vn ·with 1his crucible also contain substantial amounts of intersr/ 1
cru\:ible
growth. Oxygen in silicon arises from the dissolution of the clrUcible during growt'h. Carbon
due to its transportation from the graphite parts in the.furnace to the melt.
1ft s1hcon anses
undergoes erosion. C1si_a / ~rdelrimcnlal, as will be discussed later. Also, the purity of the 11 1
0 silic ~ oxygen
rhar can be eirher bene, ;~~ily. The susceptor, is used to support the silica crucible. It also O As an impurity, oxygen has three effects on silicon crystal : donor formatio11, yield strength
h provida t crufibJe improvement
irse/f affecrsdl e cry~:aphite is the material of choice because of its high-temperat ure properties
rhennal con ,uons. . f h I fi . ..
~ or lletter and defect generation by oxygen precipitation. The donor affects the resistivity of the
ctys't'al. lmp_rovement
should be pure w prevent contaminatron o I e crysla rom 1mpunt1es that would be volatilized . • ne gra h' in yield strength due to oxygen impurity i,s a beneficial effect. A variety of crystal defects
fro p lie oxygen precipitate formation . These defects attract fast-diffusing metallic ~pecies, which
are_as's'ociated with
graphice at rhe temperarure involved. The susccptor rests o_n a pedestal whose shaft is connected ~ive rise to lar~e
a Ill ~e junction leakage currents. The ability of defects to capture harmful impuritids is refemd
thar provides rorarion. The whole ass_embly can usually be ~a1St:d and lowered to keep the melt 10 't'o :-1s 'ge,tt,ering. ~1s
level equ. d~0lor effect can be used beneficially. This will be explained later. Carbon impurity is another
from a fixed reference poinl, which 1s needed for automatic diameter control. 1 istant lin'desiraf>le impurity
which aids in the formation of defects.
The chamber housing the furnace must provide easy access to the furnace compone
· .. After silicon crystal (also called ingots or boules) growth. it is ,..isually weighed, then Inspected
mainrenance and cleaning. The furnace structure must be airtight to prevent contamination 1 10 visually .
fin s facilitate
phere, and ha ve a specific design that does not allow any part of the chamber to becomes 0 Gross crystalline imperfections such as twinning are removed b); cutting. Also, the
h ; ; l~e atrnos. irregularly shaped or
pressure would be a facr?r in contaminating the crystal. Hottest parts of the apparatu~ undersized sections of boule are cut. Total silicon loss can equal 50% at this step. Next
:e twat its vapour the'butt (or \ang) end
Insulatwn 1s usually pro~1ded between the heater and the chamber wall. To melt the char of the ingot (or a sli~e cut from that position) is preferentially e.tr;hed to reveal defects.
·e RFat~r co<_>.led. A common etchant is
hearing or res,srance ~eatm~ are used as slated earlier. RF heating is useful for small melt
heaung is used exclus1vely m large crystal pullers. si; b (md~ction)
s, ut resistance
a one/one mixture of HF acid (49%) and five-molar chromic apd. This etchant is also
processed "'.afers to delineate other types of microdefects or j ,mpurity precipitates. Cracks
used on polished and
can be detect~d
using ultrasonic technique. Resistivity measurements are mad'~ on the flat ends of the crystal
The crystal-pulling mechanism consists of seed shaft or chain, rotation mecha~ism, and by the four-pomt
seed probe method to be described later. 1
mechanism controls two parameters of the growth process . pull rat a d .
• . . . chuck. The
· e n crysta 1 Ir • Boron (p-type)-doped CZ ~ilicon is available in re/ '.stivity from 0.0005 to 50 ohm-cm.
mechanism m_ust h~ve m1_01mum vibration and great prefision. The seed holder androtationII' ·
Also th
' ~ pu ing Arseilic and
0

mamram precise onentatJon perpendicular lo the melt surface. As shown . F phosphorus (n-type)-doped silicon crystal is available in ~ e range 0.005 to 40 ohm-cm.
pu mg mechanism must Arsenic is preferred
furnace through a purge tube where ambient ·r . . in the lower resistivity ranges. Antimony is also used in O.<f, l ohm-cm range. This dopant
In ig. 4 .3, the crystal leaves the is suitable for growing
it. From the purge tube, the ~rystal enters an ~:C:r ~~:::; is d~~e~t~d alonf the surface of the epitaxial substrates.
crystal to cool I
an isolation valve. r, w IC IS usua ly separated from the furnace by 4.2. SILICON-WA FER PREPARATION
I
The ambient control for !,he crystal ...------ --1 s~~~ ;~aft, 4.2.1. Ingot Trimming and Slicing
growth apparatus consists of gas source rotation Once the crystal ingot is obtained using above r,rocess, the extreme top and bottom
flow control, purge tube, and exhaust o; portions of the ingot are cut off and the ingot surfact\ is ground to produce a constant and
vacuum system. The crystal growth must Sensor for exact diameter which may be 100, 150, or 300 mm. A crystallographi c orientation flat
be conducted in an inert gas or vacuum diameter control Upper housing is also ground along the length of the ingot. The ingot is then sliced using a large-diameter
!s
This necessary because (i) the ho~ stainless steel saw blade with industrial diamonds embedded into the inner-diameter flat
graphlle parts must be protected from cutting edge. This will pr9(iuce circular slices 1or wafers that are about 600 to 1000 µm Fig. 4.4. A Silicon
oxygen to prevent erosion and (ii) the gas thick, as shown in Fig. 4.4. The orientation flat serves as a useful reference plane for wafer. Typical
around the process should not react with the various device processes. Correct orientation of the surface of the wafers with respect values of Dare 100,
to
the crystal planes is important for successful epitaxial layer growth, a process step to 150 or 300 mm.
molten silicon. Growth in vacuum meets be
11-- - - + - Seed shaft 8, chuck discussed later.
these requirements. Growth in a gaseous
atmosphere, generally used on large Furnace chamber 4.2.2. Wafer Polishing and Cleaning
gro_wers, must use an inert gas such as Ill ~·-:c;m-1>--il't- -t- Melt While slicing the wafer, its surface is heavily damaged. Therefore, the wafers undergo
-t---f'it--.u_;;~ ~~H--r:1--11- - Crud ble
a number of
helium or argon. The inert gas may be at polishing steps for the following reasons :
/ ,..atmospheric pressure or at reduced pres- (i) To remove the damaged silicon from the sawn surface.
. sure. _,,
(ii) To produce a highly planar or flat surface that will be required for the photolithogrJ{
6rc process
. The control system for crystal grow- -.+ To vacuum pump especially when fine-line geometries are involved. It ··
ing may consist of microprocesso r, sensors, (iii) To improve the parallel.
a nd0 utputsandprov idescontrolof process .___ _ _........:....J and Hft As discussed above, the sliced wafer is 0.6 to l mm thick. This is quite rough. Hence
parameters such as tern r t F' it is to be lapped
d' . .. to remove saw marks and to produce a flat surface. The raw wafer may have a surface
pc_ a ure, crystal
iameter, pull rate and rotation speed ig. 4 .3. A practical s1hcon crystal growing apparatus. damage (including
The u . microcracks) of the order of 75 µm. After lappin~, still the~e ex_ists a surfa~e ~amage_to_
because these rely less on operato . ~ ~e of microprocesso r-based systems for control is more common µm . It is removed with a chemical etch employing an acid mixture cons1stmg of n1tnc
a de~th of ru:o~nd 15
rm ervent1on and have many parts of the process preprog rammed. acid to ox1d1ze the
surface and hydrofluoric acid to dissolve the oxide .
r simultaneous with the final polishing stage.
. . .
The wafer is then polished mechanically on a wheel to mirror hkc finish, using alum · .
Integrated , ,
~~ ,

e sornetirnes ~:
~
powders of decreasing grit size (down to a final l µm diameter). There still exits a surface da iniurn abrasj , '
2 µm deep. Finally ii is removed by an additional chemical etching stage, which can b mage of arou Ve
Monolithic IC Processes "'
85

poli shing, the polysilicon is resident on the rear surface. The grain boundaries in the polysilicon readil ~ etain
process-induced IT)etallic contamination.
Thermal Stress Minimization. We want that the silicon wafer .should remain crystalline and should ~t
\

deform as ii undergoes various fabrication process steps. In practice wafers experience thermal stresses as t~ey'\
Usually, only one side of the wafer is given the final mirror smooth highly polished fin· h . are subjected 10 high-temperature furnace . If these stresses exceed the yield _strength of the material,
(i.e. the back side) bei ng given just a lappi ng operation to ensure an acceptable degr is ' th e Other Sid
dislocations in wafer will form . To minimize the thermal stresses, wafers are withdrawn slowly from the
parallelism. After the wafer polishing operations arc completed, the wafers arc thorough I e; of flatness a e
furnace . This minimizes the temperature gradient. Alternatively, furnace temperature may be l~"."ered pnor to
and they are now ready to be used for the various processing steps described in the folio ~ c cane~, and·drie~d
removing the wafers . Oxygen in interstitial lattice site acts to increase the yield strength of silicon as_stated
discuss_ing these steps _let us discuss some processing considerations necessary to ma7~n~ sectJons. Bero/ earlier. However this beneficial effect increases with concentration until the oxygen begins to precipitate.
perfecuon of the material. lain the purity an: Therefore, oxygen precipitates used for gettering can have negative effects on the yield strength.
4.2.3. Wafer Processing Considerations
4.3. DIFFUSION OF DOPANT IMPURITIES
. . Chemical Cleaning. As stated above, after polishing, the wafers are thorou hi The process of junction formation, i.e., transition from p ton type or vice versa, is typically acco~plished
s1hcun wafers _are usually cleaned to remove organic films, heavy metals, and par7i--~ ~leaned. Prior to Use by the process of diffusing the appropriate dopant impurities in a high temperature furnace. Impurity atoms
are aq~eous mixtures ofN°H4OH - H2O2, HCI - H2O2 and H2SO4 - H2O2 All of the~ a ~s. Commonly us~ are introduced onto the surface of a silicon wafer and diffuse into the lattice because oftheir'tendency to move
re'.11ovmg me~allic impurities, but the HCI - H2O2 mixture is the best. The.ammoniu~~U~JOn~ are efficient in from regions of high to low concentration. Diffusion of impurity atoll's into silicon crystal takes place only at
alc1d based mixtures will also remove organic contaminants, but the latter is better . tYh_ rox1de and sulfuric elevated temperature, typically IO00 to 1200°C.
c eanmg sequence would b lfu · · ' , in 1s regard A
with de . . ed . e a su . nc acid-hydrogen peroxide clean followed by the hyd fl ' : typical Although these are rather high temperatures, they are still well below the melting point of silicon, which
wnrz_ water nnses following each acid step. ro uqnc acid dip, is at 1420°C, The rate at which the various impurities diffuse into silicon will be of.. the order of 1 µm/hr al a
Gettermg Treatments. Metallic impurities h ·· , temperature ~ange stated above, and the penetration depth that are involved in most.diffusion processes will

II,~::;::i~i:E~~.,~:~;;1:f;:::;~~;~:~~:~;:'.:;i::·f~::.~~~~~~~,:
1
leakage currents) and narrow-base bipolar tr~nJ;1~~ :~~:~:: :~~:~:i:emone~ (w?ic~ requi_re low jun:,}t~
be .of the order of0.lto 30 µm . At room temperature the diffusion process will be so e~tremely slow such that
the impurities can be considered to be essentially "frozen" in place.
A method of pn junction formation which was popular in the early days is the grown.junction technique.
In this method the dopant is abruptly changed in the melt during the process of crystal growth. A convenient
To _remove impurities, as above, "gellerin treatme " . 1
. o con uct1ve impurrty precipitates'. technique for making pn junction is the alloying of a metal containing doping atoms on a semiconductor with
harmful impurities or defects from the re ions fn a w nt is came~ out: Gettering is a process that removes the opposite type of dopant. This is called the alloyed junction technique. The pn junction\using epitaxial
!ettermg treatm~nt provided to silicon wa~ers prior to~~~where ~ev1;es are f~bricated. Pregeuering refers to growth is widely used in ICs. An epitaxial grown junction is a sharp junction. In terms of volume of production,
fi at can ~bsorb impurities as they are introduced during: dro~essing. re~ellenng provides a wafer with sinks the most common technique for forming pn junctions is the impurity diffusion process. This produces diffused
or geuenng treatment as follows : ev1ce processing. There are number of techniques junction. Alongwith diffusion process the use of selective masking to control junction geometry, makes
possible the wide variety of devices available in the form of ICs. Selective diffusion is an important technique
(z) Inte~tionally damaging the back surface of th . . in its controllability, accuracy and versatility.
lapping or sand blasting. e wafer using mechanical abrasion methods, such as,
4.3.1. The Nature oflmpurity Diffusion
(ii) Damage created in wafer using focussed heat . \
laser beam is rastered along the back f; beam obtained from a Q-pulsed, Nd : YA Glaser-The The diffusion of impurities into a solid i.e., solid-state diffusion, is basically the same type of process as

... . .
t?
favourable trapping sites for fast-d "ft: ~ur ace
1 iusmg species create dislocations in the wafer which become occurs when excess carriers are created non-uniformly in a semiconductor which cause carrier gradient. In
( Ill) lntnnszc gettering -An · , each case, the diffusion is a result of random motion, and particles diffuse in the direction of decreasing
. ·
st ted · impur11y oxygen causes d f, • concentration gradient. The random motion of impurity atoms in a solid is, of course, rather limited unless the
a earlier. The defects generated b e ect generation by its precipitation. This was, temperature is high. Thus diffusion of doping impurities into silicon is accomplishe/1 at high temperature.
temperature cycle (over l050oc. N Y_ oxygen precipitation are useful as a trapping sites. High
of the wafer to make it defect-ti in 2) is e~pl~yed to lower the oxygen content near the surface There are mainly two types of physical mechanisms by which the impurities can diffusion into lattice.
cycle d They are : (i) Substitutional diffusion and (ii) Interstitial diffusion.
s are a ded lo promote the ree
fio
zone which 1s u d e d ·
. se •Or ev1ce fabrication. Additional thermal
wafer (h h . nnat1on of oxyge • . . . _
ence I e name intrinsic gett • ) n precipitates and defects m the mtenorofthe Substitutional Diffusion. At high temperature many atoms in the semiconductor move out of their lattice
Intrinsic getterin is v enng . site_, leaving vacancies into which impurity atoms can move. The impurities, thus, move through the lattice by
the bulk of h g ery useful because it fills th I exchanging places with an adjacent vacancy. Thus, substitutional diffusion takes place by replacing the silicon
. fi r e wafer serves no useful functi b e vo ume of the wafer with trapping sites. Otherwise, atoms of parent crystal by impurity atom. (Fig. 4.5.)
is ormed. on eyond mechanically supporting the thin layer where the device
Substitutional diffusion mechanism is applicable to the most common diffusants, such as boron,
All above methods are e . phosphorus, and arsenic. These dopants atoms are too big to fit into the interstices or voids. so the only way
is also fi J · mployed to improve ju r I
later use ~ to im?~ove gate-oxide qualit in MO nc ion eakage currents. However it is found that getrering they can enter the silicon crystal is to substitute for a silicon atom. .',
' metall~c prec1p1tates are fonned ( . ~I SFET and thus to reduce leakage. As it will be discussed
grow~h of rhm oxide layer of MOSFET ~mi_ar to oxygen precipitate) at the wafer surface which disrupt the

'L
technique is lo deposit I µm of poly-s ·1· ev1cefand act as points of localized break down For this a gettering
1 icon, a ler the ch · J • • • Af r
emica etching of the wafer prior 10 polishing. re
 - .. - - ---· · ·····o ~J ~--··· - · - ~sv••·t'•vn•--; ..... "' O'V ......... v .... o••p ... ~• ... ··~ 1.111vu511pul IVI ;)\,,(Ullllll~ ;:,_y;:,ll;;III ·~
roughly inversely proportional to the square of the linewidth. The X-ray lithography with storage ring source
and masked ion-beam lithography are the main candidates for high-volume production of advanced circuits
with dimensions beyond the optical limit.
4.9. ETCHING
In the photolithographic process described in sec. 4.7, we discussed about etching process. There we
discussed oxide etching. This may be referred to as wet etching process because the chemical reagents used
are in liquid fonn. A newer process for oxide etching is a plasma etching. This is also referred to as dry etching.
In fact, etching has number of applications in addition to oxide etching. This section, therefore, is devoted to
this important process, giving more emphasis on dry etching due to its importance in VLSI/ULSI fabrication .
4.9.1. Wet and Dry Etching
Wet Etching. As discussed earlier, wet etching involves dipping the wafer into a liquid bath containing
a chemical that will dissolve only the Si02 material and none of the surrounding material (refer step F 6f sec.
4. 7. l ). The etching chemical must not react with the resist. Fig. 4.32 illustrates undercutting (or overetching),
a problem that has limited the use of wet etching to processes with minimum feature sizes greater than 2 µm.
The undercutting refers to etching Si02 under the resist mask and is caused by etching chemical dissolving
the Si0 2 in both vertical and lateral directions. A measure of the amount of undercutting is called the etch bias,
which is defined as below :
Etch Bias = D1- Dm ... (4.21)
where D1 and Dm are shown in Fig. 4.32 (a).

Lateral Vertical
etching etching
Resist Si02
Si02

Si- wafer
Si-wafer
(a) (b)
Fig. 4.32. Undercutting as a result of wet etching (a) After etching (b) After resist removal.
 118 Integrated Circuits
The we t ctchan ts arc iso tropic and . . . ·n The etching mater ial should
hence give nse to underc ult& g. , therefore
offer etc hing ani sotropy. The deg '
ree of anisotropy AJ is given as
Ai= I - (V1/Vv) ...(4.22)
where V1 is the lateral etch rate and · ·
· · Vv is the vertical etch rate. When V - V then A1 = 0. This is defined
iso tropic ·
etching which produces the typ· e of etchm ·g h 1- v,
· p· 4 32 ( ) ; e 1so . . . h" h" h to be
undercutting. In ind
· • s ow n m 1g. • a , · ·' trop1c etc mg w 1c causes
· ustry however, 1so • •
trop1c etc •
hm • & d to y etching process that .
noticeable degree of underc ' uttmg
· reg g 1s re,erre an results m a
ardless of whet er or not v1-- vv· s· ce all wet etching will res
h . . .
undercutting, wet etching is classi m ult m some
fied as an isotropic etching proces
When V1 = 0, or is very small com s.
pared to Vv, the process is defined
straight walled etching pattern sim to be anisotropic and results ~n ver
ilar to that shown .in Fig. 4.33. Dry y
stra ight walled etching, which is etching, described below, result
important for producing ICs with s m very
minimum feature sizes less than
2 µm.

~eature-I_
. l..,J
Desired
Si- wa fer feature size
(a) (b) (c)
Fig. 4.33. Straight walled etching
pattern. Fig. 4.34. (a) Purely isotropic etc
h, (b) isotropic etch with a
compensation mask, and (c) anisot
ropi~ etch using
plasma etching·with no horizonta
Dry Etching. As stated above, mo l component.
st liquid etches are isotropic and
They also cause narrowing of the result. in the undercut of the ma
feature size as clearly shown in Fig sk.
spaces significantly larger than the . 4:34 (a). For feature linewidths and
feature height, which is true for LS line
problems, because once the amoun I, isotropic et<::hing present only
t of the feature narrowing for an iso a minor
feature size can be achieved by ma tropic etch is known, then the des
king the mask larger, as shown in igned
combined with isotropic etching Fig. 4.;34 (b). Thus, ~a sk compen
is a common practice in LSI techno sation
feature height have comparable dim logy. For VLSI/ULSI devices, in
ensions to feature linewidths and spa which
For this reason dry etching, which ces, mask compensation is impos
is capable of anisotropic etching, sible.
is so important to VLSI/ULSI.
Dry etching is synonymous wit
h plasma assisted etching, which
low-pressure gas discharges. In employs plasmas in the form
fact, plasma etching is one of the of
dry etching methods are reactive popular methods of the dry etchin
ion etching (RIE), sputtering, ion g ; other
The following sections concentra beam etching, and reactive ion bea
te on plasma etching, which is a pop m etching.
The next section presents a brief ular method in semiconductor ind
introduction to the·plasma, which ustry.
etching. will provide us better insight of the
plasma
4.9.2. Introduction to Plasma
Plasma is an.ionized gas with nea
rly equal amounts of positively cha
negatively charged particles, wh rged particles (positive ions) and
ich are usually electrons and a sm
useful for VLSI/ULSI processin g all amo~nt of negative _ion" ,.he
is a weakl y ionized olasma. plasma
 124 lntcgr11tcd Clrc111l1 ► 125
. CVD or LPCVD. The S11N4 cnn be ct h
The ShN4 is deposited at higher temperatures . us1~1~ 0 of 20. Either of the source gnses, CH ; Cd
:maso1ropacnll y 111 the RIE mode with~ sclccll v~ty to ~\~\rt~n/when patterned Sh~4 is used as an oxi~at~ir
f Monolithic IC Processes .
The epitaxial process has been widely employed to prepare compoun d semiconductor
. ma
terials, such as
used to prepare . . g
tollow•~
1 0
AS lnP AIGaAs, InGaAsP, CdSe, and HgCdTe. In addition, t~e pr~es~_1s al\ transistor (HBT), modu a-
C!-1 , F cnn produce these results. Tlus lugh sclcct,vlly ~,~Id ~x,de. In this process, a thm (::::: 100? A) Si N~ fil~
1
The nitride 1s pallcrncd and thick(:::::: 40Qo A Gi~ice•s : li~ht-emilling diod~ . (LED), semiconductor laser, heteroJuncl:~nf;~~e: detector.
mnsk to define trnnsistor regions Ill thermally grown ~~n-doped field-effect 1rans1s1or (MODFET), and the long - wavelengt
1s deposited over n thrn (<::= 200 A) S1O2 lnycr on the sub stradtc.t' n )
k d h h'gh
1 temperature ox1 a 10 . 4 .t0.2. Epitaxial Growth or Silicon
S10 2 1s grown in unmas c regions Y - d CVD films used as a final p . . . . ase Ii uid-phase, vapour-phase,_ and
. . . of lasmn-cnhancc ass1va1ion Tl ere are various epitaxial growth techmques, such as solld-ph . • ~VPE) has received the w1deS t
Another applicati~n o~ ctchrng 1s the pntt~rnrnf tar" c nrcn windows down to contact pnds requires little
layer over completed c1rcu11s. Herc the etclung O • ~ (CF + 0 ) as the source gas. olecu;ar beam deposition. :or a silicon epi-layer, the v~pour-phase ef~~a~~sics of the VPE process.
fcaturc-si1.c control. A typical etch for thi s applicallon is 4 2 . . . rn lance of all these techmques. Therefore, here we briefly focus on p . to the epi-layer

Metallization. Application of reactive. plasma etc 1ung• m · aluminium metalhzallon will be covered i'n a
accep . .
Basics or VPE process. A typical VPE process is illustrate m
d . F
·:!i .
4 39 (a). nor
d f !lowed by a vapour HCI
Inter section . de osition, the reactor is pu~g.ed ~y nilro~~n. or hydro~en ~or a shon pe"ot •~:s (:ay, chlorosilane) into th~
e1ling. The epitaxial depos111on I~ then m111ated by directm_g the reactate; ralure. Once the reactant ~ases
4.10. EPITAXY rowlh reactor, where the substrate 1s locate~ and kep~ at a desired growl h of ~ sical and chemical reacuons,
!re fed into the growth reactor, t~e.se chemical species undergo a ser;:e r~,;th process is clearly illustrated
on, and taxy (Pasllense oftei~en) means 'arranged'. hich result in the epi-layer depos111on. In a stead~ slate the sequenc~ o ~ ) As seen the growth process
4.10.l. ln~.r~ucti~n rd . ., cans 'u
. The word cp11_axy 1s a ?reek ~o , epi :inenl' of~toms (arranging 1hemse~ves ma crystal form) upon : Fig. 4.39 (b). (In the fig~re, the epi-layer deposit on the subsu:ale is n;\~ ~;rine~. depending on the growth
Tlus leads to followmg meanmg. It is_an arra1 la er structure is an exact extension of the sub~trate crystal is bro~n down into various steps that may occur con~ecuuvely o d ils of VPE growth process and
a crystal substrate, so that the _resultmg adden e ~hemselves along existing planes of the crystalline substrate conditions, such as growth temperature and growth pressure. Fo_r the eta of this cha ter.
structure. In other words, deposned atoms arra gb k tension of the crystal structure. The structure of the associated growth kinetics, the reader may turn to the references given at the end P
material, bonding to parent atoms'? fon:" an un ro en ~x - stal substrate.
grown epitaxial layer is thus a conunuauon of that the smgle cry . .
. s • F th above meaning one may conclude that there 1s no difference
Epitaxy vs. Cry taI ~ro;~~!· ,;~;:iqie. Bui where, in epitaxy a thin _fil":1 of single crys!al silic_on is Carri!rgas
between epitaxy and c1sta gr g . ting single crystal of the same material , m crystal growmg, a single Carrier gas
~
unreacled reactants
grown ~rom a varur ~ -e u~\a ex1~n conlrasl lo the growth technique in epitaxy. Furthermore, epitaxial reac~anls (j) 0 +
by-products
processismvolves
crystal romporuon
grown no o thpe sys
e 1quf1 I al a temperature any where near the melting point of the material.
ase;em
Trd nsferof Transfer of
Epitaxy is the foundation on which most devices arc built, an_d may be considered as_a spe~ial case of reactants by- producls
chemical vapour deposition (CVD) 10 be discussed in the next section. As stated above, epitaxy 1s a process lo surface lo main flow
10 grow a single-cryslal layer on a single-crystal substrate. _If the grown_ layer a~d the substrate are of exactl_y Reactor ® ©
the same material, the process is called homoepitaxy, and 1f they are different m any aspects, the p~es~ 1s __s---i_
called heteroepitaxy. A view widely accepted is that homoepitaxy taJces place when the two ~ate~als (1 .t ., Carrier gas Deposil By prOducts
grown layer and substrate) have the same crystalline and chemical structures, whereas he!eroeptlaxy mv_o_lves + -
Reaclanl~
I -
different materials. Example of homoepilaxy is Si-epitaxial layer deposition on a smgle-crystal sthcon
substrate ; this is commonly referred to as epitaxy or conventional Si-epitaxy A silicon epitaxial (epi, as
abbreviated) deposition on a sapphire is the example of heteroepitaxy. The tenn 'conventional ' is used_ to Subslrale Substrate
differentiate it from other novel approaches such as low-temperature epitaxy and selective Si-epitaxy, which ~) ~)
have received a great deal of allention for ULSI technology. Fig. 4.39. (a) Typical VPE process (b) Sequential steps of a VPE process.
Uses of Epitaxy. In earlier years, epitaxy was developed to enhance the perfonnance of discrete bipolar Growth Chemistry of Si-Epitaxy
transistors. These devices were first fabricated in bulk wafers using the wafer's resistivity to determine ~e There are.a number of different chemical reactions that can be used for the deposition of epitaxial layers.
brea~down voltage of th_e collector. However, high breakdown voltages need high-resistivity material. -~is Four silicon sources have been used for growing epitaxial silicon. These are silicon tetrachloride (SiCl. ).
1
requirement, coupled with the thickness of the wafer, results in excessive collector resistance that hmits dichlorosilane (SiH 2C'2), trichlorosilane (SiHC'3) and silane (SiH.1) . The silane has been used when a lower
high-fn:q~e~cy response and increases power dissipation. Epitaxial growth of a high-resistivity layer on 8 growth temperature is desired. The choice of each source gas is based on the growth conditions and layer
low-res1s11v11y substrate solves this problem.
requirements. One of the most important parameters that affects the selection of the Si-source gas is the growth
rate.
nd IC~ ut!lize epitaxial structures in much the same way the discrete transistors utilize them. The
strBipolar
1 ~te ~ epnaxial layer (epi-layer) have opposite doping types to provide isolation and a heavily doped
~~ The chemical reactions that can be used for the deposition of epitaxial layers are as shown in Table 4 .2 .
~srnn ay~r (buried layer) serves as a low resistance collector contact Unipolar devices such as the JFE1 Silicon tetrachloride has been the most studied and has seen the widest industrial use. The overall reaction can
be classed as a hydrogen reduction of a gas.
;m.plaoy ~n elpllaxial wa~er as does the VMOS technology. These structures ·will be discussed in the next chapter.
PI xy 1s a so used to improve the perform fd . MOS JCS,
ance o ynam1c random-access memory devices and C SiCl4 (gas)+ 2H2 (gas)---+ Si (solid)+ 4HCI (gas)
 l'a ble 4.2. Some Impo rtant Reac
tions for Epitaxial Layer Depo
sition Monolithic IC Proce sses
Reaction 127
Te111perat11re range temperature processing steps . This
Deposition Time
(OC) The most serious problem in this will cause a blurring of the impurity profile .m ~he regio ·

'
(µ111/mi11 .) f this interface.
I. SiCl4 + 2H2 - regard will be in the case of a very n° .
Si + 4HCI
1150 -125 0 ihat is deposited on a very heavi thin and very lightly doped ~pitax . 1 layer
ly doped substrate. For exampfo, .ia
2 . SiHCl3 + H2
- Si+ 3HCI
0.4-1 _5
itaxial \ayer is deposited on a 0.005 SO n.cm (No= Ix 10 14 cm-· 5
1100 --120 0 n..cm (No= Ix IQ 19 cm-l) n+ subst ) ~m n-t_y~e
0.4- 2.0 eP rate. The outdi
3. SiH2C h - Si+ 2HCI from the heavily doped substrate . . . . ffusion of impur'.t'.es
mto the lightl . 1
1050 -112 0
0.2-1 that would otherwise be present at y doped ep1tax 1al layer will b ot out thes hart> n/ ,t trans1 . duce
uon
4. S i H 4 - Si+ 2H2
950- 1250
the effective thickness of the lightlythe layer-s~bstr_ate interface.lne influx of d_o~°': ator~s from the su;, 11
0.2-- 0.3 doped ep1tax1al layer by I o.- 2 µm s~;~ -:i; from
heavily doped 11 + substrate, slow donor . To m1rum1re this problem o OU
_In reality, a stu_dy o~ therm diffusants such as antimony and arseni
odyn amic s of the H-C\-Si s~ste c are often used for the doping of subSt
reacu ons were occu nng eithe m show~d- that a numbe~ of in preference to phosphorus. tate
r simu ltane ously or sequentiall intermedia .
the abov e overa ll react ion may y m the depos11ton proce ss. It The epitaxial_ proces~ also s~ffer . . ved Pattern shift
proce ed asJo llow s: 1s postulated hte s from pa~tern s~t due to h~gh _temperatu
occurs when an ep1-layer 1s d~pos res m:,ro \ ics. The main
SiCl.i + H 2 ;= SiHC\3 + HCI
t at cause of these effects 1s the differ1ted over a buned layer _m the fabncat_1on o~modern bipo ar
ent growth rates on various crysta ate the effects
of pattern shift, the circuit desig l onentauons. To compens
SiHC h + H2 ;= SiH2Ch + HCI ... (A) ner must adjust the position of
features on the subsequent mask
In subsection 4.1 .2, we have briefl \ev~1s.
SiH2Cl2 ;= SiC'2 + H2 ...(B) of defects are often observed. y discussed various crystal defec
These defects may result from _ts. In epit~ ia\ process_~:::~ ~s
... (C) substrate 1mperfect1ons. conta 1;~:s
SiHCl3 ;= SiCl2 + HCI mismatch betwee~ ~he substrate mt 0
and epi-layer. Defects due to the d' . Y
prior to the depos1uon process. substrate are re~ated to the s~rf~
SiCl2 + H 2 ;= Si + 2HCI ...(D) Therefore, care must be taken ce ::~i ;:1:~~-
Note that all the abov e react particulate on the front and rear to remove organic and meta\\,c
ions, A to E, are reversible, and ...(E) substrate surface. imp
grow th rate can beco me nega threfore, unde r appro priat e condi 4.10.3. Epita xial Reactors
tive; that mean s etching proce tions the
and depo sitio n in a (SiC 4 + ss can begin . Ther e is a boun dary
H 2) mixtu re at atmospheric betw een etching The epitaxial \ayer deposition .
press ure of SiC4 . Furth ermo pressure as a function of temp takes place in a chamber ca\\ed
eratu re and panial types of reactor horizontal reacto an epitaxial reactor. 1:'er ~ are
re, it is found that an etching r, vertical reactor, and the cylin three basic
temp eratu res and the depo sition process is favou red at both cases the mean~ for heating the drical reactor. as shown m F,g.
process is favoured in the inter low and elevated silicon wafers to the required 4.40. In mos~
1100 to 1300 ° C ; there fore, medi ate temp eratu re range , radiant heating using an array temperature is ,f indu~tion heati
epitaxital deposition (using SiC/ which is usually of focussed high intensity quart n~, ahho ug
For thick er layer grow th SiHC 4 + H2) is perfo rmed at this be used. For if induction heating z halogen lamps, and res1st~nce
/3 is often used because its grow temp eratu re range. the silicon wafers rest on a silico heating can a\so
th rate is highe r than that of cooled copper induction coil n-carbide-coated graph,t~ susce
SiC/4 • serves as the primary winding ptor. A water
Gro wth oflm puri ty Doped in effect as a single-turn secon of a transfonner. The graphite
Epi-Layers. During the epi-l ayer dary winding. The susceptor serves,
impu rities are intro duce d into grow th contr olled amou nt of p- or voltage induced in the susceptor
the carrier gas to contr ol the type n-type produces a cir- RF it\duction heating coil
the diffu sion proce ss, epita xial and resis tivity of the depo sition
growth proceeds by unifo rm addit layer. Unlike culating eddy currents which ,
the dopa nt impu rities are unifo ion of atom ic layer s onto the as a result of heat-
rmly distributed throu gh the epi-l substrate. Thus, ing produced by the PR powe
Furth ermo re, epi-l ayers can ayer, and do not show a conc entra r loss raises the
be grown over diffu sed regio tion gradient. temperature to the required value
ns or over other epi-l ayers . .
For Si epita xy, dibor ane (82 Horizontal reactors offer lowes
H6) is used to incor porat e the t cost con-
(PH h) and arsin e As H3) are p-typ e dopa nt (B), wher eas struction, however, controlling
used for then- type dopa nts (P phosphine the deposition
unsta ble abov e room temperatu and As). Thes e gase s are extre process over the entire susceptor (al
re. Ther efore , they are dilua ted mely toxic and are length is a prob-
that affec t the dopa nt incorporat with a large amou nt of H • The lem. Vertical reactors are capab susc epto r
ion inclu de the grow th temp eratu 2 many factors le of very unifomt ----.. rotat ion
and react or geom etry. re, grow th rate, dopa nt/Si ratio deposition, but suffer from mech
in gas phase, anical complexity. ,- --:._,
Cylindrical reactors are also capab , /"""
Prob lems in Growing Epi-L le of uniform / ,.,,, ft•-,
deposition due to employment
contr ollin g the dopin g conc
ayers. The adva ntage s of the
entra tion and dopin g profi le.
Si epita xy are its flexi bility
and accuracy in but are not suite d for exten
of radiant heating. f t
tem~ ratur e in the rang~ 950_
~dd1u~~· becau se th~ epita xy
1mpu nues , and partJcles on the
to 1250° C ; it suffe rs from
1s an "arra nged upon " proce ss,
How ever, since this proc ess
prob lems such as autod opin
g
it is susce ptibl e to defe ct gene
subst rate prior to or durin g the
and
is carri ed out at
patte rn shift. _In
ratio n due to strain,
temperature above 1200 °c.
Typi cal Epit axial Gro,vth
typical epitaxial grow th proce
ded operation at

Proc e~. A ; '

/ ;
r, Silicon
wafe rs
'
grow th proce ss. ss includes several \~0 Suscciptor
In addition to intentional dopa steps as follows . RF \ndu ct- ,-.- .--- n
nts incor porat ed into the layer
~e _sub strat~ ~r sucep tor throu
limit s the nunt rnu~ layer thi~k
level . Let us co_ns1dcr _a typic
P ~ , ~re wtl_l be diffusion of
gh outdi ffusi on or outga ssing
ness that can be grow n with
al prob lem of outdi ffusi on.
contr
, unint entio nal dopa nts are intro
. This effec t is tenn ed auto
olled dopi ng as well as the mini
Sinc e epi-l ayer depo sitio n
duce d ~m
doping. Autodop~ng
mum doping
is a high temp era!~
_ A hydro gen carrier gas is
the reactor of air. The reactor
temperature.
used to purge ~!s
is then t\eated to a exha ust
Gas
\nlet
\on coil
l.,Al["----
Silicon \ r-i --7
wafe rs ~ \1 i1
' \
Gos
impu rities acros s the epi-l ayer/ - After thermal equilibrium (b)
(cl
~ of ,mpomues. 1lus happens nol subs trate inter face, resul ting is estab lishe d 'inlet
only during epi-la in redistribu~on in the cham ber. anhy drous HCI Fig.
ye, depositioo, bul also lakes place gas is fed into the 4.40. EpitaJC .ia\ reactors
during all ,ubseqllCIII high (a) Horizontal reactor (b) Vertical
reactor (c) Cylindrical reactor.
V 129

J28 Integrated Cir-tu/ft!

a roductio n ha zard because it as

! M•""'Urhk IC Processes .
reactor. The HC/ gas reacts with the silicon at the surfac~ of wafors in reaction t~at is reverse of _that given 0 . . . uirin, frequcnl deaning. 11 also presents . p duces abrupt junc11on .
menuoned m Table 4 -2 · This reverse reaction resu1t/ r :houl 2%. The reaction system using silane pw times al relatively (ow
(SiC/ 4 + H 2 ) . This is a/so true for other reactions rcacior chamber r:~:~!~io~cdbovc
1
,phone ,n cone . horter dcpos111on h . a high
11apour-phase-etchi11g (VPE) of the silicon surface and usually occurs al a temperature between I /SQ 0
aod pyr, 0 ·c11torosila11e as a source offers high gro:th ,rat~~· '/;~;m rempcrat~re. dichlorosil a nc as
I 200°C for 3 min . nominally. 1
as evident from Tahle 4.2. Althoug a 1qu, a .
- The temperature is then reduced to the growth 1en:1pera1ure wit~ time a!lowed for stabilizing th tcmPi;at~:::ure so it can be metered directly from a cylinder. . . discussed in sec- 4. I . It of~ers h1gf;~
temperature and flushing the HCI gas. For (SiCl4 + H2) react,on, the grap~ile boat
in the range I 150- J250°C. The vapour of SiCl 4 and hydrogen as a c_amer gas ~e mlrodu_ced into the tube
,s_heated 10 a_ temperatur: :!
vapo Tr~cltlorosi/ane is used for the phr·' X:tli:~i~yf e!:~~~'::,~;'~:J!~':~~~::iies th_an silicon tlet;:pc:~;;~~;,' · its
at room e d
rd1 10
h I s al /ower temperatures, 1g er P • 1 • 1 a liqmd
for producing epitaxial /ayer. The re~uctio~ ?f SiC/4 takes place acc~ ?g ch:m;;:~:quat,on ~t~ted earlier. gro;r,e::texpensive and most used of all the silicon sou~ces_. t '~es~igh deposition temperatures r~;u1:~e
~ase, silicon source ,s e our pressure requires a bubbler tank 10 help vaponzauon . I oxidizers in the earner gas an o
Jr ,s usual to mcorporate p- or n"type 1mpun11es to produce doped epllax,al layer · h t
. h
and the dopant flows both are turned on and growth proceeds al a rate of0.2 to 2.0 µm/mm . ~~:i~:~n tetrachloride make it less sensitive then the other sources o
eliminated a nd th e temperature reduced defects they cause. . ween 900 and I 250oC . Selecting t c
- Once growth is complete, the dopant and silicon flows are decision based on several ~actors,
' e o crating temperature range of epitaxial reactor~ is bet
usually by shutting of the power. ce;:ng r~mpcratures as well as th~ flow_and gr~wl~ ratfs is a_c~m:~e;the defect level~. pattern shift , a nd
- As the reactor cools toward ambient temperature, the hydrogen flow is replaced by a nitrogen flow f~~h as, the film thickness, doping umformny. dopmg eve require .
so that lhe reactor may be opened safely. distortion al/owed. ·c (i e pH 1 • s 2 H 6 • o r AsH3).
Depending on wafer diameter and reactor type, capacities ra~ge from 10_to 15 wafer per batch. Process The usual sources of dopanl are hydrides orlhosphor~fS, ~ro:~c'::n:~:~ is ~~~d I~ fonn the f piraxial
cycle times are about J hr. The vapour-phase etching (VPE) described above 1s necessary lo remove a small , Doping levels in epitaxial layers r_ar~ly exceed IO a~oms/cm ·. ~~\~e ran e 10'4 10 10'1 atoms/cm· . Lower
amount of Si and other contaminants from the wafer surfaces to ensure that a clear freshly etched silicon surfac base of bipolar transistor. In ma;.onty of c~es doping level JS , .. g of high voltage and deti.;ctor
will be available forepi-layerdeposi1ion. When the concentration ofSiCJ4 is high, etching can still occur eve: doping levels, in the 10'2 to JO 4 atoms/cm· range are used (or c;~a~:~~~: must be pure. Silicon sourc~s
when hydrogen chloride is not present due 10 a competing interaction. devices. To obtain such lower values, 1lfe reactor m~st be clean an ·1 bl The near surface of the silicon is
with a purity less than IOIJ atoms/cm· m the deposited ~Im are av~, a e. Uniformities of± 10% within
SiCl4 + Si := 2 SiCl2
sealed with oxide or nitri.d e layer _10 _contro! t~e autodopmg from this si;::~:-run are on the order of 20% or
Thus, the growth rate o_f epitax~a_ J silicon, ~hich will be negative if etching occu~, is ve'r critically wafers are routinely obtained, variauons within a run (batch) and ~ror".1 . . h d ·ust before the
dependent on the concentration of silicon chlonde as well as the temperature. In typical environmental' less. depending on the process and reactor. The upper limit of e~1tax1al ~1ckness is _reac e J e tor If
conditions for growth, at a rate of around 1 µmlm., produces layers which are well within the region for layer overgrows the substrate and the film becomes continuous with the silicon deposued on the su;c p uall
single-crystal epitaxy. the /ayer overgrows the substrate, the wafers become hard to separate from the susceptor, and the wa er us 1/
When reduction of SiC4 lakes place, the reaction gives rise lo free silicon atoms. Atoms from the gas cracks when removal is attempted. However. film lhick~ess of s~veral hundred m_icromet~rs ar~ grown usu a ~
phase skid about on the surface of the growing epitaxial film until they find correct position in the lattice before for some power devices. The lower limit on epi-layer thickness 1s put by aurodopmg cons1derauons, bul layer
becoming fastened into the growing structure. as thin as 0.05 to 0.5 µm have been produced.
. I:or producing doped p-or n-type epi-Jayer, a number of gases can be metered into the reactor lube, 4.10.4. Characterization or Epi-Layers
mcludm_g some very small am~unts of doping gases, such as B2H6 (diborane) for boron doping and PH.1 ln this subsection we will briefly review some of the measurements that are essential to evaluate epitaxial
(phosphme) for phosphorus dopmg of the epi-Jayer. During the epi-Jayer deposition the dopant gas molecules layers. The measurements, perfonned using sophisticated instrumentation, are used for characterizing physical,
reac~ and becom~ deco~posed and the dopant atoms thus produced become incorporated into the epi-layer. chemical, and electrical properties of the epi-layer. By employing proper characterization techniques, the
Dopmg of the ep,-layer is also a~hiev~ by adding controlled amounts of the appropriate impurity in liquid
form, for example, phosphorus tnchlonde or arsenic 1richloride, 10 the silicon chloride. manufacturers can develope and implement a successful epitaxial process.
The main advantages and disadvantages of SiCl4 as a source of Si epitaxy are as follows ; The physical properties of an epi-layer include surface morphology, crystallographic defects. siress,
and layer thickness. Surface morphology is nonnally examined by eyes under high-intensity illumination . This
Adva111ages. (i) SiCl4 is non-toxic, inexpensive and easy lo purify.
is frequently used because of its simplicity and high screening speed. When a detailed surface morphology is
(ii) Thiel reaction making silicon from SiCJ4 takes place only al surface and not on the boat or reaction required microscopic methods are employed. The optical microscopy is available in brightfield and darkfield
': h am be rwa s. modes. The brightfield mode gives the best overall image and information about the surface and is, therefore,
Disadvantages. (i) The growth process is ac 'ed b . commonly used. In contrast, the darkfield mode is very powerful in resolving small structural features on the
exchange of impurities between sil . fi d com~am Y th~ diffusion phenomenon which causes an surface and is often used to scan a wide range of defects (including crystallographic defects after etching) on
junction. icon wa er an growmg film. Tius prevents the fabrication of an ideal step
the surface. Nomarski interference-contrast microscopy can resolve surface features of3 to 5 nm in depth, far
(ii) SiCl4 process requires higher tern h . . . beyond what can be achieved by ordinary optical microscopy. Scanning electron microscope (SEM) is capable
growth rate. perature t an sllane process ( discussed below) and also has slower , o~resolving submicron surface features al a magnification much higher than that obtainable with any optical
. . . mi~roscopy. The crystal/graphic defects in the epi-layers are not always readily visible. Etchents are used to
. Choice of Si Sources. The other source f T
,s chosen when a low deposition I so _s, icon, as given earlier, are SiHCh SiH:zCl2 and Siff4. Stlant delineate defects preferentially prior to microscopic examination. A variety of techniques may be used to
(Arsenic autodoping increases with ;mperature is needed ~o minimize boron aur~oping and outdiffusion. me~ure the stress in the epi-layer. The stress is measured in terms of the wafer centre deflection . The final
ower temperatures) Slla ·n
'the Ii
:.,
·
ormat,on of silicon particles in the as stre . ne processes are prone to gas-phase nucleauo ~rhys1cal propert~ is the lay~r thickness: Th~ most widely used epi-layer thickness measurement techniques
Jas-phase nucleation can be suppressed by ~ddin : above the ~afer), which leads to poor film quality. e based on optical properties of the S1 ep1-layer. In the near infrared region (2.5 to 50 µm), lightly doped
g Cl. Anorher disadvantage is that silane rends to coat the

130 Integrated Circuits
Si is relative! ~ tran sp~rcnt. _where~s heavily doped ~i beh~ves as a re~ective surfa~e . Therefore, When
electromagnetic radiati on wnh various wavdengths ~s applied lo an ep1-la~er on as, substrate, interfere an
and optical patterns are formed because of the mterac~1on ~et ween the reflections from the air/epi-layer surr°cc
ace
and epi-layer/substrate intcface. Based on these optical interference patterns, the epi-layer thicknes
obtained . For epi-layer thickness _measurement can be performed by infrared (IR) inter~;r:n be
spectrophotometer, Founer-transform infrared (FTIR) spectroscopy, or high-resolution double-cryst
I
nee
diffracrion (HRXRD) method. The IR apparatus is a quick and nondestructive thickness meas a X-ray
te c hnique . The FTIR apparatus is capable of rapid (= 30 sec), accurate (± 0.05 µm), and ur;;~nt
(± 0.005 µm) measurement and, therefore, is widely accepted. The HRXRD method can measur I: case
1hickness of multilayer structures with an accuracy within± 2%. e a layer
Now. let us ~riefly revi~w the measurement techn_iques, which are used to characterize the chemical a
electn~al properties of an e~1-layer: These l~o properties are usually closely related. For instance, resistiv~d
(electncal propert~) of an ep1-lay~r 1s propo'.11onal to _the (activate~) dopant c~ncentrali~on (chemical propen ty
A d_o.pant m the ep1-layercan be euher electnc~ly active or nonactive, depending on the lauice site. Electrica~).,
_acm e dopant concentrauo~ can be determined_ only by electrical measurement techniques, such as 1:.1
four-p~mt P:Obe (~!ready d~scussed)_. and capacnance-voltage (C-\/) . On the other hand, total dopanr co e
ccnt~uons (including electncal_ly acllve and nonactive species) are usually measured by surface spectrosco ~-
techniques, such as secondary-ion mass spectroscopy (SIMS). Auger electron spectroscopy (AES) el pie
spectroscopy for chemical analysis {ESCA), and Rutherford backscattering spactroscopy (RBS). ' ectron
In sub-section_4.4._3, the four-~oint probe technique has been discussed. This is one of the fastest techni ue
10
r measure the resm,vtty of an ep1-layer. However, it is applicable only to an epi - layer that is grown q
•ghf Y do~ sub stra1e of an opposite conductivity type to the layer. In this technique, the resistivity p ~~ a 0
cpi- aye~ is expre~ed by P = Rs T F, where Rs is the sheet resistivity, Tis the epi-layer thickness and Fis the
fse::e:c correcuo~ factor. To avoid ohmic contact heating or reaching punch-through voltage, low-curren:
th· Ph Y~- For thin ~ayer measurement, care must be taken to avoid the tips penetrating the layer. Overall
is tee ruque_can achie~e an accuracy of only± 10% and is not capable of measuring doping profiles.
form ;:1;;:i:t:.mgprofile 1_n the e_p i-layer i_s measured by the C-V technique, that employs a mercury contact to
f ky ~amer diode wi th th e epi-layer. By applying a reverse bias, the capacitance (C). as a function
0
volJage (\/), is recorded, and the doping ·profile is obtained according to the equation : N (x) = - c3
~q EA ~dC/d\/)] and x = EA/(C (\/), where A is the junction area, xis the distance from the junction and V
th
as e bias voltage. This technique is rapid, and works well with doping in the range oi 10 14 to l0 17/c~J.
As stated before, total dopant concentratio d ·
techniques are thus used 10 evaluate the ch . n are meas_u re :ising s~rface spectroscopic techniques. These
process control. However, as Si technolo em1cal properties of the ep1-~a~er. '."ey are not useful for routine
more and more important bee f gy becomes more and more miniaturized, these techniques become
ause o excellent depth-profiling capability.
4.11. CHEMICAL VAPOUR DEPOSITION (CVD)
4.11.1. Introduction
Chemical vapour deposition (CVD) i b .
leading to the fonnation of rd bs a process Y which gases or vapours are chemically reacted,
strate. The CVD may ~ defined as the formation of nonvolatile
solid film on a substrate b a ~ on ~ su
constitutents It is a materiat thr~cllon of vapour-phase chemicals (reactants) that contain the required
near or on a ~ubstrate s rf: syn,. es1s pr~ss whereby the constituents of the vapour phases react chemically
u ace to ,orm a sohd product.
In th e fabrication of ICs dielectric fit d ·· · . .
are silicon dioxide and silico'n nitride, wh:h epos1llon is exte~s1ve~y used. Two comm~nly_used dielecu:1cs
d1e!ectncs, polysi/icon also has number of use;r.e. used ~ the isolallon, mask! ~nd passivation layers. L1~e
resistor by proper doping with d .n . . . ••ts film is used as the conducting layer, semiconductor, or
and therefore, is an important ~r~rent_im~u~llbres_. ~e CVO is used to deposit dielectric and polysilicon films.
ess rn e a icauonn of ICs. It should be emphasized that the Si0 2 layer
• 131
r
Monolithic JC Processes
. al .d · proc ess (section
formed using CVD process 1s not as good_as~ thermally grown oxide us ing therm o~• a11on . de osits
P
_ ), but is good enough to act as an electrical insulator. The ad vantage of a CVD layer 1s that the oxide
46
at a foster rate and the process requires much lower tcmpcraturc. .
Epitaxy vs. CVD. In epi~axy, the layer is dc~osited as a crystallin~ lay~r (as_s uming the subs~:=s~~
crystclline sil~con). The depos111on occurs•~ crystalline form beca~e the epllaxy 1s ~ high temperatur~~ ection,
B cause of high temperature the atoms gam enough energy to ahgn themselves m proper crystal ir .
re:ulting in an exact extension of the substrate crystal structure. For example, if s!lane _g ~ is used as sou~:::;
the epitaxial process, we find crystalline silicon layer deposit on the crystalline s1hcon wafer. At .
temperature than ~hat required for ~pit~xy, the atoms_will not be able to align alon~ the same crystal ~irect~on~
i.e., deposition will no ~ore _be epllax1al. However,_11 ~a_y be referre~ t~ as ~hem1c_a l vapour deposiuon . ta ls
the silicon layer so deposlled 1s called as polycrystalhne s1hcon (poly-SI) smce 11 cons~sts of ma_ny smaJI crys
of silicon aligned in various directions. It should be noted that poly-Si formation will occur _1~ above process
even if temperature is that of epitaxial process. but substrate surface is not a si ngle-crystal silicon.
From above discussion we deri ve conclusion as follows : The CVD is used not only lo 11eposit dielectrics
and poly-Si, but also to deposit single-crystal silicon on Si-wafer in which case the deposition is te~ed _as
epiiaxial deposition. Therefore, silicon epitaxial deposition is a special case of CVD. In fact, epitaxial
deposition was the initial form in which CVD was used in IC fabrication ; since then C~~ te~hnolo~y has
been developing, and now it .plays very wider role in IC fabrication . The epitaxial depos111on (m particula r.
homoepitaxy) has already been discussed in section 4. 10. but should be treated as special CVD process. that
occurs only for certain combinations of substrate and layer materials and under certain deposition conditions.
In this section we will, therefore, discuss deposition of Si0 2 , SiN3• poly-Si, and the depos ition of silicon crysta l
on sapphire (i.e. heteroepitaxy). The CVD is also used to deposit metals, and is used as a process for
metallization ; this will be covered in section 4.12.
4.11.2. CVD Process and Reactors
' CVDProcess
CVD Reactions. Like epitaxial process, a CVD reaction can be broken down into the following sequential
steps : (I) Transport of reacting gaseous species to the substrate surface (2) Absorption of species on the
substrate surface (3) Heterogeneous surface reaction catalyzed by the substrate surface (4) Desorption of
gaseous reaction by-products (5) Transport of reaction by-products away from the substrate surface. If we refer
to Fig. 4.39 (b), showing VPE process steps, we find that CVD process steps are essentially the same . The
chemical reactions of rectant gases (leading to the formation of solid material) take place not only on (or very
close 10) the wafer surface (heterogeneous reaction) but also in the gas phase (homogeneous reaction). Since,
it is the heterogeneous reaction that produces good quality films, such reactions are very much desired (refer
reaction step 3 above). Homogeneous reactions are undersirable, because they form gas phase clusters of the
depositing material, resuhing in poorly adhering, low-density films with defects. In addition, such reactions
also consume the reactants and can cause a decrease in deposition rate. A thorough study of the CVD process
involves examining the thermodynamics and Kinetics of the chemical reactions and the fluid mechanics of the
gas flow in the reactor.
The aforementioned steps (numbered I to 5) for the CVD process arc sequential ; so the one that occurs
at the slowest rate will determine the deposition rate, and is called the rate-limiting step. If the deposition
process is dominated by step 2, 3 or 4 as numbered above, one may say it is a surface-controlled process. On
the other hand, if a deposition process is dominated by step I, it is called a ma.ss-tran.rpan controlled process.
Thus, the rate limiting steps can be grouped into gas phase process and surface process. Thus step t (namely,
tra~sport of reactant to substrate is a reaction in gas phase process, while step 2, 3, and 4 are the reactions,
which can be grouped in the surface process.
Now, let us assume that the reactants as a gas stream above the substrate (Fig. 4.41 (a)) is divided into
two regions : free gas stream region and boundary layer region . The free gas stream is away from the substrate
surface in which the gas stream moves wi1h a velocity v in parallel to the substrate surface (a laminar flow is
 ·- , .. ..., uuuncta I
Strate surface (bet ry ayer exists next to th b
ween the b e su • Monolithic IC Processes
stream). in which th su _strate surface and free 133
e gas velocity . gas
reactant species to the b is zero. The transport of CVD Reactors
o su strate surf .
ccurs by gas-phase diffusion . ~ce (reacllon step I) Based on pressure regime, the re actors are classified as low. pressure and high pressure reactors. ~e
the free gas stream reg· m which the species from )ow-pressure group ~an be fun_hcr split into LPCVD reactors (thermal energy input) and PECVD reacto_rs
gas-phase diffusion (icon c~oss the boundary layer. The in
. . which ener~~ is partially supplied hy a plasma as well . Each of the reactor types in these two pressure regimes
ausing ma LogR
species) is proponional to the d'ffi . s~ transport of the is further divided into subgroups, which arc based on reactor geometry and heating methods . Four methods
of
concentrali9n grad1'ent I us1v1ty of the gas and the : Surfacs.reaction- heating the wafer exists : resistance heating ,finduction heating, plasma heating. and heating by photon energy.
• across the bo d ; rate-lim ited
When bolh wafers as well as reaction chambers become hot, as happens in resistance heating, the designs are
we can assume the depo ' t• un ary layer. Thus
.. s1 ion rate as th ' transport•
known as ho1-wall reactors. In these systems, films deposit on the reactor chamber walls as well as on substrate.
gases cross the bou d e rate at which the lim ited
1 This implies that reactors w_ill require frequent cleaning to avoid particle contamination. In case of ,finduction
transpon is only re~ ~layer. The rate of such mass
deposition temperat:;;e i we:kly influenced by the
temperatures the surfac . n_ t e other hand, at low
heating or infrared heating the chamber walls may not be appreciably heated, so reactors heated by these
methods are called cold-wall.reactors. If the heating of walls in these systems are significant, cooling (e.g.,
water cooling) is implemented to prevent reaction or deposition on the wall.
and eventually the arriv~ reaction rate (step 3) is reduced,
at wh. h h rate of reactants exceeds the rate The geometry of the reactors depends on the pressure regime and heat energy source, and is an important
proce:; ~n:!r are consu~~d by the surface reaction factor in throughput. APCVD reactors operate in mass-transport-limited regime, so they we designed such
. . such condtllons, the deposition rate is that an equal flux of reactants is delivered to each wafer to ensure uniform film deposition. This is achieved
surface-reactio n-rate-limited Thus at h ' h by positioning the wafers horizontally and moving them under the gas stream. An undesirable consequence
the d •. . · , 1g temperatures,
eposiuon is usually mass-tra11sport-limited ~hile at (b) of this design is the high susceptibility of the wafers to incorporated falling particles.
1
ow te~per~tures it is surface-reactio11-rate-li~1ited, as Fig. 4.41 . (a) Reactant gas stream above substrai In earlier years, dielectric and polysilicon films have been deposited at atmospheric pressure by using a
sho~n 10 Ftg: 4 -41 (b) ; the deposition rate R is a rapid face (b) CVD deposition rate R varying as a fun:,~~~- variety of reactor geometries. All these atmospheric-pressure reactors tend to have low wafer throughput,
of temperature T.
vary mg function of temperature Tin the surface-reaction- require excessive wafer handling during loading and unloading, and provide thickness uniformities that
arc
lim!ted re~ime of opei:ation (low 7),. whereas it changes only slowly with Tin the mass . trans no beucr than ±10%. Consequently, they have been replaced by low-pressure, hot-wall reactors. Operation
ort-limi at
atmospheric pressure, however, keeps the reactor design simple, and allows high film deposition rates. Some
regim~ _(higher n. llus means that m processes that are under surface-reaction- rate limitatio/ a cons/ed
other drawbacks of these reactors are that the films exhibit poor step coverage, and the wafers are highly
ct;post~on temperature must exist everywhere at all wafer surfaces so as to ensure unifonn de~osition
a~, exposed to particle contamination, as they are laid flat. Fig. 4.42 (a) shows a coniinuously-processing APCVD
~ roug out the reactor._Under such ~onditions, however, the rate at which species arrive at the surface is~o~ reactor, and is used for depositing low-temperature oxide films. The samples are carried through the
1m~ortant, because their concentrations do not limit the growth rate. Thus, it is not critical that reactor
a reactor be on a conveyor belt. Reactant gases flowing through the centre of the reactor are contained by gas curtains
designed to supply an equal flux of reactants to all locations of a wafer surface On the other ha d' · formed by fast flow of nitrogen. In some systems, horizomal tube type APCVD reactor is found. Such system
th . . · d ••
processes at are mass-transport limned, the temperature control is not so critical n m epos111on
because the growth rate is consist of horizontal quartz tube, with wafers lying flat on a fixed horizontal plate, while gas nows parallel
weakly dependent on the temperature (Fig. 4.41 (b)). However, to ensure unifo~ film deposition to
it 'is very the wafer surface. However, the continuous-processing reacters are the most widely used designs because they
much necessary _that th e reactor mu st supply an equal flux of reactants to all locations of a wafer (This possess the benefilts of high throughput, good uniformity, and the capability to process large-diameter wafers.
means
~ame concentrat,_on of reactants to be presem in the bulk gas region adjacent to all locations of the wafer): · However, they have high gas consumption and frequent need of reactor cleaning.
This
is because th e an val rates of reactants are directly proportional to the concentration gradient in the
bulk gas. · LPCVD Reactors. Fig. 4.42 (b) shows a hot-wall LPCVD reactor used to deposit polysilicon, silicon
CVD Methods. The most common de dioxide, and silicon nitride. The reactor consists of a quartz tube heated by a three-zone furnace, with
posi ion met·hod s are (1)· Atmosphenc-pre
d .. A .. ·1· · gas
ssure chemical vapour introduced into one end and pumped out the other. Pressures in the reaction chambers are typically 30 to
epo~illon ( PCVD) <.11} Low-pressure chemical vapour deposition (LPCVD), and (iii) Plasma-enhanced 250
chemical vapour depostt1on (PECVD) or plasma deposition . Pa (0.25 to 2.0 Torr); temperature ranges between 300 and 900°C, and gas nows are between 100 and l000
std . cm 3/min . (Gas nows are always reported at standard conditions, 0°C and I atm pressure). Wafers stand
A comparison of APCVD and LPCVD h th th
t . . s ows at e advantages oflow-pressure deposition are unifonn vertically, perpendicular to th~ gas flow, in a quartz holder. Special insert that alter the gas flow dynamics
are
~ ep c_o~erage · precise control of composition and structure ; low temperature processing • high-enough sometimes used . Each run processes 50 to 2(_)0 wafer_s _wi{h thicko~ss..unifor::mJ ti~SJ>f the depq_site!l_film_s_~ ithin
ep~sihon _rates a nd t~ro~ghput ; low processing cost ; no carrier gases required thus red~cing ± 5%. The LPCVD reactor can be easily scaled to hold 150 mm diameter wafers. The LPCVD has number of
particle
con ammauon ; and ep1tax1al growth of silicon at reduced pressure minimizes autod~ping. a~ntages as slated earlier, hence it is widely used in the highly cost-competitive semiconductor industry
for
Most serious disadvantages ofLPCVD d APCVD · film depositions. Whereas, the APCVD is mass - transport-limited, the LPCVD systems operate in a surface

:p~;:ro~r~~~;~~
.

PECVD an
.

.
an · ·
1s that their operating temperatures are high PECVD
to solve this proble~, as ~iscussed later. In fact, the classification of CVD into
is ased on pressure regime. A CVD method is also categorized by its energy input;
- reaction-rate limited mode. Therefore supply of equal flux of reactants to all wafers is not much desired.
a result, the reactor geometry can be designed in such a way that it can accommodate a large number of wafers
per run. Therefore, as stated above, wafers are stacked side by side, only a few mm apart, allowing wafer holder
As

. . uses rf power to generate glow discharge to transfer the energy into the reactanr gases, allowing
the
dep~s1110n on the substrate at a low temperature than in the APCVD or the LPCVD process. In
addition to
abo11e three methods, some more CVD methods exist, and will be discussed later.
to hold upto 200 wafers. For high-volume production of ICs, the number of wafers processed simultaneously
should be as large as possible, and this requirement for high wafer capacity led to the development of
the
commercially important hot-wall LPCVD reactor, shown in Fig. 4.42 (b), that satisfies the high wafer capacity
demand due to the reason mention above. However. LPCVD reactors must be capable of precise temperature
134 Integrated c·
•rcui~
N2 Gos
·+ t Prcssutc
sensor

d~1..) U -.-...-. 3- zone furnace

Heater 11111111111 & -Pump

-------,Ii ~onvcyor 'R \

Load ~as
.
f . _ __ _ _ j\JOrtz
tub~
Exhaust belt door inlet
(a) (b)
Insulated RF input Pressure
~ns·or Graphite
electrodes
Glass 3- zone furn ace
·cylinder
Aluminium ,·,.c-'•r·,,--,./-.. •

.,=~l~,
Gos holder
inl~t Pump
1-------11,-...-, . electrodes

l
Gas
inlet
Load
door
,--- 1
Gas inlet
l.-1•

-
•'-"--", _, t==~
~~==-==-~=-==--=-=_=_::==:::_:_-,=i=?ft-J
-
Quartz
tubt
(c) (d)
Fig. 4.42. CVD Reactors (a) Continuous, atmospheric-pressure reactor (b) Hot-wall, reduced-pressure reactor
(c) Parallel-plate plasma-deposition reactor (d) Hot-wall plasma-deposition reactor.

control , because they operate i~ the surface-reaction-limited mode (note that APCVD requires precise reactant
flu x control).

The major advantages of the LPCVD reactor of hot-wall type shown in Fig. 4.42 (a) are large load space,
good unif~rmity , an_d lhe ability lo feed large-diameter wafers. However, low deposition rates and the frequenl
use of toxic, corrosive, or flammable gases are the problems.
PECVD Rea~t~~- Th~ PECVD systems. rat : r~ 1.. ; ... ~~ , _,. ,ical
Monolithic IC Processes 137

along th e stcp waits . The lh!ck cusp at the lnp of the step and the thin crevice at the bottom combine to give a
re -entrant shape that 1s particularly difficult to cover with metal.
Uses of Si02.Film. _Silicon-dioxide film can be deposited with or without dopants. In VLSI , undoped
S!?2 1~used as an ms~lalmg layer between multilevel metallization. It is also used as an ion-implantation or
dtl1us_inn mask,_a captng laycl' over dot,ed regions to prevent outdiffusion during heat cycles, and to increase
the thickness ?t thcrma.\\y ~rown oxide. Phosphorous-doped SiO 2 is also used as an insulator between metal
l~ycrs, as a 1mal pas~ivauon layer over devices, and as a gcttering source. Phosphorous-doped SiO2 is
trc~ucntly u~~d as an mst~l~tor between polysilicon gates and the top metallization. A re-entrant shape in the
oxide covcnng the polys1hcon gale makes uniform deposition of the metal film impossible. The poor step
coverage of the phosphorous-doped SiO2 can be corrected by P-glass reflow process. In this process, after
chemical vapour deposition of P-doped Si02, subsequent heating is employed until the oxide softens and flows.
Therefore. the process it named reflow,
The most common reaction for depositing SiO 2 for VLSI circuits arc oxidizing silane, SiH.~ with 0 2 at
400 to 450°C. decomposing tetra ethoxysilane Si(OC 2H~)4 at 650 to 750°C, and reacting dichlorosilane,
SiCbH2, with nitrous oxide at 850 to 900°C.
Silicon Nitride Deposition. Silicon nitride (Si 3 N4) is commonly used in passivation layers on integrated
devices because of its ability to protect the diffusion of impurities and water, which would make the devices
unstable. Silicon nitride can be chemical-vapour deposited by reacting silane and ammonia at atmospheric
pressure and temperature ranging from 700 to 800° C :
3 SiH4 + 4 NH3 ➔ Si3N4 + 12 H2
(APCVD)
(gas) (gas) (solid) (gas)
or by reacting dichlorosilane and ammonia at reduced pressure and temperature between 700 and 800° C :
3 SiC12H2 + 4 NH3 ➔ Si3N4 + 6 H2 (LPCVD)
(gas) (gas) (solid) (gas)
Better uniformity and higher wafer throughput can be achieved by the low-pressure process.
Advantages of Si 3 N 4 A compound which is more resistant to ionic contamination is silicon nitride
:
(Si 3N4 ). The problems of surface contaminations can be solved by using Si3N4. MOS devices are operated at
low current levels and hence they are prone to surface contaminations. Silicon nitride can be used as a
passivating layer for MOS devices used particularly in analog IC's. The second advantage of SbN.i- is that it
has superior masking properties against the dopant impurities as compared to SiO2. The dopants such as Ga
or Al can be effectively masked by Si 3N4. Notice that these elements readily diffuse through SiO~. In particular,
Si 3N4 serv~s as a very good barrier against the penetration of such contaminants as Na+, K\ and other ions
against which SiO 2 is much less effective.
Uses ofs; 3N4 . Silicon nitride can serve as a diffusion or ion implantation mask. An interest int· ,: t'.\1h: :.uon
of silicon nitride js as an oxidation mask. The diffusion rnte of the various ox.idants, such as, U: . ..11d H2O. is
very small in silicon nitride, such that a very thin nitride layer (-1000 A) will be sufficient to prevent the
o,ddation of the underlying silicon. This is the hasis of the local oxidation of silicon (LOCOS) process used
in the fabrication of some types of high-density ICs. The Si3N4 is also used as the dielectric for DRAM MOS
capacitors when it combines with SiO2,
In the LOCOS process a siliGon nitride layer is deposited on a silicon wafer and patterned by a
photolithographic process. The wafer is then subjected tc~ a_ ther~al oxidation ~ro~ess, but th~ thermal oxide
is grown only in those areas that are not covered by the nunde him, as shown to Fig. 4.44.
The most commonly used process for the deposition of silicon nitride layers uses the CVD reaction in
which silane and ammonia are decomposed. The reaction is already given, as before, and takes place in the
presence of hydrogen .
 ~
;.:
lntegrat,dc1,,,..,_'1
13 8
~ Si3N,
r
Sh a// ~w etc he
d
·
111• Mo nol llhl c JC
Processes
contain as many
as three separate
polysilicon lay ers
,

~ "---lc.@:::2½~½->,z½->2;:½Z½->c:2°~0-;~¼/,7,/~~----'W7?m'~~ tec hno log ies .

Si3 N, \, e MO S orane
/ ilicon film . Som . nic or hos d1bphi ne
t a granular or po lys another by layers of S102. .
dm g phosp me
h' , ars ~d -'
-'- <" '-'" t0 j separated from one is dop ed dur ing deposition by _a_d rate . In contrast , a mg P
..
5 , wa fer •
on. Pol ysilicon se in the deposition
Do pin g Polysilicg diborane cau ses a large increa
Si -w afe r . Addin def~~;~~~~
~
.
(a)
5 1. 0 2 ~
to the reactants
or arsenic causes
a rap id dec rea se in the deposition rate
on, or t~e- ~dd itio n of ~op
usion, impla?tati res1s11v111es: Th': res1suv ~ of ~l?1s ope
1 im pla n d J
a_nt gas es durit~~ po dur ing
tur e
Si3N,
~ be doped by diff on
Po/ysilic~n can perature process that results m lowre and annealing um e._ Po lys ihc osi ~o n tem per ;s ar;
is a hig h-t em tem per atu ons of dep
Diffusion e, annealing ng functJ o;::es~10~situ
y on implant dos vities that are stro fc~r these three dopm~_pr
depends prim_aril ing PH3, As , or B2H6 have resisti jor dif-ference bi 11Y or ft
n
deposition by add ann eal ing tem perature. The ma for 1mplanta11on and lo"'.er mo per atu res , 0 e
Si- wa fer tra tio n, and cen trat ion ces sin g tem

"
dopant con cen er dop ant con of low er pro .
for diffusion , low er the advantage
( c) lower resistivity n an~ in~situ doping, ho"'.ever, off cap aci tor s.
S Process. as . doping . Implanta
ti~
m VL SI pro cessing. for Si- MO SF ET s, pla tes of ta!
Fig. 4.44. LOCO ts in Si using SiJN the dominant con
s1derauon tions include gat
e electr ode , a me tal or ~e
(b) Etching slo st an etching mas
k
m. Typical applica rces. Fu rth erm ore e or
~ )D ..
ing of silicon nitride film an oxidation ma Use of Po ly- Si Fil rs), and diffusion sou pol y-S i gat e to fon n a_po /ye ,

I
pattern ng Si3N4 as • (co ndu cto
a eposw on and rmal oxi de layer usi CV D ·
interconnection
layers
n deposited ove
r the cha mc ~I senso~
s,

r-
wth of the the rm al and me
Ph t (c)_Gro Ph oto res ist ox ide resistors, fuses, m silicide, is ofte aic conversion, pos sib le by its
o ore s,s t ~ ~ tungsten or tantalu tion in photovolt ical iso lati on is
silicide, such as s app lica ele ctr
< ;V D ~
ox ,ae
_#
,,,,_# ?
C~ ~ salicide structu
re. Poly-Si als o
liquid-cry stal dis
find
plays (LCDs). Th
e use of pol y-S i for
ect ion s bet we en
and large -area ow . pro vid e int erc onn
Si- wa fer oxidation , and is
dis cus sed bel
abo ve, pol ysi licon is used to , wh ich can be em plo yed as
ted ical isolation
Si- wa fer lysilicon. As sta

I
atu res
Si- wa fer Ox ida tio n of Po of pol ysi lico n provides electr ed in dry ox yg en at te~ per
~ es. Thermal oxi
dation ally oxi diz lay ers .
devices and gat ctu res . Polysilicon is usu gat e and oth er con du cti ng
~ g mask: /ec!ric for mu hil
aye r stru
dop ed- pol ysi lico n
~lline sili ~o n.
~ oxide as an etchin de using HF I . an in!erl c vc/ die ulator between the and I 100} c1:}'st
. layer using CV D oxi I 000 °C [o form an ins we en the rates for { I l I} da1 1on 1s det erm ine d
5. Patterning of SiJN4 torcsist film ; (b) etching of CV D c acid. so ut,on; between 900 and dizes at a rate bet
and the rat e of ox1
. Fig . 4.4
terned pho phosphori y doped silicon oxi faster than undopcd polysilicon,
a
y to produce a pat g of SiOi using hot Undopcd or lightl dizes
(. ~ Phato/1thographremoval of photoresist and etchin · • Ph osp hor us- dop
ed po/ y.5i/icon oxi n sur fac e. ysi lic on . Th e Si0
2
(c) h ·
ot (~180°C) hDosp ~dnc,ac1d (1:'3P04) soluti on. Unfortunatekly, centration al the
po/ ysi lico
wn on sili con and
that gro wn on pol
n ox ide s gro wn
can beetchedwithah a CPV as the etchin8 mas ' as / by the dopant con of oxi de gro her str ess tha
nitrid e film s soluti on so aye r is use d ence in the proper
ties ren ts, and hig de int erf ace
Silicon up to this etching ox , e ·d · d There is a differ hig her leakage cur pol ysi lic on- oxi
will not stand . ' D 'd breakdown fields, d to the rou gh
photoresist first and then the CV /ico n has lower perties are rel ate pol ysi lic on pro
du ces
. F' 4 45· Th e ml. nde layer is deposited :~:~~i:;:~~- grown on pol ysi rad ed oxi de pro
Ox ida tio n of am orp ho us
1
s iown m ig. · :c ~: io to ~~ i:; ~f~~ice:~;~:ss~mtnde layer very on sin gle -cr yst al
silicon . The deg
of the pol ysilicon sur fac e. kag e cur ren ts.
~~ :h~ !; :;~ ?llack the the initial roughn
ess h and low lea
vit y. Th e
~:0~ ~:: o~, e w, . not that is cau sed by akd ow n stre ngt
::r u~ ::~ :~ :s::~ photoresist is now de has high bre lic on inc rea ses
the film res isti
p~ ,:~ :e !~ t;; /t~ening or windows are etched in on/~ th~ CVD OJCJde at this point. Th ewhich will etch the a sm oot h interf
ace, and the oxi
itio n of oxy gen to pol ysi ng coa tin g for hig h vol
tag e
rap1dly, so that oped and the wafers are i d. ric aci d sol uti on , Po lys ilic on, Th
e add d as a pas siv ati
I e ot_ phospho sk for the CVD Ox yg en- Do ped lico n (SI PO S) is use
completely remov s not attack the CVD om~ers; m t~res1st thus serves as an etching ma ng pol ysi
ial, sem i-in sul ati film s
resulting mater n of die lec tric
nitride layer but doc serves us an etch,· x,_kc~ Ihe cph~ mt nd c lny er. on we hav e dis
cus sed dep osi tio
at im po rta nce
,
oxide, which in tur
n • ng mas ,or .. photoresistcan device s. ve des cri pti gai ned gre
d Depositions. ln PE CV D has
abo
t ct h.
a more convenienS'F ;;n g proc~ss for s con ! 11 nitride in which case ed to silicon Plasma•A.~siste itio n of the se film s usi ng osi tio n tem per atu re as its ma
jor
sm u etchin g is io 5: 1 com par CV D me tho ds.
De pos has low dep pin ho le
Th e pla 'th 1 2 etch rat using AP- and LP kno w, PE CV D od adh esi on , low
ride can be etched gas mixture with an rication. As we tie s suc h as go
be used. Silicon nit t to silicon dioxi::. a esp eci all y for VL
SI/ULSI chips fab
hav e ma ny des ira ble pro per h fin e-l ine pattern pro
ces ses .
: I wit h respec . . uring for the ore PE CV D film s
and com pal ibi lily
wit
un d 50
hc LPCV used in IC manufactducting la~er, udvunwge . Furtherm era ge, ade qua te electrical properties, n nit rid e (Si NH ) an d
ly-SJ) Deposition 1
PolyNJJlcon (Po talline silicon ~o l -S'1) fil D
method is widely d as the con density, go od step cov are pla sm a-d epo
sit ed sil ico
ma ter ial for the
Jy-Si, ~Im can be use SI tec hno log y enc aps ula tin g
dissociall~I are use ful in VL
dep osition of polyc istor by proper do . 'Y . ~ ms. P~1mP_urittcs. The poly-Si is deposited by nitrogen 1s e is use d as the
rys ve s as a
res Two materiuls which xid e. Plasma deposited sili con nit rid es excellent scratch pro tec tio n, ser 350°C,
semiconductor, or re between 5 an ::f o: ~h:~f1thfcrent s,~ane or 20 to 30% silane, diluted in al reaction pla sm a-d epo site d silicon dio
sm a-d epo site d nit rid e pro vid
tio n lcm per atu re, 30 0 10
silane ut u temperatu tem ut pressur, Of O2 ·
57 er pure ly-Si films. The che
mic
final pu.~siv111lo
n of dev ice s. Th e pla dif fus ion . Be cau se of the low dep osi s ite d nitride and ox ide are bo th
D sys to fabTJcate the po prevents sod ium on. Pla sm a-d epo
fed into the LPCV e • to I.Oto" moisture burrier, und osi lcd over tho tinul dev ice me1a/liz111lful wh en the bo tto m me tal lev el is Al
or go ld.
Is given UN the nitride can
be dcp
1lo n lev els . Th ey are use ent ma ter ial s . Th e
2Hz J between me1111/iza er are dif fer
Si ~ -- -, SJ+ by u,Jng use d us i11sula1or1 and epl lax lal lay dep osi lio n co nd
itio ns
y, the subs1ru1e
. features arc defined xy. In hc1 ero cpi 1ux lly con tro lled such
.
os1 tlon of the polycr yNta/Jine 6il /c
on lay er on the wafer, the desired of cap aci tors, resistorl,
cur cfu
Silicon ffctcrocpUa (crystollino Al 20.1) Is suc h 1hu1 un der is Is un cxo mp le of he1 ero cpi tax y. Jn
~ftcrdcp can Nerve as gate S tran.~istors plate, the impurity added of 1111pphiro u1c . Th
p n11 d 1 ico1 1-g nto MO crys111/ structure o sup phi rc subs1r
cct layers 1110 ~ cct
a mwikm g tJtc rod~tJ for 1JU d by osi ted on
ers can be con;ro/Je ///no 1111 cpi111xla/ slll
con foyer cun be dep
fu11c1, and inrcrconn stance of such lay CVD ofpo/ycrystu
ru11~c fl a : res y high vu/uos. 1110 ally over Dlayer
much like bu lk s/J/
sillc~11 IN,~ur.:~1 /Ike
r.: or, inn
th~t UIJC<l forJi; if c u;,20 oh ml
ip ~x~~~ '!'Yer.
tJqu arc up to ver
de po sition is usu
However, sin ce theh,, nd1•rtvinJL silicon but (orm61JI
 Integrated Circuits
140
. . _ 1
process the crystal 'Structure and atonuc spacing of the substrate must be very c ose m . ._
to be deposited. If this is not the case, the layer that is deposited wiJI be polycrystalline. or m some
amorphous. The equipment used for silicon heteroepitaxy are essentially identical to those use m
._
c:~s
atch to that of the layer

homoepitaxy.
Silicon-.on-sapphire (SOS) process. This process employs very thin 1 µm silicon epitaxial layer on_an
insulating sapphire substrate. This SOS structure is often used for CMOS ICs (CMOS/S0S).The insulaung
substrate results in a lower parasitic capacitance, which in turn results in higl1:-speed performance and very
Jow~power-consumption CMOS circuits.
4.12. METALLIZATION
Metallization is the final step in the wafer processing sequence. Metallization is the process by which
the components of ICs are interconnected by aluminium conductor. This process produces a thin-film metal
layer that will serve as the required conductor pattern for the interconnection of the various. components on
the chip._Aoother use of me~llization is .to produce_metalli~ed areas called bonding pads around the periphery
o~the chip to ~roduce metalh~d areas for the ~ondmg of wue lead~ from the package to the chip. The bonding
wires are typICally 25 µm diameter gold wires, and the bondmg pads are usually made to be around
l 00 µm x I 00 µm square to accommodate fully the flattened ends of the bonding wires and to allow for some
registration errors in the placement of the wires on the pads.
4. 12.1. Aluminium for Metallization
Aluminium (Al) is the most commonly used material for the metalli2.ation of most ICs discr \
and transistors. The film thickness is as about 1 µ.m and conductor widths of about 2 to 25 u~ ~m~ '- --~-1-
 - - - ··•-U'-' ... l-'.1-'lH,ClUU ll:S .

Epitax~·_The merger of single-wafer RTP and single-wafer CVD has brought continuous improvements
· us, rapi·d thenna1cVD (RTCVD) technology provides
to film. depositio
. n technology Th · a means of controlli·ng
depositio
. n processe s with tern t h · · methodo
. . . pera ure ramps rat er than by turning gas flows on and off. This logy
is called limited reaction processing (LRP), and is used in Si-epitaxy.
A~ RTP system suitable for epitaxy will look different from other RTP systems. Such technology is an
alternative to other growth methods such as PECVD, UHVCVD, and MBE.
'!11e re_qui~ements for ULSI devices include thinner epitaxial layer, better dopant profile control, and
s~lectlve .epi~axial growth. To achieve full selective growth of silicon epitaxy from dichlorosilane in conven-
u_o~al epitaxial growth system requires the addition of HCI. Under RTP, full selective, epitaxial growth
of
silicon has been observed over the temperature range from 650 to 1100°C without the addition of
HCL
Howeve_r, temperat ure control and unifonnity are the limitations of present RTP system as compare
conventional system. d to

Th~ req~irem ents for growing thin epitaxial layer over heavily doped substrate requires that autodoping
and outd1ffus1on from the substrate be minimized. RTCVD has been shown to produce intrinsic silicon
layers
grown on ,t silicon with results comparable to MBE.
Thin Film Deposition. The LPCVD, APCVD, and UHVCVD all depend on pyrolysis of source gases
at elevated temperat ure. At present LPCVD is the preferred conventional deposition technology for many
thin
films because it provides high deposition rate and excellent uniformity of film thickness. The applicatio
n of
RTP to CVD process is well suited to single wafer technology. Following are some comparison points for
the
LPCVD and RTCVD systems.
(i) In LPCVD, the chamber walls are hot and in equilibrium with the rest of the system. In
RTCVD
chamber, the walls are water-cooled,.thus eliminating deposition on the chamber walls.
(ii) The ways the deposition is initiated in the two system are different. In LPCVD, the gas flow
is turned
on and off for control, whereas in RTCVD, temperature is used for control with the gas flowing.
An importan t requirem ent for depositing SiO2layer having thickness of several thousand A is·good oxide
step coverage. Typical application requiring such thick layer are interlevel dielectric between metalliza
tion
layers and dielectric as a sidewall spacer on a polysilicon gate. For such applications RTCVD process is under
development.
Other application of oxide deposition is the deposition of thin oxide for MOS gate structure. Here the
silicon cleaning, gate oxide formation, and polysilicon gate electrode deposition, all occurs in a low-pres
sure
multi chamber cluster tool. This process would require the low temperature deposition of SiO2 as a substitute
for the preferred, thermally grown oxide. RTCVD offers a promising technology for high-quality oxide
deposition through the use of ultra clean gases in a chamber with a highly controlled ambient.
Silicon nitride deposition is used as a_mask against 02 diffusion during local oxidation, as a passivation
layer. It is also used as a gate dielectric in MOS memory transistors. The new application of nitride depositio
n
is interlevel dielectric in oxide-nitride-oxide stacked-gate structures. RTCVD system has been develope
d so
as to be suitable for nitride deposition. RTCVD is also developed for polycrystalline silicon deposition.
Such
deposition is carried out using conventional LPCVD systems. Polysilicon is used as the gate electrode material
in ULSI MOS devices. It is also useq
_ as an interconnect layer with a low-resistivity, silicide forming-metal such as titanium or cobalt.
- as polysilicon resistor in analog ICs and in static RAM chips.
 154 Integ rated Circuits

n is possible usin g RTC VD system at elev ated

temperature and
. Very smo ~t? poly ~ilic on film depo sitio I
noted that
tempex~~ur~ _~esuJts in rough surface. It should be
r:cs sure. Dep os1t10n us.1~g f:PC V~ at eJe~ at~ .th~ -~ate_ot d~position because of single-waf~r processing. \

hig h t~mp erat ure depo s1tw n is requ ired to

mctease
nnity.
es t chaJ leng e for RTC VD syst ems desi gned to .deposit poJysilicon is film thic knes s umfo
T he bigg ctric layers
found weJJ-suited to grow thin high qual ity diele
Oxi dati on. Rap id ther mal oxid atio n (RTO) is n are the more
I devi ces. The mai n issu es that ·differ-en tiate -RTO from conventional ther mal oxid atio
in ULS furnace, the desi gn of the radi atio n source, and
the
mbe r desi gn in RTO com pare d to quar tz tube
com ple x cha
id therm al processing is used
tem pera ture mea sure men t and calibration. Rap s.
- to grow diel ectr ic film s as well as to imp
art the desired chem ical or elec trica l prop ertie
devices.
- in thin -gat e diel ectr ic formation for MO S ic properties
(RT A) syst em poss ess elec trica l and diel ectr
Oxi des ann eale d in Rap id ThermaJ Ann eali ng d dielectric
para ble to or bett er than thos e of furn ace oxides. RTO oxid es seem to exh ibit imp rove
that are com ace annealing in.the
conv enti onal proc ess. RTA diff ers from furn
brea kdo wn prop ertie s ove r furn ace oxid e of in the annealing
h wafe rs are h~ated: RTA find_s app lica tion s
way the waf ers are heat ed and the rate~ at ~hic
of dop ants for Junc tion form atio n.
of ion imp lant atio n defe cts and to the d1ffus10n The ear\~
for cont acts to junc tion and gate stru ctur es.
Met alliz atio n. RTP has been wide ly appl led ired a significant
~y ~as perf orm ed in furn ace syst ems that requ
dev elop men t of seJf -aJig ne~ silic ide technoJo
n t~ avo id oxy gen con t~m atm n. RTP enab led silic ide tech nolo gy to reac h production
amo unt of atte ntio
~•~ co~~ ~• ao d shor t, high tem pera ture ann eali ng. The latte r perm its the growth of the
beca use of atmo sphe
desi red high -con duc uvit y s1hc1de phas e.
4.J3 .4. Film Deposition for VLSI
0
": in earlier section. Dielectr ic films,
i!~,~:! :1,.t! e.~~~ :lt!~~ ;~~~!~~~~~ -~~d-~~l:sili~o~_fiJ ,,. --~ "~ed as
&: , _ "