7 t Registration No. : Total number of printed pages - 3 B.Tech €S30136/ CS30106 5" SEMESTER REGULAR EXAMINATION ~ 2021 COMPUTER ORGANIZATION BRANCH: CSE/CSITICSFE/CSSE Time — 3 Hours Full Marks - 100 Answer all questions from Part — A and Part- B The figures in the right-hand margin indicate marks. PART-A . Answer the following questions: [2 x 15] (a) Differentiate between Computer Architecture and Computer Organization. (b)Consider a non-pipelined machine with 6 stages. The length of each stage is 20ns, 10ns, 30ns, 25ns, 40ns, and 1I5ns. Suppose for implementing pipelining, the machine adds Sns overhead to each stage for clock skew and set up. What is the speed-up factor for the pipelining system (ignore any hazard impact) (c) Define Memory address register and memory data register. (@ Differentiate between the temporal and spatial locality of reference. (e) Assume that for a certain processor, a read request takes 65 nanoseconds on a cache miss and 10 nanoseconds on a cache hit. Suppose while running a “program, it was observed that 70% of the processors read requests resulting in acache hit. The average and access time in nanoseconds is (f) Estimate how many 128 X 8bits RAM memory chips are required to build a RAM memory system of 128 X 16 bits? Show the arrangements with a neat diagram. (g)State micro-operation? Give an example of it. (h) Illustrate the significance of the control unit. (Write down the control sequence (steps) for a memory read operation. G)Represent (-15)10 in a signed magnitude form and One’s Complement form, (Explain underflow (arithmetic operation) condition with example. (I) Briefly explain biased exponent with example,wv 2 s . Answer any two: (m) What is the need for an interface between the I/O device and the CPU? Justify your answer. (n) Explain Direct Memory Access (DMA). (0) Differentiate between memory-mapped I/O and Isolated 1/0. PART -B Answer any two; [7x2] (a) Define pipeline hazards and their type. Consider the following code sequence having five instructions 1 to IS. 11: ADD R14, R2, R3 12: MUL R7, R14, R3 13: SUB R4, R1, RS 14: ADD R3, R2, R4 15: MUL R7, R8, RO Find and explain the types of data hazards present in the above instruction set. +4] (b) Explain different instruction formats. A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 registers, and an address part. i. How many bits are there in the operation code, the register code part, and the address part? ii, Draw the instruction word format and indicate the number of bits in each part. iii, How many bits are there in the data and address inputs of the memory? [2+6] (c) Define addressing mode. Explain any five addressing modes with an example for each. [2+5) Answer any two: (7 x2] (@) Explain virtual memory organization and its address translation mechanism using the paging technique. [3+4] (b) Explain the need for cache memory and various cache mapping methods. A 4- way set associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB. [3+4] 1. How many bits are required for addressing the main memory? I How many bits are needed to represent the TAG, SET and WORD fields? (c) What is the cache coherence problem? Consider a 4-way set associative mapping with 16 cache blocks. The memory block requests are in the order. 0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155 If the LRU replacement policy is used, which cache block will not be present in the cache? Also, calculate the hit ratio and miss ratio, [3+4] (7 x2] (@) Explain single bus CPU organization with a neat diagram, ao 2 =(b) Explain the difference between horizontal and vertical microprogrammed control units. Suppose an instruction set architecture of a general-purpose Machine has a total of 126 control signals. What is the number of bits required in the control word for horizontal and vertical micro-instruction encoding? (S+2] (c) Define micro-instruction and microprogram. Write down the control sequence (steps) to execute the instruction Add RI, R2 in a single bus architecture. B+4] . Answer the followings: (7x 2] a (a) Write short notes on IEEE 754 standards floating-point representation for both single precision and double precision. Give examples wherever required. (b) Write down Booth’s multiplication rule. Perform multiplication between (+12) and (-8) using Booth’s algorithm. [2+5] . Answer the followings: (7x 2] 2 (a) Define asynchronous data transfer. Summarize various methods to achieve the asynchronous way of data transfer, (b) Explain HDD architecture. Consider a disk pack with the following specifications- 16 surfaces, 128 tracks per surface, 256 sectors per track and 512 bytes per sector. Answer the following questions- L. What is the capacity of the disk pack? II. What is the number of bits required to address the sector? IIL. If the disk is rotating at 3600 RPM, what is the data transfer rate? [4+3] ————_ Course Outcome Assessment Scheme ; COs Questions Total Mark COT: Identify and analyze the basic structures Of @ - computer hardware units, connectivity and software. Ql(a,b), Q2Ga,e) fas CO2: Design the baste structure of machine Instruction and programs, memory location, Q1(6) Q2(b) 9 CO3: Analyze different memory in the hlerarohy, thelr mapping and their performance, QHGd, e,,.Q3 27 CO% Analyze iniernal details of @ processor, how : instructions are executed using different hardware units, | 24Gb i Q4 27 and how control unit controls all hardware components, COS: Study the design of ALU for arithmetic operations | 77 and use of registers, UGK, QS 27 C ization of secondary St ‘06: Analyze the organization of secondary storage and Qin, 0) 95 = how all the /O devices communicate with CPU and transfer data,ENTRAL | R REFERENCE BOO Registration no: le] al Total Number of Pages: 02 PCcs4301 5" Semester Regular / Back Examination 2016-17 COMPUTER ORGANIZATION BRANCH(S): CSE, FASHION, FAT, IT, ITE Time: 3 Hours Max Marks: 70 Q.CODE:Y458 Answer Question No.1 which is compulsory and any five from the rest. The figures in the right hand margin indicate marks. ai Answer the following questions: (2x 10) a) What are the basic components according to the von-Neumann architecture? b) What are the functions of a memory data register and memory address register? . c) The address range of a memory having 7 Addressing lines are from H to H. 4) Whats the function of mode signal for a adder / substractor circuit? ) What is page replacement algorithm is best and why? f) Whats seek time? g) Whatis the use of I/O processor? hh) Why refreshing circuit is required in dynamic RAM? i) Add 0.2513 x 10°& 0.02513 x 10° i) What is computer architecture? 2, a) What is computer organization? ) € b) Explain the functional units of a CPU with a suitable diagram? ®) Q3 a) Design a memory having FOUR (04) memory chips, each memory chiss (8) contains SIXTEEN (16) number of Registers and each register capacity if of 1 byte. “ b) Explain the instruction execution cycle with state diagrain, 6) Q4 a) Explain the Addition / Subtraction circuit with a suitable diagram. Find 6) the output of (+45) + (-31) by using that circuit, : b) What are'the characteristics of a cache? Draw the direct cache having (8) main miémory capacity of 24 bytes ‘and cache size of 12 bytes PageL containing each block size of 4 words,Qs Qs Q7 a) b) a) Explain about the Unconditional branch instructions with a Suitable example from each, Show how the addition pPeration is performed in a single bus organization, R2, if the operands are available in two CPU registers R1 g Write thé micro instructions for the abovs Operations, ; a) b) ce) Write short notes on any two: Virtual Memory IEEE-488 standard Cache write policies, (5) (5) (7) (3) (5) (5) (8x2)Registration no: | Total Number of Pages: Qi CENTI AL LIBRARY REFERENCE BOOK B.TECH SUBJECT CODE: PCCS4301 FIFTH [ BACK] SEMESTER EXAMINATION(NOV.-DEC.) - 2017 SUBJECT NAME ; COMPUTER ORGANIZATION BRANCH(S): CSE/IT Time: 3 Hours Max marks: 70 Answer Question No.1 which is compulsory and any five from the rest. The figures in the right hand margin indicate marks. Answer the following questions: [2x10] a) What are the different control signals is used to store a word in memory? b) What are the types of instructions? Define and differentiate between instruction interpretation and instruction execution. c) Explain Big-Endian and Little-Endian representation of data in memory. d) What is the difference between a source operand and the destination operand of an instruction? e) Ifa CPU has 32bit MAR and 16 bit MDR, and then calculate the capacity Of the RAM? f) _Whatis the seek time of a Hard Disk? 9) What do you mean by TLB? h) Define handshaking? i) What is one- address instruction format, explain with suitable example? j) Explain cache coherence, P.T.O. PCCS4301Whats an addressirig mode? Explain different types of addressing modes with example. Q2 a) b) Explain with the suitable diagram for a Von-Neuman machine structure. Q3 .a) Differentiate between Hardwired Control and Micro programmed control unit py ExPlain the virtual memory concept with 2 suitable diagram. a4 A block-set-associative cache consists of a total of 128 blocks divided a) _ into 4-blocksets.The main memory contains 4K blocks of 128 words each. (1) How many bits are there in a main memory address, and Word fields? (ii) How many bits are there in each of the Tag and Set? b) Explain multi-bus organization of a computer. Q5 a) Differentiate between CISC and RISC Architecture. b) Write the Booth’s Algorithm for multiplying two binary numbers in signed-2's complement representation and multiply 27 with -34. Q6 a) A Disk rotates at speed of 5200 RPM; it has 2000 cylinders, 16. surfaces, and 512 sectors/track, what is the average rotation delay? b) Design a 4-bit carry-look ahead fast adder and show it with a schematic diagram. Q7 a) _ Explain hor the /O devices communicate with the processor. b) Briefly describe different cache mapping techniques? as Write short notes on any two: a) Memory interleaving b) Fixed point Representation c) Virtual memory PCCS4301 15] (5) (5) 8) 5) 8) 6 i) 6 15) (5) [5x2] P.T.O.a Registration No/ College Roll No: Total Number of Pages:2 B.TECH 530136/ c530106 FIFTH SEMESTER (REG,/BACK-15/16) EXAMINATION — 2019 COMPUTER ORGANIZATION BRANCH (8): IT/CSE Time: 3 Hours Max marks: 100 Answer all Questions from Part - A and Part ~B The figures in the right hand margin indicate marks. PART=A QL. Answer the following questions: [2x15] a) Distinguish between Computer Organization and Computer Architecture. b) Explain the key functions of the following registers. IR, SP, PC, MAR ¢) Define the key concept of TLB, 4d) How the seek time of a Hard Disk is Calculated? e) Explain the disadvantages of write back policy. f) Ifa RAM has 32bit MAR and 16 bit MDR, and then calculate the capacity of the RAM. 8) Define memory interleaving. h) Explain the basic concept of pipelining. i) Write the steps to retrieve a word from a memory location by the CPU. j)lllustrate the six stages of an instruction cycle. k) Explain Zero- address instruction format, with suitable example. 1) Define interrupt vector. m) Write the different control signal is used to stored a word in memory. n) Define handshaking. 0) Explain basic components of a central Processing Unit. PART-B Q2. (Answer any two) : [7x2] a. Define addressing mode. Explain different types of addressing modes with example. b. Differentiate between CISC and RISC Architecture. c. Explain with the suitable diagram for a Von-Neumann machine structure. Q.3. (Answer any two) a. Briefly describe different cache mapping techniques, b. A block-set-associative cache consists of a total of 128 blocks divided into 4-block sets. The main memory contains 4K blocks of 128 words each, (I) How many bits are there in a maln memory address, and Word fields? (ii) How many bits are there in each of the Tag and Set? (7x2 c. Write short notes on single and multibus organization.Q.4. (Answer any two) (742) 3. Differentiate between Hardwired Control and Micro Programmed control unit. », Perform the multiplication operation between 13 and -6 by using Booth's algorithm, . Explain the virtual memory concept with a suitable diagram. (7x2) Q.5. (Answer the followings) 2. Define a micro instruction. Write the micro instruction for transferring a data from the Memory to the CPU register, » A cache memory uses two-way set associative mapping technique to do the address mapping. The cache memory can accommodate 32 MB of data where as the main memory can store? Go X 32 of data. Each block of cache memory can accommodate 256 KB of words from main memory. Explain how memory mapping.takes place and also find out the actual size of cache memory? [2] = Q.6. (Answer the followings) 2. A Disk rotates at speed of 7200 RPM; it has 4000 cylinders, 16 surfaces, 256 sectors/track, what is the average rotation delay? ». Explain the three possible modes of data transfer with neat diagram. Course Outcome Assessment Scheme: ‘COI: identify and analyze the basie structures of a computer hardware units, connectivity and software, (C01: 11% (q1.(ato)+q.2.c#24247611) C02: Design the basie structure of machine Instruction and programs, memory location. €02:22% (qi.{behe/ok}+ q.2.0¢ q.2.b=24242424747=22) C03: Analyze different memory In the hlerarchy, thelr mapping 603:32 (a1.(coesfeg}+ q3.a¢ q3.b¢q4.c49.51b9242421247474747632) ‘in (COs: Analyze Internal details ofa processor, how instructions are executed using different haravare unis, and how control unt co ind thelr performance, dy all hardware components, 604254 (qh(lom)4q.3:c4q:4.0495.0%242674747625) (COS: Study the design of ALU for athmetic operations and use ofr || cos:7% (q4.b=7) : CO6: Analyze the organization of secondary storage and how all the /0 devices communicate with CPU and transfer data, C06:20% qh.(dtlin}+9.6.040.6ENTRAL LIERAKY Total Number of Pages:2 REFERENC? BOOK Registration No/ College Roll No: | B.TECH cs30106 FIFTH SEMESTER (REGULAR) EXAMINATION (NOV.-DEC.)- 2017 COMPUTER ORGANIZATION BRANCH (S):IT/CSE Time :3 Hours Max marks : 100 ‘Answer all Questions from Part - A and Part ~B ‘The figures in the right hand margin indicate marks. PART-A Ql. Answer the following questions: [2x15] a) Distinguish between Computer Grganization and Computer Architecture. © What are the functions of following registers? IR, SP, PC, MAR a ¢) What do you mean by TLB? @) "Differentiate between RISC and CISC. e) Explain the disadvantages of write back policy. f)_ fa RAM has 32bit MAR and 16 bit MOR, and then calculate the capacity of the RAM? g) Define memory interleaving? h) Explain Little-endian and Big-endian representation in memory. i) Write the steps to retrieve a word from a memory location by the CPU. j) How many 128x8 RAM chips are needed to provide a memory capacity of 2048 bytes? Specify the size of decoder. k) Find the magnitude of the following numbers using Booth’ rule. 1144411, 1000111 1) Define paging technique in virtual memory management. @ _ m) Specify the differences between Memory mapped I/O and Isolated 1/0. rn) What is Zero- address instruction format, explain with suitable example? 0) Explain the different methods of bus arbitration. PART-B- Q2. (Answer the followings) re} a. What is an addressing mode? Why addressing mode is required? Explain different types of addressing modes with example. b. Draw and explain the schematic diagram of the basic operational concept of the processor of a computer, Explain the steps required for the execution of an instruction. [7x2] Q.3. (Answer any two) a. Why mapping function is needed in cache memory? Explain the different types of cache memory P.O, L mapping technique.b. Ablock-set-associative cache consists of a total of 128 blocks divided Into 4-block sets. The main memory contains 4K blocks of 128 words each. i. How many bits are there ina main memory address, and Word fields? ji, How many bits are there in each of the Tag and Set? c. Explain the different techniques to reduce cache miss penalty. Q.4. (Answer any two) [72] 2. Differentiate between Hardwired Control and Micro programmed control unit. b. Show how the addition operation is performed in a single bus organization if both the operands are available in registers R1 and R2. Write micro instruction for the given operation. cc. Explain the virtual memory concept with a suitable diagram. QS. (Answer the followings) [7x2] 3. Perform the multiplication operation between 13 and -6 by using Booth's algorithm. ae b. Design and explain thé working principle of Carry look ahead adder. Compare how is it fasté~ than ripple carry adder. Qs. (Answer any two) [ra] a. What is a micro instruction? Write the micro instruction for transferring a data from the Memory to the CPU register. b. Ahard disk with 1 platter rotates at 7200 rpm and has 1024 tracks, each with 2048 sectors. Disk r/ws head starts at track 0. The disk receives a request to access a random sector on a random track. If seek time of disk is 2ms for every 100 tracks it crosses. Find out Average Seek time, Average Rotational Latency and Transfer time for a sector? ¢. How performance of a computer is measured. Define the different characteristics to improve the performance of a computer. ‘Course Outcome Assessment Scheme: COI: Identify and analyze the basic structures of a computer hardware units, connectivity and software. M(a}+1(b)+1(d)+2(b)+6(c)=12% CO2: Design the basic structure of machine instruction and programs, memory location. 1(h)+1()+1(n)#1(0)+2(a)=12% COS: Analyze different memory in the hierarchy, their mapping and their performance, 1(0)#1(e)+1()+1(8)+1G)+1()+3(a)+3(b)+3(0)=28% C04: Analyze intemal details of a processor, how instructions are executed using different hardware units, and how control unit controls all hardware components, 1(n)+4(a}+4(b)+4(c)+6(a)=25% | COS: Study the design of ALU for arithmetic operations and use of registers. 1K) #5(@)+5(b) 15%Registration No: ] B.TECH Total Number of Pages: 3 CS30106 FIFTH SEMESTER (REGULAR/BACK) EXAMINATION — 2018-19 [2016 ADMISSION BATCH ONWARD] COMPUTER ORGANIZATION BRANCH (S):CSE & IT Time : 3 Hours Max marks : 100 Answer all Questions from Part - A and Part - B. The figures in the right hand margin indicate marks. ai Answer the following questions: [2x15] a) What is buffer register? How does it help in data transfer? b) Discuss different parameters of basic performance equation. ©) What is the relation between clock cycles and clock rate? d) Discuss condition code flags and what are their types? ©) What are the different types of buses used in a computer system? f) What do you mean by TLB? 9) Discuss the average access time of a hard disk. h) What do you mean by data path? i) Hows the ALU operation performs to achieve R3->R1+R2? j) Analyse how low level memory interleaving is advantageous than high level memory interleaving? k) Differentiate between Write-Back and Write-Through policies. |!) What is the seek time of a Hard Disk? m) Discuss Associative Mapping. 1) Write the steps to retrieve a word from a memory location by the CPU, ©) What are the different control signals used to store a word in memory?Q2 Q3 a4 Qs a6 a) b) b) PART B Answer any two. Draw and explain the schematic diagram of the basic operational concept of a computer. Explain the steps required for the execution of an instruction. Differentiate between RISC and SISC computers. What is their impact on Instruction Set Architecture? What is an addressing mode? Explain different types of addressing modes with examples. Answer any two. Briefly describe different cache mapping techniques. Explain the virtual memory concept with a suitable diagram. What is memory interleaving? Explain low level & high level memory interleaving techniques with examples. Answer al Write the micro instructions for the execution of the following assembly language instruction.- ADD R3, (R4) in a computer system? Explain the What is the functionality of a Control Us design procedure of hardwired control unit with necessary diagrams Answer all. Divide 522 by 37 following the restoring division algorithm. Design a 4-bit carry-look ahead fast adder with a schematic diagram. Explain the three possible modes of data transfer with neat diagrams. Assume that the disk rotates at 4000 rpm; each track of the disk has 16 sectors and each sector contains 2kb data; data transfer rate of the disk is 64 MBisecond; and average seek time of disk is 10 millisecond. Calculate the average access time for the disk. ‘What is Virtual memory? Explain virtual memory mapping using paging with suitable example. Discuss how page fault can be handled by the system? 1a) a7 a n @ m1 7 7 7 7 a 7 7Ss Registration no: Total Number of Pages: 02 B.TECH PCCS4301 FIFTH SEMESTER EXAMINATION (DEC.) — 2016-17 COMPUTER ORGANIZATION BRANCH(S): CSE/IT Time: 3 Hours Max marks: 70 Answer Question No.1 which is compulsory and any five from the rest. a a) b) °) q) é 9 hy 2 a) b) The figures in the right hand margin indicate marks. Answer the following questions: Distinguish between Computer Organization and Computer Architecture. Distinguish between based addressing and index addressing. Explain the two addressing mechanism Big-endian and Little-endian notation? What is Zero-address instruction format, explain with suitable example? What is the basic concept of pipelining? Why exponent of a floating point number is used in BIASED form? Represent the binary number 1011.1101 using IEEE single precision and double precision format. What is Cache Coherence and what are the different techniques used toachieve that? The access time of a cache memory is 200ns and the main memory access time is 1000ns. If the cache memory has a miss rate of 20%, than what is the average memory access time? If 2 RAM has 32bit MAR and 16 bit MDR, than caloulate the capacity of the RAM. Draw and explain the schematic diagram of the basic operational concept of the processor of a computer. Explain the steps required for the execution of any particular instruction in details. Discuss the basic performance equation of computer system and mention all the different factors having their impact on enhancing the formance of a computer? (2x10) (x2)— 3 a) What is the advantage of programming in assembly language instead (5 x 2) Petting in HLL? Explain different types of assembly language instructions with suitable examples. 5) What is the significance of Addressing Mode in Instruction Set Architecture? Explain at least five different addressing modes with suitable example, Q4 2) Write the Booth Algorithm and multiply 23 and -27 using Booth's (5.x 2) algorithm? b) Design a Carry Look Ahead Fast Adder with proper diagrammatic representation, Q5 a) Explain the restoring division algorithm for division of two integers with (5 x 2) an example, b) Write the IEEE format for representing floating point numbers in single Precision and double precision format. Also mention how it Tepresents the special values like 0, », Denormal Number, Not a Number. Q6 a) Acache memory uses two-way set associative Mapping technique to (5x2) do the address translation. The cache memory can accommodate 4 MB of data and the main memory size is 1 GB X 32. Each block of cache memory can accommodate 128 KB of words from main memory Explain how memory mapping takes place. b) What is Memory Interleaving? Explain low level memory interleaving with proper example and diagrammatic representation. How Low level memory interleaving is advantageous than high level memory interleaving? Q7 a) Draw and explain the single bus architecture of a processor. Write the (5x2) microinstructions for the execution of the following assembly language | ! instruction. “ | ADD (R3) , R4 b) What is Virtual Memory? Explain Virtual memory mapping technique using paging. , Qs y (5x 2) a) Distinguish between Hardwired Control Unit and Micro programmed - Control Unit. ultilevel CacheCENTRAL LIBRARY + Ce br Registration no: [ | | Total Number of Pages: 2 B.TECH PCCS4301 FIFTH SEMESTER EXAMINATION — 2016-17 COMPUTER ORGANIZATION BRANCH(S): CSE/IT Time: 3 Hours Max marks: 70 Answer Question No.1 which is compulsory and any five from the rest. at a) b) °) 4) e) 9) h) Q2 a) b) Q3 a) The figures in the right hand margin indicate marks. Answer the following questions: (2x10) What afe the five functionally independent main parts of a computer? Differentiate between Big-Endian and Little-Endian assignments? What is the seek time and response time of a hard disk? What are the functions of following registers? IR, SP, PC, MAR. Draw a 4 bit full adder. Give an example of three address, two. address, one address and zero address instructions? Write the steps for addition of floating point numbers? Discuss the average memory access time of a multi level cache system? Give four differences between RISC and SISC Instructions ? Define memory interleaving? What is addressing mode? Explain different types of addressing modes. Discuss about single bus organization of a processor with proper diagrammatic representation. tic Design a 4-bit carry-look ahead fast adder and show it with a ‘schemal diagram. Write the IEEE754 format for representing floating point number in (5) 8) 6) 6)Single precision and double precision format, Represent the binary number 11.1110 using the IEEE7S4 single precision floating point format. 4 a) Perform the multiplication operation between 32 and -26 by using (5) Booth's algorithm. ») Explain the virtual memory concept and its mapping procedure using (6) the concept of paging with a sultable diagram. QS a) Briefly describe different cache mapping techniques? (6) ») A 4 way set-associative cache consists of 4Mb of words. The main (6) memory contains 4 GB X 64 words. A block in the cache memory | contains 512 KB words. (I) Design the mapping and find out the number of bits in the different fields of the address. (ii) What is the actual size of cache memory? Q6 a) Briefly explain the micro-programmed control unit with suitable example? b) Explain the non-restoring di ion operation process with an example. Q7 a) Whatis the need to replace a page? Explain the FIFO algorithm briefly. A hard disk has 16 surfaces, 400 tracks per surface and 800 sectors per track each sector can accommodate 256 Bytes. What is the b) maximum storage capacity of the hard disk? Write short notes on any two a) Locality of reference 1/0 mapped I/O Vs Memory mapped I/O. r) ) Hardwired control unit@ Registration No. : Total number of printed pages - 3 B.Tech CS30136/ CS30106 5°” SEMESTER REGULAR EXAMINATION — 2021 COMPUTER ORGANIZATION BRANCH: CSEICSIT/CSFE/CSSE Time - 3 Hours Full Marks - 100 Answer all questions from Part - A and Part - B The figures in the right-hand margin indicate marks. PART-A . Answer the following questions: [2x 15] (a) Differentiate between Computer Architecture and Computer Organization. (b)Consider a non-pipelined machine with 6 stages. The length of each stage is 20ns, 10ns, 30ns, 25ns, 40ns, and I5ns. Suppose for implementing pipelining, the machine adds Sns overhead to each stage for clock skew and set up. What is the speed-up factor for the pipelining system (ignore any hazard impact) (c) Define Memory address register and memory data register. (d)Differentiate between the temporal and spatial locality of reference. (e) Assume that for a certain processor, a read request takes 65 nanoseconds on @ cache miss and 10 nanoseconds on a cache hit. Suppose while running a * program, it was observed that 70% of the processors read requests resulting in acache hit. The average and access time in nanoseconds is (f) Estimate how many 128 X 8bits RAM memory chips are required to build a RAM memory system of 128 X 16 bits? Show the arrangements with a neat diagram. (g)State micro-operation? Give an example of it. (h)Illustrate the significance of the control unit. (i) Write down the control sequence (steps) for a memory read operation. (Represent (-15)10 in a signed magnitude form and One's Complement form. (Explain underflow (arithmetic operation) condition with example. (\) Briefly explain biased exponent with example,v 2 (m) What is the need for an interface between the I/O device and the CPU? Justify your answer, (n) Explain Direct Memory Access (DMA). (©)Differentiate between memory-mapped I/O and Isolated 1/0, PART-B . Answer any two: (7x2] (2) Define pipetine hazards and their type. Consider the following code sequence having five instructions I1 to IS. 1: ADD R11, R2, R3 12: MUL R7, R1, R3 13: SUB R4, R1,R5 14: ADD R3, R2, Ra 15: MUL R7, R8, RO . Find and explain the types of data hazards present in the above instruction set. [3+4] (©) Explain different instruction formats. A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in oxe word of Teale coat, sttuetion has four parts: an indirect bit, an operation code, a freister code part to specify one of 64 registers, and an address part. i. How many bits are there in the operation code, the register code part, and the address part? ii Draw the instruction word format and indicate the number of bits in each part, itl, How many bits are there in the data and address inputs of the memory? [245] (c) Define addressing mode. Explain any five addressing modes with an example for each. (245) Answer any two: (7x2 (@)Explain virtual memory organization and its address translation mechanism using the paging technique, [B+4] ()Explain the need for cache memory and various cache mapping methods. A 4- Way set associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words, The word length is 32 bits. The size of the physical address space is 4 GB. B44] 1. How many bits are required for addressing the main memory? IL. How many bits are needed to represent the TAG, SET and WORD fields? (c) What is the cache coherence problem? Consider a 4-way set associative mapping with 16 cache blocks. The memory block requests are in the order- 0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 135 If the LRU replacement policy is used, which cache block will not be present in the cache? Also, calculate the hit ratio and miss ratio. [344] Answer any fwd es am ; e in single bus CPU organization with a neat diagram. (a) Explai i e f 2 Bcc6. Answer the followings: (b) Explain the difference ‘between horizontal and vertical microprogrammed control units. Suppose an instruction set architecture of a general-purpose machine has a total of 126 control signals. What is the number of bits required in the control word for horizontal and vertical micro-instruction encoding? (5+2] (c) Define micro-instruction and microprogram. Write down the control sequence (steps) to execute the instruction Add RI, R2 in a single bus architecture. [3+4] . Answer the followings: (7x2) (a) Write short notes on IEEE 754 standards floating-point representation for both single precision and double precision. Give examples wherever required. a (b) Write down Booth’s multiplication rule. Perform multiplication between (+12) and (-8) using Booth’s algorithm. [2+5] (7x2) (a) Define asynchronous data transfer. Summarize various methods to achieve the asynchronous way of data transfer. : (b) Explain HDD architecture. Consider a disk pack with the following specifications- 16 surfaces, 128 tracks per surface, 256 sectors per track and 512 bytes per sector. Answer the following questions- I. What is the capacity of the disk pack? I. What is the number of bits required to address the sector? Ill. If the disk is rotating at 3600 RPM, what is the data transfer rate? [4+3] —_— Course Outcome Assessment Scheme > cos Questions Total Mark COI: Identify and analyze the basic structures of a Q(a, b), Q2(a,6) a computer hardware units, connectivity and software. TOR Design the baste structure of machine insiruction | (6) Qa¢py 7 and programs, memory. losation — ike Hearty We] one p, ze a C03; Analyze different mem ‘mapping and their performance. Saatersoeane haw | aera a