Chapter 2: Computer-System Structures

 Computer System Operation

 I/O Structure
 Storage Structure
 Storage Hierarchy
 Hardware Protection
 General System Architecture

OS Notes by Dr. Naveen Choudhary

 Computer-System Architecture

Bootstrap:(1) Initialize h/w - like cpu registers, device controllers, memory controllers etc
( 2 ) Loads o.s kernel into the primary memory and then transfers control to O.S

OS Notes by Dr. Naveen Choudhary

 Computer-System Operation

 I/O devices and the CPU can execute concurrently.

 Each device controller is in charge of a particular device
type.
 Each device controller has a local buffer & a set of special
purpose registers
 CPU loads the appropriate registers with in the device
controller ( say for some read operation )
 I/O is from the device to local buffer of controller.
 CPU moves data from/to main memory to/from local
buffers
 Device controller informs CPU that it has finished its
operation by causing an interrupt.

OS Notes by Dr. Naveen Choudhary

 Common Functions of Interrupts

 Interrupt transfers control to the interrupt service routine

generally, through the interrupt vector, which contains the
addresses of all the service routines.
 Interrupt architecture must save the address of the
interrupted instruction.
 Incoming interrupts are disabled while another interrupt is
being processed to prevent a lost interrupt (specifically
when program counters and other registers are being
saved )
 A trap is a software-generated interrupt caused either by
an error or a user request.
 An operating system is interrupt driven.

OS Notes by Dr. Naveen Choudhary

 Interrupt Handling

 The operating system preserves the state of the CPU by

storing registers and the program counter. (disable further
interrupts, while this is being done )
 Separate segments of code determine what action should
be taken for each type of interrupt

OS Notes by Dr. Naveen Choudhary

 I/O Structure

 After I/O starts, control returns to user program only upon

I/O completion.  Synchronous I/O
 Wait instruction idles the CPU until the next interrupt
 Wait loop (contention for memory access). infinite loop
 Such infinite loop might also need to pool any i/o device
that do not support interrupt structure
 POOLING :: check for a flag (in i/o device controller) to
become true or false
 At most one I/O request is outstanding at a time, no
simultaneous I/O processing.
 After I/O starts, control returns to user program without
waiting for I/O completion.  Asynchronous I/O
 When i/o completes, the I/O device controller interrupts the
CPU to inform the CPU that it has finished it’s operation

OS Notes by Dr. Naveen Choudhary

 Two I/O Methods

Synchronous Asynchronous

OS Notes by Dr. Naveen Choudhary

 Device-Status Table
The O.S also need to be able to keep track of many i/o requests at
the same time. For this purpose the O.S uses a table containing an
entry for each i/o device. Such table entry indicates the device type,
address & status( not functioning, idle, busy)

First element in the queue : represents the request being processed

Other elements in the queue : represents the requests waiting in the
queue
OS Notes by Dr. Naveen Choudhary
 Contd…

 When i/o needs CPU attention (because it wants to start

new operation or it has completed an operation), it
interrupts
 The O.S in response to the interrupt, first determines
which i/o device raised the interrupt and then indexes into
the i/o device table accordingly
 O.s now modifies the device table entry and status
accordingly (if i/o completed – also inform the waiting
process accordingly )

OS Notes by Dr. Naveen Choudhary

 Direct Memory Access Structure

 Used for high-speed I/O devices able to transmit

information at close to memory speeds.
 Device controller transfers blocks of data from buffer
storage directly to main memory without CPU
intervention.
 Only one interrupt is generated per block, rather than the
one interrupt per byte.

OS Notes by Dr. Naveen Choudhary

 Storage Structure

 Main memory – only large storage media that the CPU

can access directly.
 Secondary storage – extension of main memory that
provides large nonvolatile storage capacity.
 Magnetic disks – rigid metal or glass platters covered with
magnetic recording material
 Disk surface is logically divided into tracks, which are
subdivided into sectors.
 The disk controller determines the logical interaction
between the device and the computer.

OS Notes by Dr. Naveen Choudhary

 Moving-Head Disk Mechanism

OS Notes by Dr. Naveen Choudhary

 Magentic Tape

 Slow
 Good for sequential access and not good for random
access
 Generally used as Backup media

OS Notes by Dr. Naveen Choudhary

 Storage Hierarchy

 Storage systems organized in hierarchy.

 Speed
 Cost
 Volatility
 Caching – copying information into faster storage system;
main memory can be viewed as a last cache for
secondary storage.
 Main memory  generally dynamic RAM, cache  static
RAM
 The program must be in main memory to be executed
because main memory is the only large storage area (in
addition to registers and cache) that the processor can
access directly

OS Notes by Dr. Naveen Choudhary

 Storage-Device Hierarchy

As we go down the level : access time increases,

cost per bit decreases, block size increases
Magnetic disk and below : non volatile
Electronic disk :nothing but large DRAM ARRAY
OS Notes by Dr. Naveen Choudhary
 Caching

 Use of high-speed memory to hold recently-accessed

data.
 Requires a cache management policy.
 Caching introduces another level in storage hierarchy.
This requires data that is simultaneously stored in more
than one level to be consistent.
 CACHE COHERENCE & CONSISTENCY
 uniprocessors systems : not a big problem
 multiprocessor systems : big problem
 cache coherence is generally a h/w issue and is
handled below the O. S. level

OS Notes by Dr. Naveen Choudhary

 Migration of A From Disk to Register

OS Notes by Dr. Naveen Choudhary

 Hardware Protection

 Dual-Mode Operation
 I/O Protection
 Memory Protection
 CPU Protection

OS Notes by Dr. Naveen Choudhary

 Dual-Mode Operation

 Sharing system resources requires operating system to ensure

that an incorrect program cannot cause other programs to
execute incorrectly. (basically provides us with the means for
protecting the O. S from errant users, and errant users from one
another
 Provide hardware support to differentiate between at least two
modes of operations.
1. User mode – execution done on behalf of a user.
2. Monitor mode (also kernel mode or system mode) – execution
done on behalf of operating system.
 Certain instruction can only be run in monitor mode
 At system boot time, the h/w starts in monitor mode. The
o.s is then loaded and starts user processes in user mode

OS Notes by Dr. Naveen Choudhary

 Dual-Mode Operation (Cont.)

 Mode bit added to computer hardware to indicate the

current mode: monitor (0) or user (1).
 When an interrupt or fault occurs hardware switches to
monitor mode.
Interrupt/fault/trap

monitor user
set user mode

Privileged instructions can be issued only in monitor mode.

OS Notes by Dr. Naveen Choudhary

 I/O Protection

 A user program may disrupt the normal operation of the

system by issuing illegal I/O instruction, by accessing
memory location within the O.S itself or by refusing to
relinquish the CPU
 To prevent users from doing illegal I/O, All I/O instructions
are privileged instructions.
 Must ensure that a user program could never gain control
of the computer in monitor mode (I.e., a user program
that, as part of its execution, stores a new address in the
interrupt vector).

OS Notes by Dr. Naveen Choudhary

 Use of A System Call to Perform I/O

OS Notes by Dr. Naveen Choudhary

 Memory Protection

 Must provide memory protection at least for the interrupt

vector and the interrupt service routines. (so that an
errant user does not get the power to work in protected
mode)
Interrupt vector
Table (in Mem) User Program -trap to
SAR4  Take address from
Service routine IVT & execute the service
address 1
Service routine (this is required to
SRA 2 Routine be done in monitor mode)
SRA 3 If user modifies SAR4
address and gives there the
SRA 4 Memo address of his program
ry then he can run his
program in monitor mode

OS Notes by Dr. Naveen Choudhary

 Contd ..

 In order to have memory protection, add two registers

that determine the range of legal addresses a program
may access: (to protect errant users from each other)
 Base register – holds the smallest legal physical memory
address.
 Limit register – contains the size of the range
 Memory outside the defined range is protected.

OS Notes by Dr. Naveen Choudhary

 Use of A Base and Limit Register

OS Notes by Dr. Naveen Choudhary

 Hardware Address Protection
300040 300040 +120900 = 420940

OS Notes by Dr. Naveen Choudhary

 Hardware Protection

 When executing in monitor mode, the operating system

has unrestricted access to both monitor and user’s
memory.
 The load instructions for the base and limit registers are
privileged instructions.

OS Notes by Dr. Naveen Choudhary

 CPU Protection

 O.S should ensure that a process is not stuck up in an

infinite loop and so will held the CPU for ever.
 Soln.
 Timer – interrupts computer after specified period to
ensure operating system maintains control.
 Timer is decremented every clock tick.
 When timer reaches the value 0, an interrupt occurs.
 Timer commonly used to implement time sharing.
 Time also used to compute the current time.
 Load-timer is a privileged instruction.

OS Notes by Dr. Naveen Choudhary