9/27/2010

Integrated Circuits
ECE481

Lecture 4

Layout
Mohamed Dessouky
Ain Shams University I.C. Lab.

M. Dessouky

ECE481 Lecture 3

Inverter: Schematic and Cross-Section

V DD M 2 Vin

Vout M 1

M. Dessouky

ECE481 Lecture 3

9/27/2010

Inverter: Wafer Cross-Section

All vertical dimensions are set by the fab. Example: Well and Diffusion Depth Poly and Metal thickness The designer has no control on layer thickness.

M. Dessouky

ECE481 Lecture 3

Inverter: Cross-Section and Mask Set

M. Dessouky

ECE481 Lecture 3

9/27/2010

Inverter: Mask Set

All horizontal dimensions are set by the designer. Only minimum dimensions and minimum spacings are set by the fab. Masks determine the circuit structure, connectivity and device dimensions.

M. Dessouky

ECE481 Lecture 3

Layout
Defines horizontal geometries that appear on the masks used in photolithography during fabrication, i.e. device dimensions. It is an important design view, prepared by the designer. In modern technologies, layout has a great impact on circuit performance. Most companies have dedicated layout teams.
ECE481 Lecture 3

M. Dessouky

9/27/2010

Inverter: Design Views

Schematic V DD M 2 V in Layout

Vout M 1

The designer is only concerned with the schematic and layout design views.
ECE481 Lecture 3

M. Dessouky

Layout Layers
Each layer corresponds to a separate photolithography mask in the target fabrication technology. It consists of a pattern of rectangular color-coded areas (boxes) defined by the fab.

Poly N+

n-transistor

Metal
M. Dessouky

Contact
ECE481 Lecture 3

9/27/2010

Layout Layers (contd.)

Fabrication uses a set of layers that are not natural for a designer:
Some of these layers are really the combination of layers a designer would like to think about. For example active is really all the diffusion layers merged together. Many of these layers can be derived from other layers. For example the select layers and the threshold adjust implants could be derived from the diffusion type and where poly crosses the diffusion So rather than working at the actual mask layers, the fab creates a set of more intuitive layers for the designers to work with.

Requires a CAD tool to generate the real mask layers for fabrication
Generating the manufacturing data is called tapeout

M. Dessouky

ECE481 Lecture 3

CMOS Process Layers: Example

Depend on the fab definition.

M. Dessouky

ECE481 Lecture 3

10

9/27/2010

Fabrication Constraints on Layout

Fabrication places many constraints on the layout. In general, there are two main types of constraints: 1. Resolution constraints What is the smallest width feature than can be printed What is the smallest spacing that will guarantee no shorts Depend on lithography and processing steps that follow 2. Alignment/overlap constraints Need to align layers to each other

Width tolerance Spacing tolerance Mask alignment

M. Dessouky ECE481 Lecture 3

11

Geometric Design Rules

A set of rules that guarantees proper transistor and interconnect fabrication despite various tolerances in each step of processing. In general, the designer determines transistor length and width, while design rules dictate most of the other dimensions. Dimensions:
Scalable design rules: All dimensions in integer multiples of Minimum line width (poly gate) = 2 When technology is scaled, only changes, all rules are scaled. Eases technology porting without the need to redraw layout Not optimum Absolute dimensions (micron rules)

M. Dessouky

ECE481 Lecture 3

12

9/27/2010

Design Rules: Minimum Width

Geometries must exceed a minimum value imposed by processing capabilities of the technology. If a rectangle is excessively narrow, it may break due to tolerances. The thicker the layer, the greater its minimum allowble width.

M. Dessouky

ECE481 Lecture 3

13

Design Rules: Minimum Spacing

On the same mask: to avoid that two paths become shorted if placed too close. On different masks: to avoid parasitic devices.

M. Dessouky

ECE481 Lecture 3

14

9/27/2010

Design Rules: Minimum Enclosure

Ensures enclosure (geometries completely inside other geometries) despite mask misalignments. Transistors surrounded by well and select masks with sufficient margin. Contacts surrounded by enough margin of both materials to be contacted.

M. Dessouky

ECE481 Lecture 3

15

Design Rules: Minimum Extension

Some geometries must extend beyond the edge of others by a minimum value. The gate polysilicon must have a minimum extension beyond the active area to ensure proper transistor action at the edge.

M. Dessouky

ECE481 Lecture 3

16

9/27/2010

Example: Intra-Layer Design Rules

M. Dessouky

ECE481 Lecture 3

17

Example: Vias and Contacts Rules

M. Dessouky

ECE481 Lecture 3

18

9/27/2010

Example: Transistor Rules

19

ECE481 Lecture 3

Example: Select Layer

20

ECE481 Lecture 3

10

9/27/2010

Vias and Contacts

Contacts only between:
Metal1 and Poly Metal1 and active area

Vias between subsequent metal layers. For example, to contact Metal3 to the poly, the following masks should be used: Poly-C-M1-V1-M2-V2-M3 The higher the metal level, the thicker the metal, and the lower the sheet resistance.

M. Dessouky

ECE481 Lecture 3

21

Layout Example: CMOS Inverter Layout

M. Dessouky

ECE481 Lecture 3

22

11

9/27/2010

Layout Example: 2-input NAND gate

VDD

M3
B

M4
Out

M2
A

M1

Identify each transistor and each node

ECE481 Lecture 3

23

CAD Tool: Layout Editor

Build the layout of all building blocks Integrate all building blocks into the final sub-system layout Edit layers:
Add Remove Cut Copy Paste Resize

ECE481 Lecture 3

24

12

9/27/2010

CAD Tool: Design Rule Checker (DRC)

To ensure that the layout meets the geometric design rule constraints.

poly_not_fet to all_diff minimum spacing = 0.14 um.

ECE481 Lecture 3

25

Layout-versus-Schematic (LVS) Checker

To ensure that the layout devices (dimensions) and connectivity have a one-to-one correspondence with the design netlist.

V DD Compare Vin M 2

Vout M1

M. Dessouky

ECE481 Lecture 3

26

13

9/27/2010

LVS: Operation
Extracted Netlist

Extract

Layout

Compare
No Design Netlist

Yes

End

Debug

ECE481 Lecture 3

27

CAD Tool: Parasitic Extraction

Extract the Real netlist + parasitics (RC) from the layout.
Extracted Netlist + Parasitics (RC)

Extract with Parasitics

Layout

This is usually followed by a post-layout simulation to make sure that added layout parasitics did not alter the required circuit performance.

ECE481 Lecture 3

28

14

9/27/2010

Designer-Foundry Relation

In order to implement an ASIC, the designer has to choose

An appropriate technology with required speed A fabrication house (Foundry) with required cost

M. Dessouky

ECE481 Lecture 3

29

Designer-Foundry Relation

and to use EDA tools.

EDA Tools

M. Dessouky

ECE481 Lecture 3

30

15

9/27/2010

Designer-Foundry Relation

EDA Tools

Design Libraries Design Kit Compatible with the EDA Tools

M. Dessouky

ECE481 Lecture 3

31

Foundry Deliverables
Design Libraries digital building blocks (cell-based)
A physical layout Models: behavioral, Verilog/VHDL, detailed timing model A test strategy A circuit schematic and cell icon A routing model Schematic Symbols (Full-Custom) Device Models (Full-Custom Simulation) Device Layout Generator (Full-Custom) Design Rules (Verification)

Design Kit

M. Dessouky

ECE481 Lecture 3

32

16

9/27/2010

Designer-Foundry Relation

Layout Masks (Tapeout)

EDA Tools

Design Libraries Design Kit

M. Dessouky

ECE481 Lecture 3

33

Designer-Foundry Relation

Layout Masks (Packaged) Chips

EDA Tools

Design Libraries Design Kit

M. Dessouky

ECE481 Lecture 3

34

17

9/27/2010

Links
CAD Companies
Mentor Graphics: http://www.mentor.com/ Synopsys: http://www.synopsys.com/ Cadence: http://www.cadence.com/

Free design tools

Electric VLSI Design System http://www.staticfreesoft.com/index.html Magic VLSI Layout tool http://opencircuitdesign.com/magic/ Microwind http://www.microwind.net/index.php

35

Your Initials, Presentation Title, Month Year

ECE481 Lecture 3

References
Rabaey, sections 2.3 & 2.4

M. Dessouky

ECE481 Lecture 3

36

18