UNIT 3

MS. V D NAGRALE
T E ELECTRONICS
FUNDAMENTALS OF HDL

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 NEED OF PLDs
 INTRODUCTION OF PLDs
 CPLD
 FPGA
 PROGRAMMABLE INTERCONNECT
 COMPARISION BETWEEN CPLD AND FPGA

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 Ease of design
 Low development cost
 Fast time to market
 Higher product revenue
 Reduced board area
 Low cost
 Cost of ownership
 Reliability

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WORLD OF INTEGRATED CIRCUITS

FULL- SEMI –
USER
CUSTOM CUSTOM PROGRAMMABLE
ASICs ASICs

PLD
FPGA

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 Programmable Logic Arrays (PLAs) were a
solution to the speed and input limitations of
PROMs.
 PLAs consist of a large number of inputs
connected to an AND plane, where different
combinations of signals can be logically ANDed
together according to how the part is
programmed.
 The outputs of the AND plane go into an OR
plane, where the terms are ORed together in
different combinations and finally outputs are
produced.

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 The Programmable Array Logic (PAL) is a
variation of the PLA. Like the PLA, it has a
wide, programmable AND plane for ANDing
inputs together.
 The OR plane is fixed, limiting the number of
terms that can be Ored together.
 Other basic logic devices,such as Multiplexers,
exclusive ORs, and latches are added to the
inputs and outputs.

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ANTIFUSE METHOD

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Generic Logic Array

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 FEATURES
 Some of the CPLD features are in common with
PALs:
 Non-volatile configuration memory. Unlike many
FPGAs, an external configuration ROM isn't
required, and the CPLD can function immediately
on system start-up.
 For many legacy CPLD devices, routing constrains
most logic blocks to have input and output signals
connected to external pins, reducing opportunities
for internal state storage and deeply layered logic.
This is usually not a factor for larger CPLDs and
newer CPLD product families.
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 Other features are in common with FPGAs:
 Large number of gates available. CPLDs typically have the
equivalent of thousands to tens of thousands of logic gates,
allowing implementation of moderately complicated data
processing devices.
 PALs typically have a few hundred gate equivalents at most,
while FPGAs typically range from tens of thousands to several
million.
 Some provisions for logic more flexible than sum-of-product
expressions, including complicated feedback paths between
macro cells, and specialized logic for implementing various
commonly used functions, such as integer arithmetic.
 The most noticeable difference between a large CPLD and a small
FPGA is the presence of on-chip non-volatile memory in the
CPLD.
 The characteristic of non-volatility makes the CPLD devices used
in modern digital designs for performing "boot loader" functions
before handing over control to other devices not having this
capability.
 A good example is where a CPLD is used to load configuration
data for an FPGA from non-volatile memory.

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 CPLD is an erasable programmable device
based on EPROM or EEPROM technology.
 Basic CPLD cell is called as macrocell, which is
implementation of CLB (Configurable Logic
Block).
 CLB composed of AND array surrounded by
interconnect area.
 CPLDs may be thought of as multiple
interconnected SPLD’s.
 SPLD block called a logic block is based on
PAL/PLA, macrocell, I/O structureetc.

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NO. OF
FUNCTION
BLOCKS

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 User programmable Ground facility
enables users to declare any I/O pin
as ground. If unused I/O pins are
grounded the interference (RFI/EMI)
noise is minimized.
 Slew Rate is user programmable.
Lowering the slew rate enables user to
reduce ringing& noise effect.

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 Cheap/fast fuse connections
◦ small area (can fit lots of them)
◦ low resistance wires (fast even if in multiple
segments)
◦ very high resistance when not connected
◦ small capacitance (wires can be longer)
 Pass transistors (switches)
◦ used to connect wires
◦ bi-directional
 Multiplexors
◦ used to connect one of a set of possible sources to
input
◦ can be used to implement logic functions

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 Fuse and anti-fuse
◦ fuse makes or breaks link between two wires
◦ typical connections are 50-300 ohm
◦ one-time programmable
 Flash
◦ High density
◦ Process issues
 RAM-based
◦ memory bit controls a switch that
connects/disconnects two wires
◦ typical connections are .5K-1K ohm
◦ can be programmed and re-programmed easily
(tested at factory)

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 FPGA is concept of SOG (Sea of gates).

 SRAM/Antifuse/Flash based architecture.

 The building blocks – CLB, GRM and I/O cells.

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 Logic block - how are functions implemented: fixed
functions (manipulate inputs) or programmable?
◦ support complex functions, need fewer blocks, but they are
bigger so less of them on chip
◦ support simple functions, need more blocks, but they are
smaller so more of them on chip
 Interconnect
◦ how are logic blocks arranged?
◦ how many wires will be needed between them?
◦ are wires evenly distributed across chip?
◦ programmability slows wires down – are some wires
specialized to long distances?
◦ how many inputs/outputs must be routed to/from each
logic block?
◦ what utilization are we willing to accept? 50%? 20%? 90%?

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 CLB - Configurable Logic Block
◦ 5-input, 1 output function
◦ or 2 4-input, 1 output functions
◦ optional register on outputs IOB IOB IOB IOB

 Built-in fast carry logic

IOB
 Can be used as memory
 Three types of routing CLB CLB

IOB
◦ direct
◦ general-purpose Wiring Channels
◦ long lines of various lengths
IOB

 RAM-programmable
◦ can be reconfigured CLB CLB
IOB

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 Symmetrical Array
 Row based
 SOG
 Hierarchical PLD

 FPGA is a SRAM based volatile structure, it can be

reconfigured by making power off and use of
EPROM. Hence it is called as field programmable.

 FPGA Vendors Xilinx with Virtex & Spartan,

Actel, Altera, Cyprus, AT&T, Quick Logic.

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XC5200 family consists of
programmable IOBs, logic blocks
and interconnect.

It consists of m by n matrix of
versa blocks. Each versa block
consists of CLB. Each CLB
consists of 4 logic cells.Each
logic cells consists of function
generators /look up table and D
flip-flop.

General-purpose routing
connects to the Versa Block
through the General Routing
Matrix (GRM).
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Function generator (F) delivers any COMBO function. It has
input F1 - F4. Carry input (C1) & Carry output (CO) are
important in arithmetic operation like look ahead carry
generator.D flip-flop (FD) can be clocked by global CLOCK (CK)

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SPARTAN-II
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 Some wires will not be utilized.
 Congestion will not be same
throughout chip.
 Types of wires:
◦ –Short wires: local LE connections.
◦ –Global wires: long-distance, buffered
communication.
◦ –Special wires: clocks, etc.

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Offset segments

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 INTERCONNECT
 Types of interconnect
◦ –local;
◦ –general-purpose;
◦ –dedicated;
◦ –I/O pin.

General-purpose network
 Provides majority of routing resources
◦ –General routing matrix (GRM) connects horizontal/vertical
channels and CLBs.
◦ –Interconnect between adjacent GRMs.
◦ –Hex lines connect GRM to GRMs six blocks away.
◦ –12 longlines span the chip.

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 Antifuse FPGAs:
– Devices are configured by burning a set of
fuses.
– Once the chip is configured, it cannot be
altered any more.
– Bug fixes and updates possible for new
PCBs, but hardly for already manufactured
boards.
– ASIC replacement for small volumes.

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 Flash FPGAs devices:
– may be re-programmed several thousand
times and are nonvolatile,
– keep their configuration after power-off
with only marginal additional effort,
– the chips may be updated in the field
– expensive
– re-configuration takes several seconds

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 SRAM FPGAs:
– currently the dominating technology
– unlimited re-programming
– additional circuitry is required to load the
configuration into the FPGA after power-on
– re-configuration is very fast, some devices
allow even partial reconfiguration during
operation

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CPLD FPGA
Function Block Versa Block
Macro Cell Logic Cell
Product Term Allocator Function Generator (LUT)
D/T FF D FF
Local/Global CLK Global CLK
Implementation using gates using memory
Gates connectivity is configured Memory is programmed
Not good for math Operations good for all operations
Not rich in interconnects rich

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CPLD
Delays are predictable
Normally non volatile
Low gate count
Does not need boot
Good for space applications
Low density & pin count
Not so many evolutions
FPGA
may not be predictable
Normally volatile (except Actel)
High cell count
needs (except Actel)
not good (except Actel)
high
many (almost every 6 months)
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