B.

Tech (ECE) (III-Year/ VI-Semester)

Continuous Assessment Test-2, March-2022
DIGITAL VLSI SYSTEM DESIGN– U19ECT62
Day and Date: Section:B
Time: 09.00 AM to 10.40AM Max. Marks- 50
Instructions:
IMP: Verify that you have received question paper with correct course, code, branch etc.
i) All questions are compulsory.
ii) Figure to the right indicate full marks.
iii) Assume suitable data wherever necessary.
Course Outcomes:
CO2: Discuss about the different combinational and sequential logic blocks
CO3: Describe the terms and keywords in Verilog HDL.
Knowledge Level:K1–Remember,K2–Understand,K3–Apply,K4–Analyze,K5–Evaluate&K6-Create
Mark CO’
B.L
s s
PART A (10 Marks)
Answer all the Questions
Q.1 2 K2 CO
Write a truth table of priority encoder?
2
Q.2 2 K3 CO
Differentiate Moore and Mealy model with neat block diagram
2
Q.3 In the coding given below, fill the keyword needed in line no.2 2 K2 CO
3
Line No. Verilog code
1 module gate (input a, input b, output sum, output
carry);
2 ____ (sum,a,b);
3 assign carry = a&b;
4 endmodule
Q.4 What are the key functions of Programming Language Interface 2 K2 CO
(PLI). 3
Q.5 2 K3 CO
What is the use of the keyword “PARAMETER “ in Verilog HDL?
3
PART B (20 Marks)
Answer all the Questions
Design a shift register where “1011” can be loaded at 0th clock 5 K3 CO
cycle and outputs are taken as shown below 2
Clock Q
Q.6 1 1
2 1
3 0
4 1
With a neat logic diagram and truth table explain 5 K3 CO
Q.7 i) D Flip flop 2
ii) JK Flip flop
5 K2 CO
Q.8 Write in detail about module and its port types
3
Q.9 Explain the following language constraints with example in 5 K3 CO
Verilog HDL 3
 i) Keywords
ii) Identifiers
iii) White Space Characters

PART C (20 Marks)

Answer any two Questions
Q.1 Design a decade counter in which all the flip-flops will have 10 K3 CO
0 common clock signal. 2
Q.1 Explain in detail about simulation and synthesis with the help of 10 K3 CO
1 Vivado 2014.4 3
Q.1 10 K3 CO
What are the Levels of design description in Verilog?
2 3