Scribd Logo
Upload

Welcome to Scribd!

  • 18-Width and Resistance Calculation of PMOS and NMOS in CMOS Logic-03!02!2022 (03-Feb-2022) Material - I - 03!02!2022 - 12a. - Width - Calculation - of

    Uploaded by

    Aniket Ranjan
    20 views8 pages
    The document discusses calculating the widths of PMOS and NMOS transistors in CMOS logic gates to equalize pull-up and pull-down resistances (R). For an inverter, the PMOS width (Wp) is set to 2 times the NMOS width (Wn) to make Rp=Rn. For a 2-input NAND gate, Wp remains 240n while Wn is doubled to 240n/2 to account for the doubled pull-down path. A 3-input NAND uses Wp of 240n and Wn of 3×120n/3. A 3-input NOR has Wp of 3×(2×120n)/3 and Wn of 120

    Original Description:

    Original Title

    18-Width and Resistance Calculation of PMOS and NMOS in CMOS Logic-03!02!2022 [03-Feb-2022]Material_I_03!02!2022_12a._width_calculation_of

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    The document discusses calculating the widths of PMOS and NMOS transistors in CMOS logic gates to equalize pull-up and pull-down resistances (R). For an inverter, the PMOS width (Wp) is set to 2 times the NMOS width (Wn) to make Rp=Rn. For a 2-input NAND gate, Wp remains 240n while Wn is doubled to 240n/2 to account for the doubled pull-down path. A 3-input NAND uses Wp of 240n and Wn of 3×120n/3. A 3-input NOR has Wp of 3×(2×120n)/3 and Wn of 120

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    20 views8 pages

    18-Width and Resistance Calculation of PMOS and NMOS in CMOS Logic-03!02!2022 (03-Feb-2022) Material - I - 03!02!2022 - 12a. - Width - Calculation - of

    Uploaded by

    Aniket Ranjan
    The document discusses calculating the widths of PMOS and NMOS transistors in CMOS logic gates to equalize pull-up and pull-down resistances (R). For an inverter, the PMOS width (Wp) is set to 2 times the NMOS width (Wn) to make Rp=Rn. For a 2-input NAND gate, Wp remains 240n while Wn is doubled to 240n/2 to account for the doubled pull-down path. A 3-input NAND uses Wp of 240n and Wn of 3×120n/3. A 3-input NOR has Wp of 3×(2×120n)/3 and Wn of 120

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    of 8

    CMOS LOGIC

    R1  1
    l 1   2  R1  R2
    a
    l But We have to make it R1 = R2
    R2   2
    a
    a(Cross Sectional Area)
    is dirctionaly propotional to w ( width)

    w a  R 

    Generally to make R p  Rn
    We set W p as 2 to 3 times of Wn
    Width Calculation for a single CMOS
    Inverter
    We assume, W p  2Wn
    to make R p  Rn

    W p  2 120n  240n

    Wn 120n
    Width Calculation for a 2 input NAND
    Gate
    Clue :
    Resistance of Pull up Path of the Circuit  Resistance of Pull up Path of a CMOS Inverter
    Resistance of Pull down Path of the Circuit  Resistance of Pull down Path of a CMOS Inverter
    Wp  240n, R

    W p  240n, R
    W p  2 120n  240n, R

    Wn 120n, R
    Wn 120 n, R
    Wn 120 n, R

    Here pull down path Resistance


    is 2R, but We need R only.
    Width Calculation for a 2 input NAND
    Gate
    Clue :
    Resistance of Pull up Path of the Circuit  Resistance of Pull up Path of a CMOS Inverter
    Resistance of Pull down Path of the Circuit  Resistance of Pull down Path of a CMOS Inverter
    Wp  240n, R

    W p  240n, R
    W p  2 120n  240n, R

    Wn  2 120n, R / 2
    Wn 120 n, R
    Wn  2 120 n, R / 2
    DESIGN A 3 INPUT NAND GATE USING
    CMOS LOGIC
    Wp  240n, R Wp  240n, R

    Wp  240n, R

    Wn  3120n, R / 3

    Wn  3120 n, R / 3

    Wn  3120 n, R / 3
    DESIGN A 3 INPUT NOR GATE USING
    CMOS LOGIC

    W p  3 (2 120n)  720n, R / 3
    Wp  3 (2 120n)  720n, R / 3

    Wp  3 (2 120n)  720n, R / 3

    Wn 120 n, R

    Wn 120 n, R
    Wn 120 n, R
    Compound Gate

    Wp  3 (2 120n)  720n, R / 3
    Wp  3 (2 120n)  720n, R / 3
    Wp  3 (2 120n)  720n, R / 3

    Wp  240n, R

    Wn  2 120 n, R / 2

    Wn  2 120 n, R / 2

    Wn  2 120 n, R / 2 Wn  2 120 n, R / 2
    Determine width of each transistor
    A XOR B = A XNOR B

    You might also like