S19 Warning :

Statement : Nonscan DFF

u_leo_ddr0_u_leo_ddr_phy/u_dwc_ddrphy_top_u_DWC_ddrphy_pub/MRTUB/dwc_ddrphy_apb2cfg_d
wc_ddrphy_apbfifo_u_fifo_fifo_reg_1__44_ disturbed during time 0 of load_unload procedure.

Cause: Cell is not able to hold its value. Nonscan cells must hold their state during the application of the
load_unload procedure.

Cell name: u_leo_ddr1_u_leo_ddr_apb_dec_u_leo_apb_cdc_ddr_phy_dst_pslverr_r_reg

Source: u_leo_ddr1_u_leo_ddr_clk_div2_u_HAND_GATE_SDFQD2BWP240H8P57PDLVT

Cell name : u_leo_cxl_phy/pipe_pcs_pipe_ctl_inst_lane15_pwr_ctl_lane_off_refclk_snapshot_reg

Mux Cell name:

u_leo_cxl_phy/pipe_pcs_upcs_clk_ctl_clk_ctl_15__phy_ref_dig_clk_mux/clk0123_mux/
gen_clk_en_11_clk01_mux/U3

Proposed solution: to hold the data we made clock to zero such that non scan cell hold data in shift
mode. This reduces the S19 violation but increases C16 violation.

S29 Warning:

Statement: Dependent slave

u_leo_ddr0_u_leo_ddr_phy/u_dwc_ddrphy_top_u_DWC_DDRPHYDBYTE_8/rx_data_fifo_2/
I_wre_ptr_b3 may not hold same value as master
u_leo_ddr0_u_leo_ddr_phy/u_dwc_ddrphy_top_u_DWC_DDRPHYDBYTE_8/rx_data_fifo_2/
RETIMING_FLOP1

Cause: This violation arises due to the wrong polarity on clock of slave, on back tracing the clock is
coming from JTAG_TCK with some combinational logic which makes this clock of wrong polarity due to
which positive edge slave is not able to hold master’s value.

C2 Warning:

Statement: Clock PIs off did not force off clock input 2 of nonscan DFF
u_leo_ddr1_u_leo_ddr_phy/u_dwc_ddrphy_top_u_DWC_ddrphy_pub/MRTUB/dwc_ddrphy_apb2cfg_d
wc_ddrphy_apbfifo_u_fifo_fifo_reg_3__44_

Cause: This violation arises when tool is not able to force this cell’s clock off in clock off mode . On
analyzing the clock off cell we have found that the clock is internally generated .

Cell name:
u_leo_ddr1_u_leo_ddr_phy/u_dwc_ddrphy_top_u_DWC_ddrphy_pub/MRTUB/dwc_ddrphy_apb2cfg_d
wc_ddrphy_apbfifo_u_fifo_fifo_reg_3__44_
Source: u_leo_ddr1_u_leo_ddr_clk_div2_u_HAND_GATE_SDFQD2BWP240H8P57PDLVT

Cell name: DFF u_leo_ddr1_u_leo_ddr_apb_dec_u_leo_apb_cdc_ddr_phy_dst_pslverr_r_reg

Source : u_leo_ddr1_u_leo_ddr_clk_div2_u_HAND_GATE_SDFQD2BWP240H8P57PDLVT

Proposed solution : Clock should not be internally generated .It should be controllable from the top
level.

C3 Warning:

Statement: Clock PIs off failed to allow transparency of nonscan DLAT

u_leo_cxl_ctr1/u_leo_cxl_ctr_sms_proc_U_leo_cxl_ctr_sms_processor_dwsms_async_rst_rst_slow_syn
c_dwsms_async_rst_r_reg_0_

Cause: The clock in the given cell is tied to 0 which leads to not capturing of data

Cell name:
u_leo_cxl_ctr1/u_leo_cxl_ctr_sms_proc_U_leo_cxl_ctr_sms_processor_dwsms_async_rst_rst_slow_syn
c_dwsms_async_rst_r_reg_0_

Proposed solution: Clock should not be TIE0 it should be pulsed.

C5 Warning:

Statement: Clock JTAG_TCK can capture new data on LS input 2 of DLAT

u_leo_cxl_ctr1/ckr_u_clk_rst_u_clk_gate_dft_coreclk_gated_ckgt

Source of violation: input 2 of DFF

u_leo_cxl_ctr1/cfg_csr_csr_internal_field_pm_en_core_clk_ovr_cfg_reg

Cause: A clock must not capture data into a level sensitive (LS) port (latch or RAM) if that data might be
affected by new captured data.
Cell name : u_leo_cxl_ctr1/ckr_u_clk_rst_u_clk_gate_dft_coreclk_gated_ckgt

C6 Warning:

Statement: Clock JTAG_TCK can capture new data on TE input 2 of DFF

u_leo_ddr1_u0_ddr_tap_u_tap_U1_U7 (C6-1)

Source of violation: input 2 of DFF u_leo_ddr1_u0_ddr_tap_u_tap_U1_current_state_reg_4_

Cause : A clock must not capture data into a trailing edge (TE) port if that data might be affected by new
captured data.

Cell Name: u_leo_ddr1_u0_ddr_tap_u_tap_U1_U7

Source Name: u_leo_ddr1_u0_ddr_tap_u_tap_U1_current_state_reg_4_

C8 Warning:

Statement : JTAG_TCK clock path affected by new capture on LS input 2 of DLAT

u_leo_ddr0_u_leo_ddr_phy/u_dwc_ddrphy_top_u_DWC_DDRPHYACX4_11/zPclkdatclkdrv/
DbyteGater/ILATCH

Source of violation: input 2 of DLAT

u_leo_ddr0_u_leo_ddr_phy/u_dwc_ddrphy_top_u_DWC_DDRPHYMASTER_top/clktree_master/
I_GatePclkC1/ILATCH .

Cause: Clock path affected by new capture .Some clocks are coming from RESET_N and some from
JTAG_TCK.
Cell name: u_leo_ddr0_u_leo_ddr_phy/u_dwc_ddrphy_top_u_DWC_DDRPHYACX4_11/zPclkdatclkdrv/
DbyteGater/ILATCH

Source name:
u_leo_ddr0_u_leo_ddr_phy/u_dwc_ddrphy_top_u_DWC_DDRPHYMASTER_top/clktree_master/
I_GatePclkC1/ILATCH

Proposed solution: We have analyzed RESET_N and we have found that it is not used as a clock
anywhere in the design and we have removed it from the clock definitions in the spf. By removing the
C26 violation this also gets reduced.

C9 Warning:

Statement: JTAG_TCK clock path affected by new capture on TE input 2 of DFF

u_leo_ddr0_u_leo_ddr_phy/u_dwc_ddrphy_top_u_DWC_DDRPHYDBYTE_9/rx_data_fifo_8/I_qv_b0

Source of violation: input 2 of DLAT

u_leo_ddr0_u_leo_ddr_phy/u_dwc_ddrphy_top_u_DWC_DDRPHYDBYTE_9/rx_data_fifo_8/I_WClk0

Cause: The path from a clock to a trailing edge port must not be affected by its new captured data.
Cell name: u_leo_ddr0_u_leo_ddr_phy/u_dwc_ddrphy_top_u_DWC_DDRPHYDBYTE_9/rx_data_fifo_8/
I_qv_b0

C16 Warning:

Statement: Clock input 2 of nonscan DLAT

u_leo_cxl_ctr1/u_leo_cxl_ctr_sms_proc_U_leo_cxl_ctr_sms_processor_dwsms_async_rst_rst_slow_syn
c_dwsms_async_rst_r_reg_0_ cannot capture data

Cause: This violation arises as the cell is getting 0 value on the clock ,when we back trace the clock we
have found that it is connected to TIE0.

Cell name:
u_leo_cxl_ctr1/u_leo_cxl_ctr_sms_proc_U_leo_cxl_ctr_sms_processor_dwsms_async_rst_wrstn_sync_
dwsms_async_rst_r_reg_0_
Proposed solution: We were getting 0 on the clock port so we pulsed the clock.

C25 Warning:

Statement: Input 2 of unstable DLAT (50452754) connected from DFF and DLAT

Cause: Clock is internally generated coming from different sources

Sources:

Source 1 name: u_leo_ddr0_u_leo_ddr_phy/u_dwc_ddrphy_top_u_DWC_DDRPHYMASTER_top/PLL/pll

Source 2 name:
u_leo_ddr0_u_leo_ddr_phy/u_dwc_ddrphy_top_u_DWC_DDRPHYMASTER_top/clktree_master/
I_GatePclkC1/ILATCH

C26 Warning:

Statement: Warning: Clock RESET_N used as data is different than capture clock JTAG_TCK for inputs 2/3
of stable DFF
Cause: Clock RESET_N used as data is different than capture clock.

Cell name: u_leo_cxl_ctr1/csr_u_cxl_cntl_apb_sm_agent_csr_write_access_reg

Possible solution: We have analyzed RESET_N and we have found that it is not used as a clock anywhere
in the design and we have removed it from the clock definitions in the spf.