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110 (2) Semi Phys Devices - CH3 Prof JCGuo
110 (2) Semi Phys Devices - CH3 Prof JCGuo
Physics and Devices
半導體物理與元件
Chapter‐3
MOSFET and MOS Capacitors
CMOS Device Structure
Basic Features of MOSFET
MOSFET Fundamentals
MOS Capacitors
Threshold Voltage (VT) Model
Four terminal devices
Typical layout
Fabrication steps
CMOS circuits and symbols
/As
Pre‐gate doping (P31/As75)
Hard mask
BARC (TEOS/SiN)
Composite
spacer
TEOS/SiN/TEOS
Silicidation
TiSi2, COSi2, NiSi
4‐terminal devices
2022 Sem. Physics & devices Prof. J.C. Guo, 郭治群教授 9
Basic Features of MOSFETs
Capacitance
Equivalent circuit : DC model
Equivalent circuit : dynamic model
MOSFET device model approach
Gate to accumulation layer at off‐state
IG effect on IDS :
worse for long‐channel
devices
RG effect :
C‐V depletion (IG & RG )
fmax, Thermal noise
Parasitic RLC in 4‐terminal devices
Rg, Rs, Rd, Rb, Lg, Ls, Ld, Lb
Ideal MOS Band Diagram (zero ms)
Actual MOS Engery Band Diagram
non‐zero ms
‐ Thermal equilibrium
‐ Accumulation
‐ Depletion
‐ Inversion
Surface carrier density
m ox B
Eg
s s Bp
2q
Eg
ms m s Bp
2q
Eg
Bp p
2q
Eg
ms m s p
q
(8.8eV)
(4.5eV)
s B
p
MOS Capacitor C‐V Characteristics
MOS C‐V defined Threshold Voltage
Poly‐Si gate effect
Inversion layer quantization effect
MOSFET VT model : geometry effects
p (x)
E i ( x ) E i ( )
q
q p ( x ) q p ( x )
pp ( x ) pp 0 e kBT
N Ae kBT
q p ( x ) 2 q p ( x )
ni
np ( x ) np 0e kBT
e kBT
NA
S p ( x 0)
Ei ( x 0) Ei ( )
surface potential
q
q S
pp ( x 0) pp 0e kBT
q S
np ( x 0) np 0e kBT
q p ( x )
np ( x ) np 0e kBT
q
q p ( x )
d 2 p q p ( x )
pp 0 e kBT
1 np 0 e kBT
1
dx 2 si
q pp 0 1
2 si L D
2
then ( x )
surface electric field
s ( x 0)
surface space charge
Qs si s
np 0
2
n
np 0 S np 0
F S , S 1 S 1 , i
e S
e
p p0 p p0 pp 0 NA
At flatband S 0 Qs ( S 0)
kBT N A
Weak inversion B S 2 B , B n
q ni
e B e S e 2 B
e 2 B e S e B
B S 2 B
e S e 2 B
S 2 B
S 2 B
S np 0 S
1 e e 1
dQs si pp 0
CD
d S 2LD np 0
F S ,
p
p0
si
CFB CD S 0 Flatband capaci tan ce
LD
S
Example for the n‐substrate
• Electrons are attracted to the n‐substrate surface
• Small signal capacitance per unit area is given by
OX
COX
tOX
OX kOX 0
0 8.854 1014 F / cm : permitivity in the air
kOX : dielectric constant of oxide
tOX : oxide thickness
2022 Sem. Physics & devices Prof. J.C. Guo, 郭治群教授 40
MOS Capacitor C‐V Characteristics
Depletion : VG < 0 (n‐type substrate)
• Electrons are repelled from the n‐substrate surface
• Small signal capacitance per unit area is given by
1 1 1 COX Cd
C
C COX Cd COX Cd
Si
Cd
xd
Si kSi 0
kSi : dielectric constant of silicon
2022 Sem. Physics & devices xd : depletion layer width Prof. J.C. Guo, 郭治群教授 41
MOS Capacitor C‐V Characteristics
Inversion : VG < VT < 0 (N‐type substrate)
• Holes (inversion carriers) pile up at oxide/Si interface
• Under strong inversion
‐ Xd,max = maximum depletion layer width
‐ Cdmin=Cd(Xd=Xd,max)
• For VG in depletion ~weak inversion
‐ Xd a VG1/2
EOX
VOX
Q
qND xd 2 2 si | s |
s xd
2 si qND
ND
s @(VGS VT ) 2 Fn 2T n
i
n
2 si ND
xd ,max xd ( s 2 Fn ) 2T n
qND i
n
si T
ND
2 n
qND i
n
Generally, inversion carriers must be treated quantum
mechanically (QM) as a 2D gas. According to QM model
• inversion layer carriers occupy discrete energy bands
• peak distribution is around 10~30A away from the surface
2022 Sem. Physics & devices Prof. J.C. Guo, 郭治群教授 47
MOS C‐V Defined VT
( )
near Co
Eg NA
N poly -gate / p-Si substrate : ms T n
2q i
n
Eg ND
P poly -gate / n -Si substrate : ms T n
2q i
n
2D electron gas
confined in QW
Short Channel Effect
Reverse Short Channel Effect
DIBL effect
Narrow Width Effect
Inverse Narrow Width Effect
rj xd
or QB ' | VT |
L rj
The drain bias lowers the potential
barrier between source and channel,
and hence increases the current
In principle, it is possible to derive an
analytical model to estimate Dfs as a
function of L and VD. However, a
simple model for a closed form may not
exist. Thus, only analytical models for
SCE are based on charge sharing effect
In reality, 2D device simulation have to be used to analyze DIBL. If the
surface region is implanted to shift VT, then DIBL may occur beneath
the surface where the doping is lighter. To solve this problem, a deep
heavily doped channel implant is used to prevent the drain potential
from punch‐through to the source
In addition to short channel
effects on VT, narrow width effect
is another important geometry
scaling factor affecting VT
MOSFET cross section along
the channel width direction
In the boundary between the active and isolation regions, the
depletion layer cannot change abruptly. Consequently, the transition
region is formed with spreading of field lines from the gate outside
the active region (W). Thus,the gate charge QG have to support part
of charge outside of active region and this extra charge loading leads
to degraded Qinv at fixed Vg or increase of VT to reach required Qinv
Non‐uniform vertical profile
‐ Multiple channel implantations
‐ Retrograde channel implantation
Non‐uniform lateral profile
‐ Halo implantation
‐ Super halo implantation
Well proximity effect (WPE)
‐ Well implant mask to channel distance
2D non‐uniform lateral Boron profile after S/D Processing