Vlsi Lab Manual: Department of Information Technology

VLSI LAB DCET TANVEER SULTANA
DEPARTMENT OF INFORMATION TECHNOLOGY
VLSI LAB MANUAL
B.E. VII Semester CBCS
DECCAN COLLEGE OF ENGINEERING & TECHNOLOGY

Dar-us-Salam, Hyderabad -500 001.
2021
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Lab Manual for the Academic Year 2020-2021

SUBJECT : VLSI Design LAB
SUBJECT CODE : PC -751IT
SEMESTER : VII
STREAM : INFORMATION TECHNOLOGY
INSTRUCTOR: Mrs.Tanveer sultana
List of Experiments to be performed

1. Switch level modelling using Verilog a) Logic gates b) AOl and OAI gates c)
Transmission gate d) Complex logic gates using CMOS
2. Gate-level Modelling—Digital circuits using gate primitives—using Verilog. a) Half adder
and full adders b) AOl gate with and without delay
c) OAl gate with and without delay c) 2:1 MUX using tri-state buffers
d) S-R latch
3. RTL Modelling of general VLSI system components. a) 4:1 MUX b) 2 to 4 Decoder c) 8:3
Priority encoder d) Flip-flops
4. Mixed gate-level and Switch-level modelling using Verilog
a) Constructing a 4-input AND gate using CMOS 2-input NAND and NOR gates. b)
Constructing a 2 to 4 decoder using CMOS 2-input AND gates and NOT gates etc.
5. Synthesis of Digital Circuits a) Ripple carry adder and carry look-ahead adder
6. Verilog code for finite state machine
7. Simple layouts of Inverter, NAND2 and NOR2 gates
2
S NO CONTENTS/PROGRAM NAME Page No
INTRODUCTION
I Hardware Description Language
SWITCH LEVEL MODELING
1 Design a NOT gate using CMOS
2 Design a 2-Input NAND gate using CMOS
3 Design a 2-Input NOR gate using CMOS
4 Design an AOI f=ab + ac + bd using CMOS
5 Design an OAI f=(a + b). (a + c). (b + d) using CMOS
6 Design a CMOS transmission gate using switch level modeling
7 Design cmos xor transmission gate using switch level modeling
8. CMOS complex logic gate implementation of function f= d’+a’b’c’

using switch level modeling
STRUCTURAL GATE LEVEL MODELING
9 Design a Half Adder
10 Design a Full Adder
11 Design AOI (WITHOUT DELAY)using gate level modeling
12 Design AOI (WITH DELAY)using gate level modeling
13 Design OAI (WITHOUT DELAY)using gate level modeling
14 Design OAI (WITH DELAY)using gate level modeling
15 Design a 2:1 MUX using Tri State Buffer
16 Design a S-R Latch
DATA FLOW MODELING
17 Design all logic gates using data flow modeling
MIXED LEVEL MODELING
3
18 Four inputs and gate using two inputs cmos nand2 & nor using mixed
level modeling
19 Decoder 2:4 using 2 inputs cmos and2 gate using mixed level modeling
BEHAVIORAL MODELING
20 Design mux 4:1using behavioural modeling
21 Design a Positive Edge Triggered Master-Slave D Flipflop
22 Design a Positive Edge Triggered Master-Slave JK Flipflop
23 Design a 8:3 priority encoder
24 MOORE FSM
SIMPLE LAYOUT DIAGRAMS
25 Draw a Layout diagram for NOT gate
26 Draw a Layout diagram for a 2-Input NAND gate
27 Draw a Layout diagram for a 2-Input NOR gate
SYNTHESIS OF DIGITAL CIRCUITS
28 Implement Ripple Carry Adder using RTL & Behavioral Modeling
29 Implement Carry Look Ahead Adder using RTL & Behavioral

Modeling
4
HDL(HARDWARE DESCRIPTION LANGUAGE)
HDL -> Hardware description language allows us to specify the components that makeup
instead of having to use a pictorial representation like a block or logic diagram. Every
component is defined by its input and output part logic function. It performs and timing
characteristics such as delay and clocking. An entire digital system can described in text
format using prescribed set of roles and keywords (reserved words).
Generally two types of HDL
(1) VHDL (VHSLC HDL):

➔ Very high speed: Integrated circuit HDL
(2) Verilog HDL:
➔ Mostly in VLSI design uses verilog HDL.
➔ Verilog HDL is a relatively loose and free following language.
➔ It uses similar procedures and constructs C- programming language.
➔ Verilog HDL provides for description of a digital System at all of the levels in VLSI
design flow.
➔ Verilog code use sans serif font type.
➔ This language is case sensitive.
In VLSI we have following types of modeling
(1) Structural Gate level modeling.

(2) Switch level modeling.
(3) Hierarchal modeling (mixed level modeling Gate and Switch level modeling).
(4) Behavioral modeling.
(5) Dataflow and RTL modeling.
5
VLSI DESIGN FLOW
6
STEPS FOR ISE DESIGN SUIT
1. Open ISE Design Suite 14.5 .
2. Click on File > NewProject...
7
3. Give a name to the project and click on [Next].
4. Click on [Next] again.
8
5. Then click on [Finish].
6. Right click in “Hierarchy”.
9
7. Click on ‘New Source...’.
8. Select ‘Verilog Module’.
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9. Give a name to the module then click on [Next].
10. Give the input and output parameters. Then click on [Next].
11
11. Click on [Finish].
12. Write the Verilog code.
12
13. In the process pane expand ‘Synthesize – XST’.
14. Run ‘Check Syntax’ to check the syntax of the written verilog code.
13
15. Goto ‘Simulation’ in view pane. Then right click again in ‘Hierarchy’ and select ‘New
Source...’.
16. Select ‘Verilog Test Fixture’ and give a name to the file. Then click on [Next].
14
17. Select the Verilog code module that was created before and click on [Next].
18. Enter the ‘Test Bench Code’.
15
19. Expand ‘Isim Simulator’ in processes.
20. Run the ‘Behavioral Check Syntax’ and ‘Simulate Behavioral Model’.
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21. Check the Output.
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1. CMOS NOT GATE USING SWITCH LEVEL MODELING
AIM: To design NOT logic gate in switch level modeling using verilog code
Description: The NOT or INVERT function is often considered the simplest Boolean
operation.
➔ NOT logic gate Cmos is built using one PFET and one NFET. Gate input ‘a’ is given
common to both FETS and o/p ‘f’ is drawn connecting both FETS in series.
➔ If gate i/p a=0 then PFET mp is ON and NFET mn is off. This connect the o/p node
‘f’ to power supply voltage VDD (i/p) giving an o/p f=1
➔ If the gate i/p a=1 then NFET mn is on and PFET mp is off. This connect the o/p node
f to ground (i/p).
Expression for o/p:
f = 𝑎̅ . 1 + a . 0 = 𝑎̅
f = NOT ( a ) = 𝑎̅
NOT GATE:
Symbol:
CMOS Diagram:
18
TRUTH TABLE:
INPUT OUTPUT
a f
0 1
1 0
//Verilog code:
module cmosnot(x,y);
input x;
output y;
Supply1 vdd;
Supply2 gnd;
pmos p1(y,vdd,x);
nmos n1(y,gnd,x);
endmodule
///test bench
module tbcmosnot;
reg x;
wire y;
cmosnot cl(y,x);
initial begin
a=0;
#50; a=1;
end
initial
$monitor($time,”x=%b y=%b”,x,y);
endmodule
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2. CMOS NAND2 GATE USING SWITCH LEVEL MODELING

AIM: TO design NAND logic gate in switch level modeling using verilog code.
Description: NAND gate is called as universal gate. NAND2 logic gate Cmos circuit is built
using 2 parallel connected PFET and 2 series connected NFET.
➔ If gate inputs a = b = 1 then PFET are off [p1 & p2] and NFET [n1 & n2] are ON.
This connecting ground (i/p) to o/p node f = 0.
➔ If either of gate inputs is zero then o/p node f=1.
➔ NAND gate is complement of NOR gate.
➔ NAND function is negation of ‘and’ function.
Expression for o/p:
f (a , b)= 𝑎̅ . 1 + 𝑏̅ . 1+ a . b . 0
f = ̅𝑎 + 𝑏̅ =𝑎. 𝑏
f = 𝑎 .𝑏
SYMBOL:
CMOS DIAGRAM:
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TRUTH TABLE:
INPUT OUTPUT
a b f
0 0 1
0 1 1
1 0 1
1 1 0
//Verilog code:
module cmosnand2 (
input a,
input b,
output f
);
wire wn;
supply1 vdd;
supply0 gnd;
pmos p1(f,vdd,a);
pmos p2(f,vdd,b);
nmos n1(f,wn,a);
nmos n2(wn,gnd,b);
endmodule
//Test bench
module tbcmosnand2;
reg a,b;
wire f;
cmosnand2 n3(f,a,b);
initial begin
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{a,b}=2’b00;
#50 {a,b}=2’b01;
#50 {a,b}=2’b10;
#50 {a,b}=2’b11;
end
initial
$monitor($time,”a=%b b=%b f=%b”,a,b,f);
Endmodule
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3. CMOS NOR GATE USING SWITCH LEVEL MODELING
AIM:- To design NOR logic gate in Switch level modeling using verilog code.
DESCRIPTION:- NOR is an universal gate.
NOR2 logic gate CMOS circuit is built using two series PFET (p1&p2) and two parallel
connected NFET (n1&n2).
If both inputs a=b=0 then PFET p1&p2 are ON and NFETS (n1&n2) are off. This connects
the VDD input to output node f=1
If either gate inputs is one then output f=1.
NOR gate is complement of NAND gate.
NOR gate is negation of OR gate.
EXPRESSION FOR OUTPUT:-
f (a,b) = . .1 + .b.0 + a. .0+a.b.0
f(a,b)= . =
f=
SYMBOL:
CMOS DIAGRAM:
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TRUTH TABLE:
INPUT OUTPUT
a b f
0 0 1
0 1 0
1 0 0
1 1 0
//Verilog code:
module NOR2(
input a,
input b,
output f
);
wire wp;
supply1 vdd;
supply0 gnd;
pmos p1(wp,vdd,a);
pmos p2(f,wp,b);
nmos n1(f,gnd,a);
nmos n2(f,gnd,b);
endmodule
//Test bench
module tbcmosnor2;
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reg a,b;
wire f;
cmosnor2 n3(f,a,b);
initial begin
{a,b}=2’b00;
#50 {a,b}=2’b01;
#50 {a,b}=2’b10;
#50 {a,b}=2’b11;
end
initial
$monitor($time,”a=%b b=%b f=%b”,a,b,f);
Endmodule
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4 CMOS AOI GATE USING SWITCH LEVEL MODELING

AIM:-To design AOI gate in Switch level modeling using verilog code.
DESCRIPTION:-The inverting nature of CMOS logic circuits allows to construct
logic circuit for AOI logic expression.
An AOI [AND-or-inverter] function is the one that implements the operation in the
order
AND->OR->NOT.
AOI function can also be called as inverted SOP (Sum Of Products).
AOI4->here four inputs are used to design AOI gate.
AOI4 CMOS circuit built using serves and parallel FET’s connected.
n1 and n2, n3 and n4, n5 and n6 are connected in series (n1.n2,n3.n4,n5.n6).
n1.n2,n3.n4,n5.n6 are parallel to each other (n1.n2|n3.n4|n5.n6).
p1 and p2 are parallel, p3 and p4are parallel , p5 and p6 are parallel.
p1 and p2, p3and p4, p5 and p6 are in series with each other[(p1|p2).()p3|p4).(p5|p6)].
| -> parallel representation-> OR operation.
. -> series representation ->AND operation.

f = 𝑎𝑏 + 𝑎𝑐 + 𝑏𝑑
CIRCUIT:
CMOS CIRCUIT FOR AOI:
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TRUTH TABLE(AOI)
INPUT OUTPUT
a b c d f
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 1 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
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1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
//Verilog code:
module oai(
input a,
input b,
input c,
input d,
output f
);
wire wp,wn2,wn1;
supply1 vdd;
supply0 gnd;
pmos p1(wp,vdd,a);
pmos p2(fwp,vdd,b);
pmos p3(f,wp,c);
pmos p4(f,wp,d);
nmos n1(f,wn1,a);
nmos n2(wn1,gnd,b);
nmos n3(f,wn2,c);
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nmos n4(wn2,gnd,d);
endmodule
Test bench
module tbaoi;
// Inputs
reg a;
reg b;
reg c;
reg d;
// Outputs
wire f;
// Instantiate the Unit Under Test (UUT)
aoi uut (
.a(a),
.b(b),
.c(c),
.d(d),
.f(f)
);
initial begin
// Initialize Inputs
{a,b,c,d}=4'b0000;
// Wait 100 ns for global reset to finish
#50 {a,b,c,d}=4'b0001;
#50 {a,b,c,d}=4'b0010;
#50 {a,b,c,d}=4'b0011;
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#50 {a,b,c,d}=4'b0100;
#50 {a,b,c,d}=4'b0101;
#50 {a,b,c,d}=4'b0110;
#50 {a,b,c,d}=4'b0111;
#50 {a,b,c,d}=4'b1000;
#50 {a,b,c,d}=4'b1001;
#50 {a,b,c,d}=4'b1010;
#50 {a,b,c,d}=4'b1011;
#50 {a,b,c,d}=4'b1100;
#50 {a,b,c,d}=4'b1101;
#50 {a,b,c,d}=4'b1110;
#50 {a,b,c,d}=4'b1111;
// Add stimulus here
end
initial
$monitor($time,"a=%b b=%b c=%b d=%b f=%b",a,b,c,d,f);
endmodule
5. CMOS OAI GATE USING SWITCH LEVEL MODELING
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AIM:-To design OAI gate in Switch level modeling using verilog code.
DESCRIPTION:- CMOS inverting nature allows to construct logic circuit for OAI
function
OAI is complement of AOI.
OAI function performs the operation in order OR->AND->INVERTER.
OAI is also called as inverted POS (Product Of Sum).
OAI CMOS circuit is built using Series-Parallel connected FETS.
p1.p2, p3.p4, p5.p6 are connected in series.
(p1.p2)|(p3.p4)|(p5.p6) are connected in series.
n1 and n2 are parallel, n3 and n4 are parallel, n5 and n6 are parallel.

(n1|n2).(n3|n4).(n5|n6) are in series with each other.
OAI@-> here four inputs are taken and gives one output.
f= (a+b).(a+c).(b+d)
CIRCUIT DIAGRAM FOR OAI:
CMOS DIAGRAM FOR OAI:
TRUTH TABLE(OAI)
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INPUT OUTPUT
A b c d F
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
//Verilog code:
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module oai(
input a,
input b,
input c,
input d,
output f
);
wire wp1,wp2,wn;
supply1 vdd;
supply0 gnd;
pmos p1(wp1,vdd,a);
pmos p2(f,wp1,b);
pmos p3(wp2,vdd,c);
pmos p4(f,wp2,d);
nmos n1(f,wn,a);
nmos n2(f,wn,b);
nmos n3(wn,gnd,c);
nmos n4(wn,gnd,d);
endmodule
Test bench
module tboai;
// Inputs
reg a;
reg b;
reg c;
reg d;
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// Outputs
wire f;
oai uut (
.a(a),
.b(b),
.c(c),
.d(d),
.f(f)
);
initial begin
{a,b,c,d}=4'b0000;
#50 {a,b,c,d}=4'b0001;
#50 {a,b,c,d}=4'b0010;
#50 {a,b,c,d}=4'b0011;
#50 {a,b,c,d}=4'b0100;
#50 {a,b,c,d}=4'b0101;
#50 {a,b,c,d}=4'b0110;
#50 {a,b,c,d}=4'b0111;
#50 {a,b,c,d}=4'b1000;
#50 {a,b,c,d}=4'b1001;
#50 {a,b,c,d}=4'b1010;
#50 {a,b,c,d}=4'b1011;
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#50 {a,b,c,d}=4'b1100;
#50 {a,b,c,d}=4'b1101;
#50 {a,b,c,d}=4'b1110;
#50 {a,b,c,d}=4'b1111;
end
initial
endmodule
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6. CMOS TRANSMISSION GATE using switch level modeling

AIM:-To design Transmission gate in Switch level modeling using verilog code.
DESCRIPTION:- Two MOS transistors are connected back-to-back in parallel with

an inverter used between the gate of the NMOS and PMOS to provide the two
complementary control voltages. When the input control signal, VC is LOW, both the
NMOS and PMOS transistors are cut-off and the switch is open. When VC is high,
both devices are biased into conduction and the switch is closed.
Thus the transmission gate acts as a “closed” switch when VC = 1, while the gate acts
as an “open” switch when VC = 0 operating as a voltage-controlled switch. The
bubble of the symbol indicating the gate of the PMOS FET.
36
// Verilog code:
module cmostg(
input x,
input s,
output y
);
supply1 vdd;
supply0 gnd;
pmos p1(y,x,~s);
nmos n1(y,x,s);
endmodule
test bench
module tbcmostg;
// Inputs
reg x;
reg s;
// Outputs
wire y;
cmostg uut (
.x(x),
.s(s),
.y(y)
);
initial begin
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{s,x}=2'b00;
#50 {s,x}=2'b01;
#50 {s,x}=2'b10;
#50 {s,x}=2'b11;
end
initial
$monitor(Stime,"y=%b x=%b s=%b",y,x,s);
Endmodule
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7. cmos xor transmission gate using switch level modeling
A transmission gate is constructed from a normally open switch (NMOS transistor) wired in
parallel with a normally closed switch (PMOS transistor), with complementary control signals.
A transmission gate is constructed from a normally open switch (NMOS transistor) wired in
parallel with a normally closed switch (PMOS transistor), with complementary control signals.
The two transmission gates work in tandem to realize a selector operation. Depending on the
state of the A input, either Input B or the inverted version of input B appears at the f (XOR)
output.
CIRCUIT DIAGRAM
TRUTH TABLE
39
//verilog code
module xor2tg(
input a,
input b,
output f
);
wire a1=~a,b1=~b;
pmos p1(f,a,b);
pmos p2(f,a1,b1);
nmos n1(f,a,b1);
nmos n1(f,a1,b);
endmodule
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test bench
module tbxor2tg;
// Inputs
reg a;
reg b;
// Outputs
wire f;
xor2tg uut (
.a(a),
.b(b),
.f(f)
);
initial begin
{a,b}=2'b00;
#50 {a,b}=2'b01;
#50 {a,b}=2'b10;
#50 {a,b}=2'b11;
end
initial
$monitor($time,"f=%b a=%b b=%b",f,a,b);
endmodule
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8. CMOS complex logic gate implementation of function f= d’+a’b’c’ using switch level
modeling
Logic gates can be built up into chains of logical decisions. Some logic gates may have more
than two inputs. The diagram below shows a complex logic gate combining three simple
gates.
CIRCUIT SYMBOL
TRUTH TABLE
42
//Verilog code
module cmoscl(
input a,
input b,
input c,
input d,
output f
);
wire wp1,wp2,wn;
supply1 vdd;
supply0 gnd;
pmos p1(wp1,vdd,a);
pmos p2(wp2,wp1,b);
pmos p3(f,wp2,c);
pmos p4(f,vdd,d);
nmos n1(f,wn,d);
nmos n2(wn,gnd,a);
nmos n3(wn,gnd,b);
nmos n4(wn,gnd,c);
endmodule
//test bench
module tbcmoscl;
// Inputs
reg a;
reg b;
reg c;
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reg d;
// Outputs
wire f;
cmoscl uut (
.a(a),
.b(b),
.c(c),
.d(d),
.f(f)
);
initial begin
{a,b,c,d}=4'b0000;
#50 {a,b,c,d}=4'b0001;
#50 {a,b,c,d}=4'b0010;
#50 {a,b,c,d}=4'b0011;
#50 {a,b,c,d}=4'b0100;
#50 {a,b,c,d}=4'b0101;
#50 {a,b,c,d}=4'b0110;
#50 {a,b,c,d}=4'b0111;
#50 {a,b,c,d}=4'b1000;
#50 {a,b,c,d}=4'b1001;
#50 {a,b,c,d}=4'b1010;
#50 {a,b,c,d}=4'b1011;
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#50 {a,b,c,d}=4'b1100;
#50 {a,b,c,d}=4'b1101;
#50 {a,b,c,d}=4'b1110;
#50 {a,b,c,d}=4'b1111;
end
initial
endmodule
45
9. HALF ADDER USING GATE LEVEL MODELING
DESCRIPTION: A half adder is a logical circuit that performs an addition on two binary
digits as inputs and produces an two binary digits outputs as Sum and Carryout.
➔ Half adder is built from XOR gate and AND gate.

➔ Half adder adds to one bit binary numbers.
Advantage:
➔ Half adder would be used to add the least Significant bits in ripple carry adder, as this
addition can have no carry input.
➔ It is significantly less complex than full adder.
➔ It saves on hardware in the situation where carry input is not needed.
Drawback:
➔ Half adder cannot be used for multi bit addition since it cannot include a carry input.
Equations or formula:
Sumout = a b
Carryout = Cout = a . b
Where a &b are inputs to half adder circuit and Sumout and Carryout are outputs.
SYMBOL:
46
CIRCUIT DIAGRAM:
//Verilog code
module halfadd(
input a,
input b,
output s,
output c
);
xor(s,a,b);
and(c,a,b);
endmodule
// test bench
module tbhalfadd;
// Inputs
reg a;
reg b;
// Outputs
wire s;
wire c;
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halfadd uut (
.a(a),
.b(b),
.s(s),
.c(c)
);
initial begin
{a,b}=2'b00;
#50 {a,b}=2'b01;
#50 {a,b}=2'b10;
#50 {a,b}=2'b11;
end
initial
$monitor($time,"a=%b b=%b s=%b c=%b",a,b,s,c);
endmodule
48
10. FULL ADDER USING GATE LEVEL MODELING
DESCRIPTION: The 3-bit full adder circuit adds 3- one.bit binary number Cin, a, b as
inputs and produces an output two one bit numbers as Sumout and Carryout(Cout).
➔ Full adder is simply 2 half adders joined by an OR gate. The o/p of XOR gate is
called Sumout and o/p of AND gate is carry [ w2 & w3].
Advantages:
➔ Full adders are used in nbit binary words [multiput i/p].

➔ It is usually a component in a cascade of adders which add 8,16,32 etc, binary
numbers. Carry i/p for full adder circuit is from carry o/p from circuit “above” itself in
cascade. The carry o/p from full adder is fed to another full adder “below” itself in
cascade.
Disadvantage:
➔ Complex than half adder.

Equations or formulae:
Sumout = a b Cin
Cout = (a . b) + (Cin.(a b))
Cout = (a . b) + (Cin . a) + (Cin . b)
SYMBOL:
49
CIRCUIT DIAGRAM:
verilog code
module fulladder(
input a,
input b,
input ci,
output s,
output co
);
wire w1,w2,w3;
xor a1(s,a,b,ci);
and a2(w1,a,b);
and a3(w2,b,ci);
and a4(w3,ci,a);
or a5(co,w1,w2,w3);
endmodule
50
test bench
module tbfulladder;
// Inputs
reg a;
reg b;
reg ci;
// Outputs
wire s;
wire co;
fulladder uut (
.a(a),
.b(b),
.ci(ci),
.s(s),
.co(co)
);
initial begin
{a,b,ci}=3'b000;
#50{a,b,ci}=3'b001;
#50{a,b,ci}=3'b010;
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#50{a,b,ci}=3'b011;
#50{a,b,ci}=3'b100;
#50{a,b,ci}=3'b101;
#50{a,b,ci}=3'b110;
#50{a,b,ci}=3'b111;
end
initial
$monitor($time,"a=%b b=%b ci=%b s=%b co=%b",a,b,ci,s,co);
endmodule
52
11. AOI (WITHOUT DELAY)using gate level modeling
AND-OR-Invert (AOI) logic and AOI gates are two-level compound (or complex) logic
functions constructed from the combination of one or more AND gates followed by a NOR
gate. Construction of AOI cells is particularly efficient using CMOS technology where the
total number of transistor gates can be compared to the same construction using NAND
logic or NOR logic. The complement of AOI Logic is OR-AND-Invert (OAI) logic where the
OR gates precede a NAND gate.
CIRCUIT SYMBOL
53
//Verilog code
module aoigate(
input a,
input b,
input c,
input d,
output f
);
wire w1,w2;
and a1(w1,a,b);
and a2(w2,c,d);
nor a3(f,w1,w2);
endmodule
// test bench:
module tbaoigate;
// Inputs
reg a;
reg b;
reg c;
reg d;
// Outputs
wire f;
aoigate uut (
.a(a),
.b(b),
54
.c(c),
.d(d),
.f(f)
);
initial begin
{a,b,c,d}=4'b0000;// Wait 100 ns for global reset to finish
#50 {a,b,c,d}=4'b0001;
#50 {a,b,c,d}=4'b0010;
#50 {a,b,c,d}=4'b0011;
#50 {a,b,c,d}=4'b0100;
#50 {a,b,c,d}=4'b0101;
#50 {a,b,c,d}=4'b0110;
#50 {a,b,c,d}=4'b0111;
#50 {a,b,c,d}=4'b1000;
#50 {a,b,c,d}=4'b1001;
#50 {a,b,c,d}=4'b1010;
#50 {a,b,c,d}=4'b1011;
#50 {a,b,c,d}=4'b1100;
#50 {a,b,c,d}=4'b1101;
#50 {a,b,c,d}=4'b1110;
#50 {a,b,c,d}=4'b1111;
end
initial
endmodule
55
12. AOI (WITH DELAY) USING GATE LEVEL MODELING
//Verilog code
module aoidelay(
input a,
input b,
input c,
input d,
output f
);
wire w1,w2;
and #50 t1(w1,a,b);
56
and #50 t2(w2,c,d);
nor #50 t3(f,w1,w2);
endmodule
//test bench
module tbaoidelay;
// Inputs
reg a;
reg b;
reg c;
reg d;
// Outputs
wire f;
aoidelay uut (
.a(a),
.b(b),
.c(c),
.d(d),
.f(f)
);
initial begin
{a,b,c,d}=4'b0000;
#50 {a,b,c,d}=4'b0001;
#50 {a,b,c,d}=4'b0010;
57
#50 {a,b,c,d}=4'b0011;
#50 {a,b,c,d}=4'b0100;
#50 {a,b,c,d}=4'b0101;
#50 {a,b,c,d}=4'b0110;
#50 {a,b,c,d}=4'b0111;
#50 {a,b,c,d}=4'b1000;
#50 {a,b,c,d}=4'b1001;
#50 {a,b,c,d}=4'b1010;
#50 {a,b,c,d}=4'b1011;
#50 {a,b,c,d}=4'b1100;
#50 {a,b,c,d}=4'b1101;
#50 {a,b,c,d}=4'b1110;
#50 {a,b,c,d}=4'b1111;
end
initial
endmodule
58
13. OAI (WITHOUT DELAY)USING GATE LEVEL MODELING
59
//Verilog code
module oaigate(
input a,
input b,
input c,
input d,
output f
);
wire w1,w2;
or r1(w1,a,b);
or r2(w2,c,d);
nand r3(f,w1,w2);
endmodule
//test bench
module tboaigate;
// Inputs
reg a;
reg b;
reg c;
reg d;
// Outputs
wire f;
oaigate uut (
.a(a),
60
.b(b),
.c(c),
.d(d),
.f(f)
);
initial begin// Initialize Inputs
{a,b,c,d}=4'b0000;// Wait 100 ns for global reset to finish
#50 {a,b,c,d}=4'b0001;
#50 {a,b,c,d}=4'b0010;
#50 {a,b,c,d}=4'b0011;
#50 {a,b,c,d}=4'b0100;
#50 {a,b,c,d}=4'b0101;
#50 {a,b,c,d}=4'b0110;
#50 {a,b,c,d}=4'b0111;
#50 {a,b,c,d}=4'b1000;
#50 {a,b,c,d}=4'b1001;
#50 {a,b,c,d}=4'b1010;
#50 {a,b,c,d}=4'b1011;
#50 {a,b,c,d}=4'b1100;
#50 {a,b,c,d}=4'b1101;
#50 {a,b,c,d}=4'b1110;
#50 {a,b,c,d}=4'b1111;
end
initial
endmodule
61
14. OAI (WITH DELAY) USING GATE LEVEL MODELING
//Verilog code:
module oaidelay(
input a,
input b,
input c,
input d,
output f
);
wire w1,w2;
or #50 r1(w1,a,b);
62
or #50 r2(w2,c,d);
nand #50 r3(f,w1,w2);
endmodule
//Test bench:
module tboaidelay;
// Inputs
reg a;
reg b;
reg c;
reg d;
// Outputs
wire f;
oaidelay uut (
.a(a),
.b(b),
.c(c),
.d(d),
.f(f)
);
initial begin
{a,b,c,d}=4'b0000;
#50 {a,b,c,d}=4'b0001;
#50 {a,b,c,d}=4'b0010;
63
#50 {a,b,c,d}=4'b0011;
#50 {a,b,c,d}=4'b0100;
#50 {a,b,c,d}=4'b0101;
#50 {a,b,c,d}=4'b0110;
#50 {a,b,c,d}=4'b0111;
#50 {a,b,c,d}=4'b1000;
#50 {a,b,c,d}=4'b1001;
#50 {a,b,c,d}=4'b1010;
#50 {a,b,c,d}=4'b1011;
#50 {a,b,c,d}=4'b1100;
#50 {a,b,c,d}=4'b1101;
#50 {a,b,c,d}=4'b1110;
#50 {a,b,c,d}=4'b1111;
end
initial
endmodule
64
15. MULTIPLEXER 2:1 OF TRI STATE USING GATE LEVEL MODELING
DESCRIPTION: Multiplier can be considered as multiple inputs and single output switch.
2:1 mux have 2 inputs and produces a single output depending upon the select input [s]
2:1 mux is designed using 2 buffers that is active low buffer and active high buffer
Active low buffer is on when input is zero
Active high buffer is on when input is one
EXPRESSION :
out = 𝑝0 . 𝑠 + 𝑝1 . s
SYMBOL( 2:1 MUX USING BUFFER)
CIRCUIT DIAGRAM:
65
TRUTH TABLE(2:1 MUX USING BUFFER)
INPUTS OUTPUT
P0 P1 S Out
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 1
//Verilog code
module mux21(
input a,
input b,
input s,
output f
);
bufif0 b1(f,a,s);
bufif1 b2(f,b,s);
endmodule
//test bench
module tbmux21;
// Inputs
reg a;
reg b;
66
reg s;
// Outputs
wire f;
mux21 uut (
.a(a),
.b(b),
.s(s),
.f(f)
);
initial begin
{s,a}=2'b00;
#50 {s,a}=2'b01;
#50 {s,a}=2'b10;
#50 {s,a}=2'b11;
end
initial
$monitor($time,"s=%b a=%b b=%b f=%b",s,a,b,f);
endmodule
67
16. SR LATCH USING GATE LEVEL MODELING
DESCRIPTION: SR Latch circuit is built making use of 2 NOR gate that are cross coupled
[i.e the output of one NOR gate is passed as an input to another NOR gate]
Usage:
➢ A Latch is a storage device that can receive and hold an input bit.
➢ A Latch is transparent [that is a change can be seen in outputs]
➢ SR Latch has 2 inputs S & L and produces two outputs Q and ~Q.
Disadvantages: When both inputs are one the outputs are invalid or undetermined state.
Equation or expression of outputs:
Q= R+Qbar
Qbar = S+Q
SYMBOL:
S SR Q bar
LATCH
R Q
LOGIC DIAGRAM:
68
TRUTH TABLE
INPUTS OUTPUTS
S R Q Qbar
0 0 Previous previous
0 1 0 1
1 0 1 0
1 1 0 0
when S=0 and R=0 , the output Q will have the previous state.
When S=0 and R=1, it is in the reset state.
When S=1 and R=0, it is in the set state.
When both S=1 and R=1, the output is invalid or undetermined.
//Verilog code
module srlatch(
input S,
input R,
output Q,
output Qbar
);
nor n1(Qbar,S,Q);
nor n2(Q,R,Qbar);
endmodule
69
//test bench code:
module tbsrlatch;
// Inputs
reg S;
reg R;
// Outputs
wire Q;
wire Qbar;
srlatch uut (
.S(S),
.R(R),
.Q(Q),
.Qbar(Qbar)
);
initial begin
{S,R}=2'b00;
#50 {S,R}=2'b01;
#50 {S,R}=2'b10;
#50 {S,R}=2'b11; // Add stimulus here
end
initial
$monitor($time,"S=%b R=%b Q=%b Qbar=%b",S,R,Q,Qbar);
Endmodule
70
17. ALL LOGIC GATES USING DATA FLOW MODELING

Logic gates can be made of resistors and transistors or diodes. A resistor can commonly be
used as a pull-up or pull-down resistor. Pull-up and pull-down resistors are used when there
are any unused logic gate inputs to connect to a logic level 1 or 0. This prevents any false
switching of the gate. Pull-up resistors are connected to Vcc (+5V), and pull-down resistors are
connected to ground (0 V)
//VERILOG CODE
module logicdfm(
input a,
input b,
output c,
output d,
output e,
output f,
71
output g,
output h
);
assign c=a&b;
assign d=a|b;
assign e=a^b;
assign f=~(a&b);
assign g=~(a|b);
assign h=~(a^b);
endmodule
//TEST BENCH
module tblogicdfm;
// Inputs
reg a;
reg b;
// Outputs
wire c;
wire d;
wire e;
wire f;
wire g;
wire h;
logicdfm uut (
.a(a),
.b(b),
72
.c(c),
.d(d),
.e(e),
.f(f),
.g(g),
.h(h)
);
initial begin
{a,b}=2'b00;
#50 {a,b}=2'b01;
#50 {a,b}=2'b10;
#50 {a,b}=2'b11;
end
initial
$monitor($time,"a=%b b=%b c=%b d=%b e=%b f=%b g=%b

h=%b",a,b,c,d,e,f,g,h);
Endmodule
73
18`. FOUR INPUTS AND GATE USING TWO INPUTS CMOS NAND2 & NOR USING
MIXED LEVEL MODELING
//VERILOG CODE
//NAND2
module mlmnand2(
input a,
input b,
output f
);
wire wn;
supply1 vdd;
supply0 gnd;
pmos p1(f,vdd,a);
pmos p2(f,vdd,b);
nmos n1(f,wn,a);
nmos n2(wn,gnd,b);
endmodule
//NOR2
module mlmNOR2(
input a,
input b,
output f
);
wire wp;
74
supply1 vdd;
supply0 gnd;
pmos p1(wp,vdd,a);
pmos p2(f,wp,b);
nmos n1(f,gnd,a);
nmos n2(f,gnd,b);
endmodule
//AND4
module mlmAND4(
input a,
input b,
input c,
input d,
output f
);
wire w1,w2;
mlmnand2 n1(w1,a,b);
mlmnand2 n2(w2,c,d);
mlmNOR2 n3(f,w1,w2);
endmodule
//TEST BENCH
module tbAND4;
// Inputs
reg a;
reg b;
75
reg c;
reg d;
// Outputs
wire f;
mlmAND4 uut (
.a(a),
.b(b),
.c(c),
.d(d),
.f(f)
);
initial begin
{a,b,c,d}=4'b0000;
#50 {a,b,c,d}=4'b0001;
#50 {a,b,c,d}=4'b0010;
#50 {a,b,c,d}=4'b0011;
#50 {a,b,c,d}=4'b0001;
#50 {a,b,c,d}=4'b0100;
#50 {a,b,c,d}=4'b0101;
#50 {a,b,c,d}=4'b0110;
#50 {a,b,c,d}=4'b0111;
#50 {a,b,c,d}=4'b1000;
76
#50 {a,b,c,d}=4'b1001;
#50 {a,b,c,d}=4'b1010;
#50 {a,b,c,d}=4'b1011;
#50 {a,b,c,d}=4'b1100;
#50 {a,b,c,d}=4'b1101;
#50 {a,b,c,d}=4'b1110;
#50 {a,b,c,d}=4'b1111;
end
initial
$monitor($time,"f=%b a=%b b=%b c=%b d=%b",f,a,b,c,d);
Endmodule
77
19. DECODER 2:4 USING 2 INPUTS CMOS AND2 GATE USING MIXED LEVEL
MODELING
DESCRIPTION: A decoder is a device which does the reverse of an encoder, undoing the
encoding so that original information can be retrieved decoder is a multiple input, multiple
output logic. Circuit that converts coded inputs into coded outputs where the input and output
codes are different. Ex: n to 2n, BCD decoders.
APPLICATIONS: Data multiplexing, 7-segment display and memory address decoding.
• 2 Types of Binary Decoder.

(1) Active high decoder: It sets a 1 on the selected line and keep others at zero.
(2) Active low decoder: It set zero on the selected line and keep others at 1.
Simplest decoder circuit would be AND gate because the output of AND gate is high.
(1) Only when all its inputs are high such output is called as active high output.
2-4 binary decoder have 2 inputs lines s0 and s1 that combinationally pass through 4
AND gates to provide 4 lines output d0,d1,d2,d3.
EXPRESSION FOR OUTPUTS:
𝑑0 = 𝑠1 .𝑠0
𝑑1 = 𝑠1 .𝑠0
𝑑2 =𝑠1 .𝑠0
𝑑3 = 𝑠1 .𝑠0
SYMBOL:
s1 s0
2:4
d0
d1
Binary
d2
decoder d3
78
CIRCUIT DIAGRAM
TRUTH TABLE( 2:4 BINARY DECODER)
Input Outputs
s1 s0 d0 d1 d2 d3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
79
//VERILOG CODE
//CMOS AND2
module cmosand2(
input a,
input b,
output f
);
wire wn,g;
supply1 vdd;
supply0 gnd;
pmos p1(g,vdd,a),p2(g,vdd,b),p3(f,vdd,g);
nmos n1(g,wn,a),n2(wn,gnd,b),n3(f,gnd,g);
endmodule
module dec24(
input w0,
input w1,
output d0,
output d1,
output d2,
output d3
);
cmosand2 a1(d3,~w0,~w1);
cmosand2 a2(d2,~w0,w1);
cmosand2 a3(d1,w0,~w1);
cmosand2 a4(d0,w0,w1);
80
endmodule
//TEST BENCH
module tbdec24;
// Inputs
reg w0;
reg w1;
// Outputs
wire d0;
wire d1;
wire d2;
wire d3;
dec24 uut (
.w0(w0),
.w1(w1),
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3)
);
initial begin
{w1,w0}=2'b00;
#50 {w1,w0}=2'b01;
#50 {w1,w0}=2'b10;
81
#50 {w1,w0}=2'b11;
end
initial
$monitor($time,"d0=%b d1=%b d2=%b d3=%b w0=%b w1=%b", d0,d1,d2,d3,w1,w0);
Endmodule
82
20. MUX 4:1USING BEHAVIORAL MODELING
DESCRIPTION: Multiplexer or mux is a device that performs multiplexing, it selects one of

that into a single line digital input signals and outputs that into a single line
4:1 mux is built using 4 AND gates, 2 NOT gate and one OR gate.
Each AND gate has 3 inputs[ that is 4 inputs a to d is applied to one input of AND gate, 2
inputs are select inputs to AND gate]
Select lines s0 ans s1 are decoded to select a particular AND gate to produce an output of
a.~s0.~s1to G1 AND gate

b.s0.~s1 to G2 AND gate
c.~s0.s1 to G3 AND gate
d.s0.s1 to G4 AND gate
EXPRESSION
f = (a . 𝑠0 . 𝑠1 ) + (b . 𝑠0 . 𝑠1 ) + (c . 𝑠0 . 𝑠1 ) + (d . 𝑠0 . 𝑠1 )
SYMBOL:
83
CIRCUIT DIAGRAM:
TRUTH TABLE:
INPUTS OUTPUT
S1 S0 d c b a f
0 0 0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
1 1 0 1 1
0 1 0 0 0 0 0
0 0 0 1 0
0 1 1 0 1
1 0 0 0 0 0 0
0 0 0 1 0
0 1 0 1 1
84
1 0 1 1 0
1 1 0 1 1 1 0
0 0 0 1 0
1 1 1 1 1
1 0 0 0 1
//VERILOG
module MUX41(
input [3:0]a,
input b,
input c,
input d,
input [1:0]s,
output [3:0]f
);
reg [3:0]f;
always@(s or a or b or c or d)
case(s)
2'b00:f=a;
2'b01:f=b;
2'b10:f=c;
2'b11:f=d;
endcase
endmodule
//TEST BENCH
module tbMUX41;
// Inputs
85
reg [3:0] a;
reg b;
reg c;
reg d;
reg [1:0] s;
// Outputs
wire [3:0] f;
MUX41 uut (
.a(a),
.b(b),
.c(c),
.d(d),
.s(s),
.f(f)
);
initial begin
a = 10;
b =11;
c = 12;
d = 13;
s = 0;
#50 s=1;
#50 s=2;
86
#50 s=3;
end
initial
$monitor($time,"f=%b a=%b b=%b c=%b d=%b s=%b",f,a,b,c,d,s);
Endmodule
87
21. D FLIPFLOP USING BEHAVIORAL MODELING
DESCRIPTION :flipflop is a storage device which can hold or store 1 bit numbers.
A flipflop differs from latch in that it is nontransperent. D flipflop(DFF) is most commonly
used flipflop in CMOS circuits.
• Basic DFF design is master-slave configuration obtained by cascadfing two

oppositively phased d latches.
• Two types of master slave flipflop
1. Positive edge triggered
2. Negative edge triggered.
Master slave positive edge triggered d-flipflop:
It is obtained by applying input d and d-bar to master,clock signal
(clk) is directly given to slave and (~clk)is given to master outputs .outputs of master are
given to slave and slave outputs are q and q-bar.additionally preset and clear intput is given to
master to preset the output q=1 and clear the output q=0.
• Clock signal controls the operation and synchronization.

• Preset and clear inputs are active low inputs i.e, if preset(pr)=0 then
q=1->irrespective of d=1 or 0
• clear(cr)=0 then q=0 ->irrespectiveof d=0 or 1.
• D flipflop is built using 8 nand gates
• If preset =1 or clear=1 then output normal flipflop
• If preset and clear=0 cannot be same as zero simultaneously .
LOGICAL SYMBOL:
CIRCUIT DIAGRAM:
88
pr
q_bar w1 w3 w5
d q
master slave
clk
q_bar
q w2 w4 w6
cr
TRUTH TABLE ( D-FLIP FLOP)
Inputs Output
D Clk Pr Cr q q bar
0 1 1 1 0 1
1 1 1 1 1 0
0 1 0 1 1 0
0 0 1 1 0 1
1 0 1 1 1 0
1 1 1 0 0 1
X 0 1 0 0 1
89
module dff(q,d,clk);
input d,clk;
output q;
reg q;
always@(posedgeclk)
q=d;
endmodule
//TEST BENCH
module tbdff;
reg d,clk;
wire q;
dff dl(q,d,clk);
initial
clk=1’b0;
always
#50 clk=~clk;
initial begin
d=0;
#50 d =1;
#50 d =0;
#50 d =1;
end
initial
$monitor ($time, ”clk=%b d=%b q=%b”,clk,d,q);
Endmodule
90
22. JK FLIPFLOP USING BEHAVIORAL MODELING
DESCRIPTION:
Flip flop is a storage element based on gated latch principle which can have it’s output state
changed only on the edge of controlling clock signal.
➢ JK flipflop combines the behavior of SR &T flipflops. It behaves as SRflipflop when

J=S & K=R for all input values except J=K=1, it behaves as T flipflop & toggles it’s
state.
➢ JK flipflop is a versatile circuit.
➢ It can be used for storage purpose.
➢ It can serve as T flipflop by connecting J&K inputs together.
➢ JK flipflop with presert & clear inputs is designed using 8 NAND gates. It is positive
edge triggered flipflop.
LOGIC SYMBOL
91
CIRCUIT DIAGRAM:
TRUTH TABLE:
Inputs Outputs
j k Pr Cr Clk Q Qbar
X X 1 0 1 0 1
0 0 1 1 1 0 1
0 1 1 1 1 0 1
1 0 1 1 1 1 0
1 1 1 1 1 1/0 0/0
When both pr and cr=1 and j=0 and k=1, the flip flop is in reset state.
When both pr and cr=1 and j=1 and k=0, the flip flop is in set state.
When both pr and cr=1 and j=1 and k=1, the flip flop is in toggle state.
module JKff(q,j,k,clk);
92
input j,k,clk;
output q;
reg q;
always@(posedgeclk)
case({j,k})
2’b00:q=q;
2’b01:q=0;
2’b10:q=1;
2’b11:q=~q;
endcase
endmodule
//TEST BENCH
module tbjkff;
reg j,k,clk;
wire q;
jkff j1(q,j,k,clk);
initial
clk=1’b0;
always
#50 clk=~clk;
initial begin
{j,k}=2’b00;
#50 {j,k}=2’b01;
#50 {j,k}=2’b10;
#50 {j,k}=2’b11;
#50 {j,k}=2’b00;
end
initial
$monitor ($time, ”clk=%b j=%b k=%b q=%b”,clk,j,k,q);
endmodule
93
23. PRIORITY ENCODER 8:3 USING BEHAVIORAL MODELING
DESCRIPTION: A priority encoder examines the input bits of an n bit word and produces
an output that indicates the position of highest priority Logic 1 bit.
4 bit priority encoder is a circuit basically converts the 4 bit input into 2 bit binary
representation. If the input ‘n’ is active, all lower inputs (n-1….0) are ignored.
Each output is driven by an OR gate which is connected to NAND-INV outputs of the

corresponding input lines. NAND gate of each stage receives its input bit as well as the
NAND gate outputs of all higher priority stages. An active input on stage n effectively
disables cell lower stages n-1…0.
Circuit function does not depend at all on least significant input bit.
APPLICATIONS:
Used for intercept controllers.
They are used when multiple components(eg: processor, memory, I/O devices, etc) are to
share a common resource(eg: a bus). Each component is assigned certain priority whenever
there is conflict, the highest priority component will be granted usage of resource.
𝑦1 = 1 . 𝑥3 + 𝑥3 𝑥2 . 1 + 𝑥3 𝑥2 𝑥1 . 0 + 𝑥3 𝑥2 𝑥1 . 0
𝑦1 = 𝑥3 + 𝑥3 𝑥2
𝑦0 = 1 . 𝑥3 + 𝑥3 𝑥2 . 0 + 𝑥3 𝑥2 𝑥1 . 1 + 𝑥3 𝑥2 𝑥1 . 0
𝑦0 = 𝑥3 + 𝑥3 𝑥2 𝑥1
SYMBOL
94
CIRCUIT DESIGN
x0 is dummy
TRUTH TABLE
Input output
x3 x2 x1 x0 y1 y0
1 x x x 1 1
0 1 x x 1 0
0 0 1 x 0 1
0 0 0 x 0 0
95
//Verilog
module pe83(
input [7:0]d,
output [2:0]q,
output q3
);
reg[2:0]q;
reg q3;
always @(d)
begin
q3=1;
if(d[7]) q=7;
else if(d[6]) q=6;
else if(d[5]) q=5;
else if(d[4]) q=4;
else if(d[3]) q=3;
else if(d[2]) q=2;
else if(d[1]) q=1;
else if(d[0]) q=0;
else
begin
q3=0;
q=3'bxxx;
end
end
endmodule
96
//TEST BENCH:
module tbpe83;
// Inputs
reg [7:0] d;
// Outputs
wire [2:0] q;
wire q3;
pe83 uut (
.d(d),
.q(q),
.q3(q3)
);
initial begin// Initialize Inputs
d = 8'b00000000;// Wait 100 ns for global reset to finish
#50 d=8'b00000010;
#50 d=8'b00000100;
#50 d=8'b00001000;
#50 d=8'b00010000;
#50 d=8'b00100000;
#50 d=8'b01000000;
#50 d=8'b10000000; // Add stimulus here
end
initial
$monitor($time,"q=%b q3=%b d=%b",q,q3,d);
endmodule
97
24. MOORE FSM USING BEHAVIORAL MODELING
• Mealy State Machine : Its output depends on current state and current inputs. In the
above picture, the blue dotted line makes the circuit a mealy state machine.
• Moore State Machine : Its output depends on current state and current inputs. In the
above picture, the blue dotted line makes the circuit a mealy state machine.
98
//Verilog.
module moorefsm(
input clk,
input data_in,
input reset,
output reg data_out
);
// Declare state register
reg [2:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;
// Determine the next state
always @ (posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (data_in)
state <= S1;
else
state <= S0;
S1:
if (data_in)
state <= S1;
99
else
state <= S2;
S2:
if (data_in)
state <= S3;
else
state <= S2;
S3:
if (data_in)
state <= S4;
else
state <= S2;
S4:
if (data_in)
state <= S1;
else
state <= S2;
endcase // case (state)
end // always @ (posedge clk or posedge reset)
// Output depends only on the state
always @ (state) begin
case (state)
S0:
data_out = 1'b0;
S1:
data_out = 1'b1;
100
S2:
data_out = 1'b0;
S3:
data_out = 1'b1;
S4:
data_out = 1'b1;
default:
data_out = 1'b0;
endcase // case (state)
end // always @ (state)
endmodule
//Test bench.
module tbmoorefsm;
// Inputs
reg clk;
reg data_in;
reg reset;
// Outputs
wire data_out;
moorefsm uut (
.clk(clk),
.data_in(data_in),
.reset(reset),
.data_out(data_out)
);
101
initial
// clk = 0;
// data_in = 0;
// reset = 0;
// #100;
clk=1'b0;
always
#50 clk=~clk;
initial begin
reset=0;
#50 reset=1;data_in=0;
#50 data_in=1;
end
initial
$monitor ($time,"reset=%b clk=%b data_in=%b data_out=%b

",reset,clk,data_in,data_out);
endmodule
102
25. IMPLEMENTATION OF 4 BIT RIPPLE CARRY ADDER
DESCRIPTION: Adding two n-bit words yields an n-bit sum and carry-out bit Cn that can
either be used as carry-in to another higher order adder or act as an overflow flag.
An n-bit ripple carry adders requires n-full adders with carry-out bit Ci+1 used as carry-in bit
to next column.
Ripple carry adder is cascading of full adders.
It is based on the addition equation.
Suppose 4-bit ripple carry adders(i.e n=4)
c3 c2 c1 c0
+ a3 a2 a1 a0
+ b3 b2 b1 b0
c4 s3 s2 s1 s0
ADVANTAGE:
Instead of adding single bits we can add binary words.
Easier construction of neighbouring circuits
Sumout of full adder = Si = 𝑎𝑖 ⊕ 𝑏𝑖 ⊕ 𝑐𝑖
Carryout=cout=𝑎𝑖 . 𝑏𝑖 +𝑐𝑖 .( 𝑎𝑖 ⊕ 𝑏𝑖 )
DEMERITS:
Ripple carry latency makes slow.
Since the output of any full adder is not valid until the incoming carry bit is valid(calculated).
103
Needs to ripple carry bits serially down the chain.
LOGIC SYMBOL
RIPPLE CARRY ADDER OF 4-BIT
+ :indicate fulladder
c1,c2,c3,c4 are carryout
s3,s2,s1,s0 sumout of fulladder
a0—a3, b0---b3 and c0 are input
104
TRUTH TABLE:
//Verilog for half adder.
module half_adder(
output S,
output C,
input A,
input B
);
xor(S,A,B);
and(C,A,B);
endmodule
//Verilog for full adder.
module full_adder(
output S,
105
output Cout,
input A,
input B,
input Cin
);
wire s1,c1,c2;
half_adder HA1(s1,c1,A,B);
half_adder HA2(S,c2,s1,Cin);
or OG1(Cout,c1,c2);
endmodule
//Verilog for 4-bit ripplefulladder.
module ripple_adder_4bit(
output [3:0] Sum,
output Cout,
input [3:0] A,
input [3:0] B,
input Cin
);
wire c1,c2,c3;
full_adder FA1(Sum[0],c1,A[0],B[0],Cin),
FA2(Sum[1],c2,A[1],B[1],c1),
FA3(Sum[2],c3,A[2],B[2],c2),
FA4(Sum[3],Cout,A[3],B[3],c3);
endmodule
//Test bench.
module test_ripple_adder_4bit;
106
// Inputs
reg [3:0] A;
reg [3:0] B;
reg Cin;
// Outputs
wire [3:0] Sum;
wire Cout;
ripple_adder_4bit uut (
.Sum(Sum),
.Cout(Cout),
.A(A),
.B(B),
.Cin(Cin)
);
initial begin
A = 0;
B = 0;
Cin = 0;
#100;
#35 A=4'b0000;B=4'b0000;Cin=0;
#35 A=4'b0001;B=4'b0000;Cin=1;
#35 A=4'b1100;B=4'b1100;Cin=1;
107
#35 A=4'b1100;B=4'b1100;Cin=0;
#35 A=4'b1101;B=4'b1101;Cin=1;
#30 A=4'b0001;B=4'b1000;Cin=1;
#30 A=4'b0000;B=4'b1111;Cin=1;
#30 A=4'b1100;B=4'b1100;Cin=0;
#30 A=4'b0000;B=4'b0111;Cin=1;
#35 A=4'b1100;B=4'b0010;Cin=1; end
initial begin
$monitor("time=",$time,, "A=%b B=%b Cin=%b : Sum=%b Cout=%b",A,B,Cin,Sum,Cout);
end
endmodule
108
26. IMPLEMENTATION OF 4 BIT RIPPLE CARRY LOOK AHEAD ADDER
Description
In parallel adders, carry output of each full adder is given as a carry input to the next higher-
order state. Hence, these adders it is not possible to produce carry and sum outputs of any
state unless a carry input is available for that state.
Circuit diagram
Truth table
DESCRIPTON: CLA algorithm is based on the origin of the carryout bit in the equation
ci+1 = ai.bi + ci . (ai^bi)
In CLA the sumout and carryout equations are written in terms of generate and propagate
terms.
Generate term ‘gi’ is used since inputs one viewed as “generating” the carryout bit.
Propagate term ‘pi’ is used where an input carry ci=1 may be propagated through the full
adder.
MERITS:
CLA adders are designed to overcome the latency introduced by the rippling effect of carry
bit in ripple carry adder.
109
EXPRESSIONS FOR OUTPUTS :
𝑔𝑖 = 𝑎𝑖 . 𝑏𝑖
𝑝𝑖 = 𝑎𝑖 ⊕ 𝑏𝑖
Carryout = 𝑐𝑖+1 = 𝑔𝑖 + 𝑝𝑖 . 𝑐𝑖
Sumout = 𝑠𝑖 = 𝑝𝑖 ⊕ 𝑐𝑖
gi pi
ai . bi ai ^ bi
ai = bi = 0 0 0
ai = bi = 1 1 0
ai ≠ bi 0 1
LOGIC SYMBOL
SUM CALCUTATION USING CLA
110
CIRCUIT DIAGRAM FOR CLA:
c1 = g0 + p0 . c0
c2 = g1 + p1 . c1 = g1 + p1 . (g0 + p0 . c0)
c3 = g2 + p2 . c2 = g2 + p2. g1 + p2 . p1 .g0 + p2 . p1 . p0 . c0
c4 = g3 + p3 . c3 = g3 + p3. g2 + p3 . p2 .g1 + p3 . p2 . p1 . g0 + p3 . p2 . p1 . p0 . c0
111
TRUTH TABLE:
Inputs Output
a3 a2 a1 a0 b3 b2 b1 b0 c0 s3 s2 s1 s0 Cout
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 0 1 1 0 0 0 0 0 1 0 1
//Verilog.
112
module CLA_4Bit(
output [3:0] S,
output Cout,
output PG,
output GG,
input [3:0] A,
input [3:0] B,
input Cin
);
wire [3:0] G,P,C;
assign G = A & B; //Generate
assign P = A ^ B; //Propagate
assign C[0] = Cin;
assign C[1] = G[0] | (P[0] & C[0]);
assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);
assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] &
C[0]);
assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0])
|(P[3] & P[2] & P[1] & P[0] & C[0]);
assign S = P ^ C;
assign PG = P[3] & P[2] & P[1] & P[0];
assign GG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);
endmodule
//Test Bench.
module TEST_CLA_4bit;
// Inputs
reg [3:0] A;
113
reg [3:0] B;
reg Cin;
// Outputs
wire [3:0] S;
wire Cout;
wire PG;
wire GG;
CLA_4Bit uut (
.S(S),
.Cout(Cout),
.PG(PG),
.GG(GG),
.A(A),
.B(B),
.Cin(Cin)
);
initial begin
A = 0;
B = 0;
Cin = 0;
#100;
114
A=4'b0001;B=4'b0000;Cin=1'b0;
#30 A=4'b100;B=4'b0011;Cin=1'b0;
#30 A=4'b1101;B=4'b1010;Cin=1'b1;
#30 A=4'b1110;B=4'b1001;Cin=1'b0;
#30 A=4'b1111;B=4'b1010;Cin=1'b0;
end
initial begin
$monitor("time=",$time,, "A=%b B=%b Cin=%b : Sum=%b Cout=%b PG=%b

GG=%b",A,B,Cin,S,Cout,PG,GG);
end
endmodule
115
MICROWIND-2 AND DSCH-2 ARE USER FRIENDLY TOOLS FOR DESIGN AND
STIMULATION .
DSCH-2 : Digital schematic editor and simulator of version 2-software.
The DSCH program is a logic editor and simulator .
DSCH is used to validate the architecture of logic circuit before the microelectronic design is
started.
DSCH provides a user friendly environment for hierarchical logic design and fast simulation.
DSCH 2 is the companion software for logic design based on primitive, a hierarchical circuit
is built and simulated. Interactive symbols such as keyboards, led and displays are used for
friendly simulation. which includes delay and power consumption evaluation.
MICROWIND-2 : Microwind version 2 software is used to draw mosfet layout and

simulates the behavior.
Microwind software allows the designer to simulate and design an integrated circuit at
physical description level.
It includes all the comments for a mask editor as well as digital tools never gathered before in
a single module.
Microwind works as a comprehensive layout and simulation tool and can be applied to micro
engineering and science.
Layout diagram is used to describe about each layers of CMOS fabrication.
Layout of basic structure has following steps
STEP(0) - start with p-type substrate.
STEP(1) - n well
STEP(2) - active
STEP(3) - poly
STEP(4) - p select
116
STEP(5) - n select
STEP(6) - active contact
STEP(7) -poly contact
STEP(8) - metal 1
STEP(9) - via
STEP(10) - metal 2
STEP(11) – over glass
STEPS FOR LAYOUTS USING DSCH AND MICROWIND
1. Open Dsch2 from following icon.
2. The window will look like this.
117
3. Draw the Layout diagram using the drag and drop tools on right.
4. Click on ‘Run Simulation’ icon on top toolbar which looks like.
5. Run the simulation and toggle the switch ON and OFF.
118
6. Stop the simulation and click on the ‘Timing Diagram’ icon on top toolbar which looks
like.
7. The Timing diagram will open.
8. Goto ‘File’ and click on ‘Save As’.
119
9. Save the .sch file with a unique name.
10. Then again goto ‘File’ and then this time select ‘Make Verilog File’ option.
120
11. The Verilog code will be shown and the name of the file will be given. Remember the
name and then click on [Ok].
12. Close Dsch2 and then open Microwind2 wsing the following icon.
121
13. Goto ‘File’ and select Open.
14. Open the .sch file crested using Dsch2.
122
15. Again goto ‘File’ and select ‘Select Foundry’.
16. Again select the same .sch file.
123
17. Next goto ‘Compile’ and then select the ‘Compile Verilog File’ option.
18. Select the Verilog file created in Dsch2 (It will be a .txt file) and the clcik [Open].
124
19. The verilog code will open as below:
20. Go down and click on [Compile].
125
21. The output will be drawn.
AIM: To design NOT logic gate in switch level modeling using verilog code
Description: The NOT or INVERT function is often considered the simplest Boolean
operation.
1. NOT logic gate Cmos is built using one PFET and one NFET. Gate input ‘a’ is given
common to both FETS and o/p ‘f’ is drawn connecting both FETS in series.
2. If gate i/p a=0 then PFET mp is ON and NFET mn is off. This connect the o/p node ‘f’ to
power supply voltage VDD (i/p) giving an o/p f=1
3. If the gate i/p a=1 then NFET mn is on and PFET mp is off. This connect the o/p node f
to ground (i/p).
Expression for o/p:
f = 𝑎̅ . 1 + a . 0 = 𝑎̅
f = NOT ( a ) =𝑎̅
126
Symbol:
CMOS Diagram:
TRUTH TABLE:
INPUT OUTPUT
a F
0 1
1 0
127
2. DRAW A LAYOUT OF NAND GATE
128
AIM: TO design NAND logic gate in switch level modeling using Verilog code.
Description: NAND gate is called as universal gate. NAND2 logic gate CMOS circuit is built
using 2 parallel connected PFET and 2 series connected NFET.
4. If gate inputs a = b = 1 then PFET are off [p1 & p2] and NFET [n1 & n2] are ON. This
connecting ground (i/p) to o/p node f = 0.
5. If either of gate inputs is zero then o/p node f=1.
6. NAND gate is complement of AND gate.
7. NAND function is negation of ‘and’ function.
Expression for o/p:
f (a , b)=𝑎̅. 1 + 𝑏̅ . 1+ a .b . 0
f = ̅𝑎 +𝑏̅ =𝑎. 𝑏
SYMBOL:
CMOS DIAGRAM:
TRUTH TABLE:
129
INPUT OUTPUT
a B F
0 0 1
0 1 1
1 0 1
1 1 0
3. DRAW A LAYOUT OF NOR GATE
130
AIM:-To design NOR logic gate in Switch level modeling using Verilog code.
DESCRIPTION:-NOR is an universal gate.
NOR2 logic gate CMOS circuit is built using two series PFET (p1&p2) and two parallel
connected NFET (n1&n2).
If both inputs a=b=0 then PFET p1&p2 are ON and NFETS (n1&n2) are off. This connects the
VDD input to output node f=1
If either gate inputs is one then output f=1.
NOR gate is complement of NAND gate.
NOR gate is negation of OR gate.
f (a,b) = . .1 + .b.0 + a. .0+a.b.0
f(a,b)= . =
SYMBOL:
131
CMOS DIAGRAM:
TRUTH TABLE:
INPUT OUTPUT
A b F
0 0 1
0 1 0
1 0 0
1 1 0
132
SAMPLE VIVA QUESTION AND ANSWER
1. List the advantages of SOI CMOS process

Denser transistor structures are possible.
Lower substrate capacitances
No field inversion problem
No latch up
No body effect problem
Enhanced radiation tolerance
2. Distinguish electrically alterable & non-electrically alterable ROM

In electrically alterable ROM the cell can be turned ON or OFF by controlling the
voltages applied to the control gate, source and drain voltages. In non-electrically
alterable ROM versions, the process can only be reversed by illuminating the gate
with UV light.
3. How do you prevent latch up problem?

Latch up problem can be reduced by reducing the gain of parasitic transistors and
resistors. It can be prevented in 2 ways
Latch up resistant CMOS program
Layout technique
The various lay out techniques are
Internal latch up prevention technique I/O latch up prevention technique.
4. List the basic process for IC fabrication

_ Silicon wafer Preparation
_ Epitaxial Growth
_ Oxidation
_ Photolithography
_ Diffusion
_ Ion Implantation
_ Isolation technique
_ Metallization
_ Assembly processing & Packaging
5. What are the various Silicon wafer Preparation?

_ Crystal growth & doping
_ Ingot trimming & grinding
_ Ingot slicing
_ Wafer polishing & etching
_ Wafer cleaning.
6. Different types ofoxidation?

Dry & Wet Oxidation
133
7. What are the advantages of CMOS process?
Low power Dissipation High Packing density Bi directional capability Low Input Impedance
Low delay Sensitivity to load.
8. What is pull down device?

A device connected so as to pull the output voltage to the lower
supply voltage usualy 0V is called pull down device.
9. What is pull up device?

A device connected so as to pull the output voltage to the upper supply
voltage usually VDD is called pull up device.
10. Why NMOS technology is preferred more than PMOS technology?

N- channel transistors has greater switching speed when compared tp PMOS
transistors.
11. What are the different operating regions foe an MOS transistor?
_ Cutoff region
_ Non- Saturated Region
_ Saturated Region
12.What is Channel-length modulation?

The current between drain and source terminals is constant and
independent of the applied voltage over the terminals. This is not entirely
correct. The effective length of the conductive channel is actually modulated
by the applied VDS, increasing VDS causes the depletion region at the drain
junction to grow, reducing the length of the effective channel.
13. What is Latch – up?

Latch up is a condition in which the parasitic components give rise to the
establishment of low resistance conducting paths between VDD and VSS with
disastrous results.
Careful
control during fabrication is necessary to avoid this problem.
14.What is Stick Diagram?

It is used to convey information through the use of color code. Also it is the
cartoon of a chip layout.
15.What are the uses of Stick diagram?

_ It can be drawn much easier and faster than a complex layout.
_ These are especially important tools for layout built from large cells.
134
16.Give the various color coding used in stick diagram?

_ Green – n-diffusion
_ Red- polysilicon
_ Blue –metal
_ Yellow- implant
_ Black-contact areas.
17.Define Threshold voltage in CMOS?

The Threshold voltage, VT for a MOS transistor can be defined as the
voltage applied between the gate and the source of the MOS transistor below
which the drain to
source current, IDS effectively drops to zero.
18.What is Body effect?

The threshold volatge VT is not a constant w. r. to the voltage difference
between the substrate and the source of MOS transistor. This effect is
called substrate-bias effect or body effect.
19.What are the various cmos technologies?
Various cmos technologies are,

• n- well process or n -tub process
ii) p well process or p-tub process
iii) Twin tub process
iv) Silicon on Insulator (SOI) process
20.What is channel-stop implantation?

In n -well fabrication, n-well is protected with resist material. Because it
should not be affected by boron implantation. Then boron is implanted except n-
well. It is done using photo resist mask. This type of implantation is known as
channel-stop implantation.
21.What is LOCOS?
LOCOS mean Local Oxidation of Silicon. This is one type of oxide construction.
135

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VLSI LAB DCET TANVEER SULTANA

DEPARTMENT OF INFORMATION TECHNOLOGY

VLSI LAB MANUAL

B.E. VII Semester CBCS

DECCAN COLLEGE OF ENGINEERING & TECHNOLOGY

Lab Manual for the Academic Year 2020-2021

List of Experiments to be performed

S NO CONTENTS/PROGRAM NAME Page No

I Hardware Description Language

SWITCH LEVEL MODELING

1 Design a NOT gate using CMOS

2 Design a 2-Input NAND gate using CMOS

3 Design a 2-Input NOR gate using CMOS

4 Design an AOI f=ab + ac + bd using CMOS

5 Design an OAI f=(a + b). (a + c). (b + d) using CMOS

6 Design a CMOS transmission gate using switch level modeling

7 Design cmos xor transmission gate using switch level modeling

8. CMOS complex logic gate implementation of function f= d’+a’b’c’

STRUCTURAL GATE LEVEL MODELING

9 Design a Half Adder

10 Design a Full Adder

11 Design AOI (WITHOUT DELAY)using gate level modeling

12 Design AOI (WITH DELAY)using gate level modeling

13 Design OAI (WITHOUT DELAY)using gate level modeling

14 Design OAI (WITH DELAY)using gate level modeling

15 Design a 2:1 MUX using Tri State Buffer

16 Design a S-R Latch

DATA FLOW MODELING

17 Design all logic gates using data flow modeling

MIXED LEVEL MODELING

20 Design mux 4:1using behavioural modeling

21 Design a Positive Edge Triggered Master-Slave D Flipflop

22 Design a Positive Edge Triggered Master-Slave JK Flipflop

23 Design a 8:3 priority encoder

SIMPLE LAYOUT DIAGRAMS

25 Draw a Layout diagram for NOT gate

26 Draw a Layout diagram for a 2-Input NAND gate

27 Draw a Layout diagram for a 2-Input NOR gate

SYNTHESIS OF DIGITAL CIRCUITS

28 Implement Ripple Carry Adder using RTL & Behavioral Modeling

29 Implement Carry Look Ahead Adder using RTL & Behavioral

HDL(HARDWARE DESCRIPTION LANGUAGE)

Generally two types of HDL

(1) VHDL (VHSLC HDL):

In VLSI we have following types of modeling

(1) Structural Gate level modeling.

VLSI DESIGN FLOW

STEPS FOR ISE DESIGN SUIT

1. Open ISE Design Suite 14.5 .

2. Click on File > NewProject...

3. Give a name to the project and click on [Next].

4. Click on [Next] again.

5. Then click on [Finish].

6. Right click in “Hierarchy”.

7. Click on ‘New Source...’.

8. Select ‘Verilog Module’.

9. Give a name to the module then click on [Next].