DESIGN OF LTSSM IN USB 3.

0
 The USB3.0 specification organizes the twelve LTSSM states into four functional groups
 Operational States: U0, U1, U2, U3.
 Link Initialization & Training States: Rx.Detect, Polling, Hot Reset, Recovery.
 Testing States: Compliance Mode, Loopback.
 Other States: SS.Inactive, SS.Disabled.
 The core responsibilities of the LTSSM includes
 Link Training & Initialization
 Power Management
 Error Recovery

LTSSM State Diagram

 The 12 States transitions are as follows:
1. SS.Disable (4’b0000): It is a state where a port’s Super Speed connectivity is disabled with its
receiver termination removed. The port does not receive or transmits any USB signals in this
mode.
 To Rx.detect state when USB 3.0 is connected.

2. SS.Inactive (4’b0001): This mode is entered as a result of receiver removal or other non-
recoverable errors. During SS inactive state a port periodically performs link partner detection
 To Rx.detect state when the link partner is not detected.

3. Rx.Detect (4’b0010): This is the ‘power on’ state.

 To polling state when if the link partner is detected.

4. Polling (4’b0011): In this state link training and initialization. In polling states LPFS handshake
takes place between states before SS training starts. Bit_Lock, Symbol_lock and Rx_Equilization
are also achieved.
 To Rx detect state when there is a timeout in linking of partners.
 To SS disable state when the Super Speed connectivity is failed
 To compliance mode when the 1st hand shaking fails.
 To loop back to check for the accuracy and compatibility of the link partners or to check BER.
 To hot reset when either the device or host to reset all registers and timeouts of both link
partners.
 To U0 when the data transmission has to takes place.

5. U0 (4’b0100): This is the active state.U0 is the normal operational state where packets can be
transmitted and received. All layers are active and working in this state this state consumes
maximum power. So this mode is sustained only as long as super speed packet transfer continues
or is excepted to execute within a stipulated time out period after which this state exit to other
low power states for power saving.
 To recovery when there is error in the transmission of data.
 To U1 when the link command (LGO_U1) is given depending on the time it is in sleep mode to
save power.
  To U2 when the link command (LGO_U2) is given depending on the time it is in sleep mode to
save more power.
 To U3 when the link command (LGO_U2) is given depending on the time it is in sleep mode to
save extreme power.
 To SS inactive when the link is non-recoverable.

6. U1 (4’b0101): It is the low power state where no packets are to transmit. This mode is ‘light sleep’.
 To SS inactive state when device is disconnected.
 To U2 state when it remains in the sleep mode for more time to save more power it will go to
this state
 To recovery state when it exit LPFS.

7. U2 (4’b0110): It is a low power mode that provides more power saving capability compared to U1
but with an increased wake up time. The device goes into ‘moderate sleep’ so it takes a bit longer
than U1 to wake up.
 To recovery state when the device wakes up.
 To SS inactive state when device is disconnected.
8. U3 (4’b0111): It is the deepest low power link state where extreme power saving is provided. The
device goes into ‘deep sleep’ so it takes the longest to wake the device. The host order the device
LTSSM to transition to this state when the host sees that link operation will not be needed for long
and it can be put into inactive state.
 To recovery state when the host or device wakes up.
 In U3 state only LFPS time out takes place.

9. Hot Reset (4’b1000): The mode is used by either the host or the device to reset all registers and
timers of both link partners.
 To SS inactive state when time out takes place.
 To U0 state after the reset complete.

10. Recovery (4’b1001): The RECOVERY state defined in LTSSM is entered whenever the link fails the
operation, or faces some errors or miss-matches. This state performs the retraining of the link and
then resets the device for retrieval of the data transfer mode that it was formerly in.
 To SS inactive state when the link is non-operable.
  To hot reset state for force initialization of device USB3.0 to default state.
 To loop back state for bit error rate (BER) checking.
 To U0 when for a return to normal 5Gbps super speed link operations.
 To Rx detect if a time out or other condition requires full link training to be performed again.

11. Loop back (4’b1010): Loopback is intended for testing the accuracy and compatibility of Super
Speed receiver and transmitter. Loopback includes a bit error rate test (BERT) state machine.
Loopback master is the port that starts loopback and slave is the port that replies back.
 Rx detect state when LPFS handshake timeout.
 SS inactive state when the link is non-operable.

12. Compliance mode (4’b1011): The COMPLIANCE mode is chiefly meant to check if the receiver and
transmitter are in proper alignment. If not, then this mode re-aligns the host and device for proper
data transfer.
 To Rx detect when warm reset is given that is when registers and counters are reset

 Conclusion:

The LTSSM (Link Training and Status State Machine) block checks and memorizes what is received
on each lane, determines what should be transmitted on each lane and transitions from one state to
another.

The LTSSM also performs operations for making the link ready for data transaction in the very beginning
when the device is plugged in. Hence LTSSM is the “DATA FLOW GATEWAY CONTROL” for the device

The LTSSM must inform all the layers before opening or closing the gates for data transaction so as to
save the device from unnecessary resending or loss of data. Each signal has its own significance and
functionality. These signals have been designed up to the USB 3.0 specification’s directions and
requirements.
LTSSM Module
 LTSSM CODE

DUT

module ltssm(
input
clk,rst,lb,idle,low_impedance,lgo_u1,lgo_u2,lgo_u3,lfps_handshake,time_out,rx_termination,error,warm_rst,vbus,
reset,
output reg super_speed,lfps,bit_lock,symbol_lock,rx_equilization,
output [3:0]link_state);//lb=loopback command
reg [3:0]cs,nxt;//cs=current_state,nxt=next_state

parameter ss_disable=4'b0000,
ss_inactive=4'b0001,
rx_detect=4'b0010,
polling=4'b0011,
u0=4'b0100,
u1=4'b0101,
u2=4'b0110,
u3=4'b0111,
hot_reset=4'b1000,
recovery=4'b1001,
loop_back=4'b1010,
compliance_mode=4'b1011;

always@(posedge clk)
begin
if(rst==0)
begin
cs<=hot_reset;
super_speed<=0;
lfps<=0;
bit_lock<=0;
symbol_lock<=0;
rx_equilization<=0;
end
else
cs<=nxt;
end

always@(rst or lb or idle or low_impedance or lgo_u1 or lgo_u2 or lgo_u3 or lfps_handshake or time_out or

rx_termination or error or warm_rst or vbus or reset)
begin

case(cs)
ss_disable:
begin
lfps=0;
super_speed=0;
if(vbus)
nxt=rx_detect;
 end

ss_inactive:
begin
lfps=0;
super_speed=0;
if(warm_rst)
nxt=rx_detect;
end

rx_detect:
begin
lfps=0;
super_speed=1;
if(!warm_rst || rx_termination)
nxt=polling;
end

polling:
begin
lfps=0;
super_speed=1;
bit_lock=1;
symbol_lock=1;
rx_equilization=1;
if(warm_rst)
nxt=rx_detect;
else if(low_impedance)
nxt=compliance_mode;
else if(!vbus)
nxt=ss_disable;
else if(lb)
nxt=loop_back;
else if(idle)
nxt=u0;
else if(reset)
nxt=hot_reset;
end

u0:
begin
lfps=0;
super_speed=1;
if(lgo_u1)
nxt=u1;
else if(lgo_u2)
nxt=u2;
else if(lgo_u3)
nxt=u3;
else if(error)
nxt=recovery;
else
nxt=ss_inactive;
end
u1:
begin
lfps=1;
super_speed=1;
if(time_out)
nxt=u2;
else if(!lfps_handshake)
nxt=ss_inactive;
else if(lfps_handshake)
nxt=recovery;

end

u2:
begin
lfps=1;
super_speed=1;
if(time_out)
nxt=u3;
else if(!lfps_handshake)
nxt=ss_inactive;
else if(lfps_handshake)
nxt=recovery;
end

u3:
begin
lfps=1;
super_speed=1;
if(time_out)
nxt=u3;
else if(!lfps_handshake)
nxt=ss_inactive;
else if(lfps_handshake)
nxt=recovery;
end

hot_reset:
begin
lfps=0;
super_speed=0;
if(!lfps_handshake)
nxt=ss_inactive;
else if(idle)
nxt=u0;
end

recovery:
begin
lfps=0;
super_speed=0;
if(warm_rst)
nxt=rx_detect;
 else if(reset)
nxt=hot_reset;
else if(lb)
nxt=loop_back;
else if(!lfps_handshake)
nxt=ss_inactive;
else if(idle)
nxt=u0;
else if(!vbus)
nxt=ss_disable;
end

loop_back:
begin
lfps=1;
super_speed=1;
if(warm_rst)
nxt=rx_detect;
else if(!lfps_handshake)
nxt=ss_inactive;
end

compliance_mode:
begin
lfps=1;
super_speed=1;
if(warm_rst)
nxt=rx_detect;
end
endcase
end
assign link_state=cs;

endmodule

TB

module ltssm_tb;
reg
clk,rst,lb,idle,low_impedance,lgo_u1,lgo_u2,lgo_u3,lfps_handshake,time_out,rx_termination,error,warm_rst,vbus,
reset;
wire super_speed,lfps,bit_lock,symbol_lock,rx_equilization;
wire [3:0]link_state;

ltssm dut(.clk(clk),.rst(rst),.lb(lb),.idle(idle),.low_impedance(low_impedance),
.lgo_u1(lgo_u1),.lgo_u2(lgo_u2),.lgo_u3(lgo_u3),.lfps_handshake(lfps_handshake),
.time_out(time_out),.rx_termination(rx_termination),.error(error),.warm_rst(warm_rst),.vbus(vbus),
.super_speed(super_speed),.lfps(lfps),.bit_lock(bit_lock),
.symbol_lock(symbol_lock),.rx_equilization(rx_equilization),.link_state(link_state),.reset(reset));
/*initial begin
$monitor("[%0t] link_state=%d super_speed=%b lfps=%0d bit_lock=%b
symbol_lock=%b rx_equilization=%b clk=%b rst=%b lb=%b idle=%b
low_impedance=%b rx_termination=%b lgo_u1=%b lgo_u2=%b lgo_u3=%b
lfps_handshake=%b time_out=%b vbus=%b warm_rst=%b reset=%b
error=%b",$time,link_state,super_speed,lfps,
bit_lock,symbol_lock,rx_equilization,clk,rst,lb,idle,low_impedance,rx_termination,lgo_u1,lgo_u2,lgo_u3,lfps_hands
hake,time_out,vbus,warm_rst,error,reset);
end*/

always#5 clk=~clk;

initial begin

rst=0;
clk=0;
#10; rst=1;
lb=0; idle<=0;low_impedance=0; lgo_u1=0;
lgo_u2=0; lgo_u3=0; lfps_handshake=0; time_out=0;
rx_termination=0; vbus=0; warm_rst=0; error=0; //initilizing all inputs commands to zero

@(posedge clk);vbus=1;//ss_disable

@(posedge clk);warm_rst=1;vbus=0;//ss_inacive

@(posedge clk);warm_rst=0;rx_termination=1;//polling

@(posedge clk);rx_termination=0;warm_rst=1;//rx_detect

@(posedge clk);vbus=1;idle=1;warm_rst=0;//uo

@(posedge clk);idle=0;lb=1;//loop_back

@(posedge clk);lb=0;low_impedance=1;//complince_mood

@(posedge clk);low_impedance=0;reset=1;//hot_reset

@(posedge clk);reset=0;lgo_u1=1;//u1

@(posedge clk);lgo_u1=0;lgo_u2=1;//u2

@(posedge clk);lgo_u2=0;lgo_u3=1;//u3

@(posedge clk);lgo_u3=0;error=1;//recovery

@(posedge clk);error=0;lfps_handshake=1;//recovery

@(posedge clk);lfps_handshake=0;time_out=1;//u2

@(posedge clk);time_out=0;

@(posedge clk);time_out=1;//u3
@(posedge clk);lfps_handshake=1;time_out=0;//recovery

@(posedge clk);lfps_handshake=0;//u3

@(posedge clk);lfps_handshake=1;//recoveryI

@(posedge clk);lfps_handshake=0;//inactive

@(posedge clk);time_out=1;//u3

@(posedge clk);time_out=0;lb=1;//loop_back

@(posedge clk);lb=0;idle=1;//u0

@(posedge clk);idle=0;warm_rst=1;//rx_detect

@(posedge clk);warm_rst=0;reset=1;//hot_reset

@(posedge clk);reset=0;warm_rst=1;//rx_detect

@(posedge clk);warm_rst=0;idle=1;//u0

@(posedge clk);warm_rst=1;idle=0;//rx_detect

end
endmodule

WAVEFORMS