Miniproject

1. Design Verilog to implement synchronous FIFO with following design specification:

The basic block diagram of a synchronous FIFO

• FIFO Depth 256 Locations

• FIFO Data Width 8 bits
Simultaneous access between the write port and the read port
Data is steered into and out of the memory array by two pointers, a read address pointer and write
address pointer.
Supports full and empty status flags
Invalid read or write requests are rejected without affecting the FIFO state
Test Case :

rst write_enable read_enable write_pointer read_pointer full empty

1 x x 0 0 0 1
0 1 0 1 0 0 0
0 1 0 2 0 0 0
0 0 1 2 1 0 0
0 0 1 2 2 0 1

Code:
module sync_fifo(
input[7:0] din, input clk,rst,wen,ren, output reg[7:0] dout

);
reg[7:0] wradp = 8'b0;
reg[7:0] radp = 8'b0;
reg full;
reg[7:0] count;

reg empty;

reg[7:0] mem[0:255];
always @ (posedge clk)
begin
if(rst) begin
wradp = 0;radp = 0;
end
else
 begin
case({wen,ren})
2'b00:begin wradp <= wradp; radp<= radp; end
2'b01:begin wradp<=wradp;radp<=radp+1'b1; end
2'b10:begin wradp<=wradp+1'b1; radp<= radp; end
2'b11:begin wradp<=wradp+1'b1; radp<=radp+1'b1; end
endcase
end
end

always@(posedge clk)
begin
if(rst)
count <= 0;
else
begin
case({wen,ren})
2'b00:count<= count;
2'b01:begin
if(count != 0)
count<= count-1'b1;
end
2'b10:count <= count+1'b1;
2'b11: count <= count;
default: count<= count ;
endcase
end
end

always@(posedge clk)
begin
if(rst)
mem[wradp] <= 0;
else if(wen == 1'b1 && full == 1'b0)
mem[wradp] <= din;

else
mem[wradp] <= mem[wradp];
end

always@(posedge clk)
begin
if(rst)
dout <= 0;
else if(ren==1'b1)

dout <= mem[radp];

else
begin
if(empty)
dout <= dout;
end
end

always@(posedge clk)
 begin
if(count == 8'b0)
empty = 1'b1;
else
empty = 1'b0;
end

always@(posedge clk)
begin
if(count == 8'd255)
full = 1'b1;
else
full = 1'b0;
end

endmodule
Testbench:
module sync_fifo_test(

);
reg clk,rst,wen,ren;
reg[7:0] din;
wire[7:0] dout;
integer i;
sync_fifo uut(.din(din),.clk(clk),.rst(rst),.wen(wen),.ren(ren),.dout(dout));
initial
begin
rst = 1'b1;clk=1'b0;wen = 1'b0;ren = 1'b0;din = 0;
#10 rst = 1'b0;wen = 1'b1;ren=1'b0;
for(i = 0;i<30;i = i+1)
begin
din = din+1'b1;
#10;
end
#10 ren = 1'b1; wen = 1'b0;
#40 wen = 1'b1;ren=1'b1;din = 8'd200;
#50
#50 ren = 1'b0;
#200 $stop;
end
always #5 clk = ~clk;
endmodule
Simulation:

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