Electronics and Communications in Japan, Vol. 97, No.
7, 2014
Translated from Denki Gakkai Ronbunshi, Vol. 132-C, No. 12, December 2012, pp. 1927–1933
Design Technology of Stacked Type DTMOS
YU HIROSHIMA,1 TAKAHIRO KODAMA,2 and SHIGEYOSHI WATANABE3
1 Oi
Electric Co., Ltd, Japan
2 Japan Process Development Co., Ltd, Japan
3 Shonan Institute of Technology, Japan
SUMMARY
Stacked type DTMOS, which makes it possible to
realize both the high-speed, low-power characteristics of
FinFET type DTMOS and small the pattern area of stacked
transistors, has been newly proposed. The delay time of
the substrate of stacked type DTMOS can be reduced to
less than 10% of that for conventional FinFET type DT-
MOS by using the sidewall connection between the gate
and substrate. By using a stacked structure of NMOS with
a (110) substrate on PMOS with a (100) substrate, high-
speed performance with optimized mobility value can be
realized without sacrificing the pattern area. Furthermore,
the pattern area of the inverter/NAND circuit, LSI for com-
munication, and the DRAM buffer circuit with stacked type
DTMOS is compared with that of conventional FinFET
type DTMOS. The newly proposed stacked type DTMOS
is a promising candidate for realizing high-performance
system LSI such as GHz class microprocessors. C⃝ 2014
Wiley Periodicals, Inc. Electron Comm Jpn, 97(7): 55–62,
2014; Published online in Wiley Online Library (wileyon-
linelibrary.com). DOI 10.1002/ecj.11584
Key words: FinFET; stacked structure; DTMOS;
pattern area; system LSI.
1. Introduction
In the design of system LSIs, demand is growing for
high integration, high-speed, and low-power consumption.
DTMOS devices were proposed to implement high-speed
and low-power consumption by dynamically varying the
transistor thresholds [1, 2], but there is a problem increased
pattern area. In order to solve this problem, we previously
developed FinFET type DTMOS structures in which DT-
MOS is implemented on a small area [3].
55
Power-efficient processors operated at a relatively
high speed of 60 MHz under the voltage of 0.45 V have
recently been proposed for portable devices [4]. Commer-
cial production of microprocessors using FinFET, offering
more compact design, higher speed and lower power con-
sumption than planar transistors [5, 6], and usable for the
realization of GHz-band low-power microprocessors for
portable devices, is expected.
In the previously proposed FinFET DTMOS, the top
portion of the gate is connected to the substrate, which
allows a relatively simple fabrication process. On the other
hand, it takes time for signals to propagate from the Fin-
FET connection to the lower part of the substrate, which
may impede GHz-class operation. In addition, GHz-class
operation requires improvement of the current drivability
(hole mobility) of MOS, especially of PMOS transistors,
and few studies have proposed implementation on the LSI
level rather than the transistor level [7].
In this paper, we propose a new stacked type DTMOS
that combines stacked-structure transistors, offering even
smaller area than FinFET [8, 9], with DTMOS, while taking
account of substrate orientation. In such stacked DTMOS
with regard for substrate plane orientation, the gate and
substrate are connected on the sidewall. As a result, the
propagation time of signals from the connection to the
substrate can be reduced compared to the conventional Fin-
FET DTMOS. Furthermore, the PMOS current drivability
(hole mobility) can be improved at the LSI level by taking
account of the substrate orientation in the stacking process.
This paper is organized as follows. The structure of
stacked DTMOS is explained in Section 2. Then, the oper-
ation acceleration effect due to the introduction of stacked
DTMOS is explained in Section 3, and the effect of pattern
area reduction in NAND and other simple logic circuits
is explained in Section 4. The effect of pattern area re-
duction in full adders, communication LSIs, and DRAM
buffer circuits is explained in Section 5. Future prospects
C⃝ 2014 Wiley Periodicals, Inc.
 Fig. 1. Structure of staked DTMOS.

are described in Section 6, and a brief summary is given in

Section 7.

2. Structure of Stacked DTMOS

In the previously proposed FinFET DTMOS [3], the

top portion of the gate is connected to the substrate, which
did not require an additional area. In the stacked DTMOS
proposed in this paper too, DTMOS is implemented with-
out taking any additional area. The structure of the stacked
DTMOS is shown in Fig. 1. The sidewall on one side is
used as the gate. The gate insulating film is removed on the
opposite side to provide connection to the substrate.
As will be explained later, this structure offers both
further improvement of the DTMOS characteristics in
terms of speed and power consumption, and reduction of
the pattern area of the stacked transistors. Since the gate
and substrate are connected by the sidewall, the distance
from the connection to the substrate depth becomes shorter
than in the conventional FinFET DTMOS, which results
in a shorter signal propagation time, thus contributing to
fast operation (for details, see Section 3). In addition the
PMOS substrate and NMOS substrate can be formed se-
quentially in the fabrication process, and by taking account
of the respective plane orientations, one can improve the
PMOS current drivability (hole mobility) at the LSI level
(for details, see Section 3).
The fabrication process of the stacked DTMOS is
shown schematically in Figs. 2(a) to (d). First, the PMOS
(100) substrate is formed. The (100) substrate is employed
because the (110) plane, with the highest hole mobility, is
used for electrical conduction of the PMOS FinFET formed
perpendicular to the substrate. The PMOS (100) substrate is Fig. 2. Process steps of stacked DTMOS.
formed the by SIMOX (Separation by Implanted Oxygen)
process as described below. This is because the SIMOX
process offers excellent controllability and other process

56

Fig. 3. Parameters related to delay time of substrate.
characteristics, and a PMOS (100) substrate with a thick-
ness of 5 F = 70 nm × 5 = 350 nm can be realized by
adjusting the acceleration voltage and dose of implanted
oxygen ions (in Ref. [8], a PMOS (100) substrate about
100 nm thick was obtained at an acceleration voltage of
130 keV and a dose of 4.5× 1017 cm−2 ). After that, an
insulating oxide with a thickness of about 70 nm (F) is
deposited (in Ref. [10], an oxide film of 30 nm to 100 nm
was formed).
Then, an NMOS (110) substrate with different ori-
entation is formed on top by bonding (a). The (110) sub-
strate is employed because the (100) plane, with the high-
est electron mobility, is used for electrical conduction of
the NMOS FinFET formed perpendicular to the substrate.
The desired thickness of the NMOS (110) substrate can be
obtained by adjusting the acceleration voltage and dose of
the implanted oxygen ions (in Ref. [10], the (110) substrate
was bonded to the (100) substrate formed by SIMOX via
an insulating film). After that, two lateral surfaces of the
PMOS substrate and two lateral surfaces and the top surface
of NMOS substrate are oxidized (b). Then, the oxide film
is removed from one lateral surface of the NMOS substrate
and the PMOS substrate (c). In the case of conventional
FinFET reported in Ref. [11], a single-sided film removal
process is used to obtain different thicknesses of the gate
insulating films on the two sides of the gate. Thus, a single-
sided film removal process seems industrially feasible. Fi-
nally, the gate electrode is formed (d). Thus, the stacked
DTMOS shown in Fig. 1 can be implemented with relative
ease.
3. Acceleration of Operation by Introduction of
Stacked DTMOS
In this section, we estimate how much the operation
speed can be improved by the introduction of stacked DT-
MOS.
First, we estimate the time constant from the gate-
substrate connection to the substrate. The parameters used
for estimation are shown in Fig. 3. Both the silicon pil-
lar width W and the gate length L in the conventional
57
FinFET DTMOS and stacked DTMOS are assumed equal
to design rule F. The sidewall channel width Dconv of
the conventional FinFET DTMOS is set to 2.5 F, and the
sidewall channel width of the stacked DTMOS is set to
5 F. The 70 nm design rule is assumed, and the impurity
concentration in the substrate portion is 1017 cm−3 . The
substrate resistance RS of the conventional FinFET DT-
MOS calculated using this values is about 35 KΩ. The
stray capacitance CS of the substrate calculated from the
gate capacitance and junction capacitance is about 0.5 fF.
Thus, the substrate’s time constant, defined as the product
of RS and CS, is about 18 ps. This value is greater than the
12 ps delay time of the basic NAND circuit of a GHz-class
microprocessor [12]. That is, in terms of the substrate’s
delay time, the conventional FinFET DTMOS is suitable
for microprocessors operated at about 100 MHz, but opera-
tion in GHz band is problematic. In addition, the transistor
threshold voltage may be widely distributed because of the
difference in distance from the gate-substrate connection to
the substrate. In contrast, in the stacked DTMOS, the gate
and substrate are connected on the sidewall, and thus the
substrate resistance RS can be reduced to less than 10%
of that in the conventional FinFET DTMOS, that is, to
35 × (1/2.5) × (1/5) = 2.8 KΩ. Accordingly, the delay time
too can be reduced to 1.4 ps, which is suitable for GHz
operation. The distance from the gate-substrate connection
to the substrate is constant in the stacked DTMOS, and
hence there is no concern about wide distribution of the
transistor threshold voltage.
Next, we explain how the PMOS driving performance
can be improved at the LSI level by taking account of the
substrate plane orientation during the fabrication of the
stacked structure. The substrate plane orientation depen-
dence of transistor’s mobility was previously investigated
to enhance the current drivability of MOS transistors. In
planar transistors where current flows in the direction of
the crystal plane, the current drivability of both NMOS
and PMOS is known to be maximized when NMOS is
formed on (the 100) substrate and PMOS is formed on the
(110) substrate [13, 14]. In the common case in which the
planar NMOS and PMOS structures of LSIs are formed on
substrates with the same plane orientation, (100) substrates
are employed to seat NMOS, which higher mobility than
PMOS, thus sacrificing the current drivability of the PMOS.
In this approach, no additional pattern area is required
but the current supply capacity of the PMOS drops by
about 40% compared to the optimized mobility conditions
[15–17].
In FinFET, where current flows in the direction per-
pendicular to the crystal plane, the current drivability of
both NMOS and PMOS can be maximized when the NMOS
and PMOS are arranged at an angle of 45◦ (135◦ ) on the
same (100) substrate, as shown on the left of Fig. 4.
That is, by using this method, maximum current
drivability of both NMOS and PMOS is implemented on

Fig. 4. Selection of substrate orientation and placement
of FET for large current drivability.
silicon substrates with the same plane orientation, which
was impossible in the case of planar transistors (this method
applies to both common FinFET structures and FinFET DT-
MOS). However, for this purpose, the NMOS and PMOS
patterns must be arranged at an angle of 45◦ (135◦ ), which
increases the pattern area by about 40% [18]. (If the patterns
are not arranged at an angle of 45◦ (135◦ ) so as to prevent
this increase in area, the PMOS current supply capacity
drops by about 40%, as in the planar design.)
These problems can be solved as follows. The PMOS
and NMOS can be formed sequentially and independently
in stacked DTMOS (Fig. 2), and therefore, if the PMOS
is formed on the (100) substrate and the NMOS is formed
on the (110) substrate, as shown on the right of Fig. 4,
then the NMOS can be formed immediately above the
PMOS, without the oblique arrangement and interconnec-
tions, thus assuring maximum performance of both NMOS
and PMOS. That is, compared to the design shown at the
left of Fig. 4, the same speed can be achieved without an
increase of about 40% in the pattern area. Compared to the
conventional design in which the NMOS and PMOS gates
are arranged in parallel, the use of stacked DTMOS offers
enhanced PMOS current drivability, and therefore faster
operation of NAND circuits and other basic logic circuits.
Thus, we estimated how much the operation speed can be
increased in stacked DTMOS compared to the conventional
parallel arrangement of NMOS and PMOS. First, we de-
termined the hole mobility when the silicon side surface
of the FinFET channel is formed on the (100) side surface
(corresponding to NMOS FinFET formed on the (110) sub-
strate) and the (110) side surface (corresponding to PMOS
FinFET formed on the (100) substrate). According to de-
vice simulations [15] adjusted to measured values of the
planar transistor mobility [16, 17], the mobility of PMOS
FinFET at a charge density Ninv = 2 × 1012 cm−2 in the
inversion layer is 160 cm2 /vs at the (100) side surface and
270 cm2 /vs at the (110) side surface, that is, a ratio of 1.68.
With the higher charge density Ninv = 1 × 1013 cm−2 in the
inversion layer, the mobility is 90 cm2 /vs at the (100) side
surface and 220 cm2 /vs at the (110) side surface, so that the
58
Table 1. Relations between selection of substrate
orientation/placement of FET and delay time/pattern area
Layout of Delay Pattern
FET time area
Planar 1 1
FinFET
FinFET
DTMOS
FinFET 0.7–0.8 1.4
FinFET
DTMOS
Stacked 0.7–0.8 0.55–0.89
DTMOS
ratio increases to 2.44. Assuming that these results apply to
the 70 nm design rule adopted in this study, we found the
delay time in the basic logic circuits [19]. The components
of delay time, namely, the delay due to NMOS discharging
and the delay due to PMOS charging, are assumed to be
equal in the case of NMOS on the (100) side surface and
PMOS on the (100) side surface. On the other hand, the
delay due to PMOS charging decreases when the (110) side
surface is used for PMOS, as in this study. Thus, the total
delay time can be reduced to 1/2 + (1/2) 1.68 = 0.8 a at
charge density Ninv = 2 × 1012 cm−2 , and to 1/2 + (1/2)
2.44 = 0.7 at a charge density Ninv = 1 × 1013 cm−2 . The
above results are summarized in Table 1. As can be seen
from Table 1, the introduction of stacked DTMOS offers
a 20% to 30% increase in speed compared to the parallel
placement of NMOS and PMOS (the effect of pattern area
reduction will be discussed in Sections 4 and 5).
4. Area Reduction Effect in Basic Logic Circuits
In Section 3, we explained how the operation speed
is increased by the introduction of stacked DTMOS. In
this and the next sections, we explain how the pattern area
is reduced by the introduction of stacked DTMOS. We
investigated the effect of pattern area reduction when the
proposed stacked DTMOS is used in inverters, NAND, and
other basic logic circuits. The design rules are shown in
Table 2 (the channel width is 5 F). In every design, the rules
for the gate length, wiring, and contacts are set the same.
In addition, the allowance for the diffusion layer around
the contact was set to 0.5 F, and the distance between the
gate contacts was set to F. In FinFET DTMOS and stacked
 Table 2. Design rule for pattern design
Planar FinFET Stack
Planar DTMOS DTMOS DTMOS
Gate length F F F F
Wiring F F F F
Wiring to Wiring F F F F
Contact size F×F F×F F×F F×F
Sidewall channel width 2.5F 5F
Height of silicon substrate 2.5F 11F
Fig. 5. Layout pattern of two-input NAND (W = 5F).
DTMOS, a transistor with a channel width of 5 F is made
the minimum unit, and therefore the sidewall channel width
is 2.5 F for FinFET DTMOS, where both sidewalls can be
used, and 5 F for stacked DTMOS, where only one side can
be used. In stacked DTMOS, the NMOS is stacked on top
of the PMOS by means of insulating film with a thickness
F, and therefore the height of the silicon substrate is 5 F + F
+ 5 F = 11 F.
As an example, the pattern layout of a two-input
NAND is shown in Fig. 5. Taking the pattern area of the
conventional planar transistor design as 100%, the area
increases to 120% in the case of planar DTMOS because
of the connection between the gate and substrate. On the
other hand, the area can be reduced to 70% with FinFET
DTMOS, and to 68% with stacked DTMOS (86% of that
for FinFET DTMOS). We also examined NAND circuits
with more than two inputs and with the channel wider than
5 F. The results obtained for pattern area reduction are sum-
marized in Fig. 6 (in basic logic circuits, the area reduction
ratio is governed by the channel width, regardless of the
number of inputs; the area of the planar design is taken
as 100%). As can be seen from the graph, the pattern area
reduction increases with wider channels for any transistor
structure. In the case of planar DTMOS, the proportion of
the gate-substrate connection portion specific to DTMOS
decreases as the channel width is increased, and the pattern
area of planar DTMOS approaches that of planar design
59
Fig. 6. Pattern area ratio of inverter and NAND.
(100%). In the case of FinFET type DTMOS, the proportion
of the irreducible well spacing area decreases as the channel
width is increased, so that the area reduction effect grows.
In the case of stacked DTMOS, the area reduction effect
grows even stronger with a wider channel (86% of that for
FinFET DTMOS at a channel width of 5 F, and 55% at
80 F).
5. Area Reduction Effect in Full Adders,
Communication LSIs, and So On
Thus, we found that stacked DTMOS offers a greater
reduction of pattern area in basic logic circuits than FinFET
DTMOS. For further investigation of the area reduction
effect, we designed a more complex circuit, namely, a full
adder. We used the same design rules and transistor channel
width (= 5 F) as in the basic logic circuits. The circuit
diagram and layout patterns of the full adder are shown in
Fig. 7. The pattern area of conventional planar design was
taken as 100%. Thus, we obtained values of 113.45% for
planar DTMOS, 90.81% for FinFET DTMOS, and 80.65%
for stacked DTMOS (89% of that for FinFET DTMOS).
Since the wiring area cannot be reduced, the area reduction
ratio is somewhat lower here; however, just as in the case
of the basic logic circuits, stacked DTMOS offers a greater
area reduction than FinFET DTMOS.
In the case of transistors with a wider channel (10 F),
the when sidewall channel width is greater than in Table
2 (5 F for FinFET DTMOS, 10 F for stacked DTMS),
even higher area reduction ratios can be obtained, namely,
67.96% for FinFET DTMOS and 60.36% for stacked DT-
MOS (89% of the value for FinFET DTMOS).
We then estimated the pattern area when stacked DT-
MOS was applied to the cell library of a communications
LSI [20, 21] composed of the basic logic circuits considered
in Section 4, and to the cell library of DRAM buffer circuits.
In the former case, the proportion of transistors with narrow
channels is large; in the latter case, the proportion of transis-
tors with wide channels is large. The pattern area reduction
 Fig. 8. Pattern area comparison for system LSI for
communication: (a) planar, (b) planar DTMOS, (c)
FinFET DTMOS, (d) stack DTMOS.
Fig. 7. Two-input NAND/NOR: (a) circuit diagram, (b)
planar layout, (c) planar DTMOS layout, (d) FinFET
DTMOS layout, (e) stacked DTMOS layout.

effect for the communication LSI cell library is illustrated

Fig. 9. Pattern area comparison for buffer circuit for
in Fig. 8 (the diagram shows a breakdown of the pattern
DRAM.
area by the basic logic circuits of the communication LSI;
the number of inputs and the channel width are plotted on
the vertical and horizontal axes, respectively). As in the
basic logic circuits, taking the pattern area of conventional
planar design as 100%, the area obtained was 117% for
planar DTMOS, 65.61% for FinFET DTMOS with opti-
Fig. 10. Pattern area comparison for buffer circuit for
mized channel width (sidewall channel width 2.5 F), and
DRAM with optimized sidewall channel width.
54.19% for stacked DTMOS (83% of the value for FinFET
DTMOS). These results are close to those shown in Fig. 6
for channel widths of 5 F and 10 F. This is because most of MOS (58% of the value for FinFET DTMOS). DRAM
the channel width in communication LSI involves 5 F and buffer circuits are composed of multistage inverters, and
10 F transistors, as shown in Fig. 8(a). the channel width increases from stage to stage [22, 23].
We performed similar estimations on DRAM buffer For this reason, the effect of pattern area reduction due
circuits. The sidewall channel width was set to 2.5 F for Fin- to the introduction of the 3D structure is greater than in
FET DTMOS and 5 F for stacked DTMOS, as in Table 2. communication LSIs with narrow channel width. In DRAM
Taking the pattern area of the conventional planar design as buffer circuits, many transistors have a wide channel,
100%, the area obtained was 102.97% for planar DTMOS, and hence the optimal sidewall channel width in FinFET
44.46% for FinFET DTMOS, and 25.94% for stacked DT- DTMOS and stacked DTMOS is greater than the 2.5 F

60
and 5 F of communication LSIs. Analysis showed that the duction of the pattern area. The gate and substrate are con-
pattern area is minimized at 7.5 F and 15 F, respectively. In nected using the whole area of the silicon pillar sidewall,
this case, too, stacked DTMOS offered a greater reduction and as a result, the substrate’s delay time can be reduced
of the pattern area than FinFET DTMOS. below 1/10 compared to the conventional FinFET DTMOS.
In addition, the NMOS is stacked on the (110) plane on
top of PMOS formed on the (100) plane, and as a result,
6. Future Prospects
high-speed operation can be achieved by using the optimal
mobilities of both the NMOS and PMOS without requiring
In this investigation, we examined the operation
additional pattern area. We applied the stacked DTMOS to
speed, determined by the substrate’s time constant and the
inverter, NAND, and other simple logic circuits as well as to
mobility of NMOS and PMOS at a 70-mm design rule.
a full adder, a communication LSI, and a DRAM buffer cir-
We now compare the operation speed of the conventional
cuit. We found that the pattern area was reduced compared
FinFET DTMOS and the proposed stacked DTMOS when
to the conventional FinFET DTMOS, to 44% to 86% for
the design rule is reduced below 70 nm.
the inverter, NAND, and other simple logic circuits, 89%
DTMOS has a partial depletion structure and it is
for the full adder, 84% for the communication LSI, and
difficult to reduce the impurity concentration in the sub-
58% for the DRAM buffer circuit. The proposed stacked
strate on miniaturization. Thus, we assumed an impurity
DTMOS is a promising solution for future implementation
concentration of 1017 cm−3 , as with the 70 nm design rule.
of microprocessors for portable devices operated in the
Thus, the ratio of the substrate time constants of the FinFET
GHz band and other advanced system LSIs.
structure and the stacked structure can be expressed as (Fin-
FET silicon pillar width)/(FinFET silicon pillar height) ×
(stacked silicon pillar width)/(stacked silicon pillar height).
In terms of the design rule, this value is (F/2.5F) × (F/5F)
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AUTHORS (from left to right)

Yu Hiroshima (nonmember) graduated from Shonan Institute of Technology (Grad. School of Engineering, Dept. of
Information Science) in 2010. Student research dealt with LSI design methods using double-gate type transistors and stacked
transistors (3D transistors). Now employed by Oi Electric Co., Ltd.

Takahiro Kodama (nonmember) graduated from Shonan Institute of Technology (Grad. School of Engineering, Dept. of
Information Science) in 2012. Student research dealt with LSI design methods using SGT, FinFET, and other 3D transistors.
Now employed by Japan Process Development Co., Ltd.

Shigeyoshi Watanabe (member) received a bachelor’s degree in measurement engineering from Keio University in 1977,
completed the M.E. program in applied physics at Tokyo Institute of Technology in 1979 and joined the Toshiba Center for
Semiconductor Research and Development. Research interests: nonvolatile memory and DRAM circuit design, devices and
circuits using micro CMOS, BiCMOS, SOI, 3D transistors, high-speed low-power circuit architecture for system LSIs, and so
on. Since 2005 professor at Shonan Institute of Technology (Dept. of Information Science) (D. Eng.).

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