INTRODUCTION TO MICROPROCESSORS

3.3.4 Interrupt Acknowledge (INA) Timing

The Interrupt Acknowledge machine cycles in response to the interrupt INTR are shoWn in Pigs.
8.10a and 3.106. If the interrupt enable flip-flop (INTE FF) has been set by the El (Enabie
Interrupt) instruction, then the INTR line is sampled for a high levelduringthe penultimate cock
the If
pulse of every instruction (the TRAP and RST pins are also sampled in a similar manner).
onyvalid interrupt is INTR (so that prioritywise it has no conflicts), the CPU resets the INTE

np-1lop and enters into an Interrupt Acknowledge (INA) machine cycle. The INA cycle and OP
sends out a RD, INA sends
ycle are identical except for two differences which are: () While OF
while in OF, I0/M 0. (In INA, =

out anINTA (on the ÎNT pin); (i) During INA, IO/M 1, =

address lines, but that is of no

during Tl of M1 INA the contents of the PC are sent out on the
the INTA is sent out during T2,T3
consequence.) In response to the sampling of the interrupt,
is expected to provide an opcode
on
of Mi (NA); during this period the external interrupt logic
instruction, additional
bus to be read by the processor. If the opcode implies a multibyte
the data INA machine cycles (see Figs.
3.10a and
INTAs are sent out by the CPU during the subsequent
of course, El
the remaining bytes.
in
to clock While the opcode could be anything (except,
3.106) because they could be used to
make
and D) the RESTARTS and CALLS are most commonly used
in response to the
a predetermined program
the program jump to some other location to execute

INTR.

MINA) M2(INA)
M2MR)
SIGNALS
T4TT6 TI T2 T3
T2T3TI12 13
CLOCK

INTR

NTA

1o/M,S1,S0 (0,1,0) (1,1,1) 1,1,1)

PCH PCH
A8-A15 (PC1)H
OUT IN OUT
N
ADO-AD7
(raLo.eA PCL DO-p7(E

ALE

RD

WR

Fiure 3.10a 8085A Interrupt Acknowledge Machine Cycles

(Source: Intel Corporation)

30
 THE 8085A CPU
SIGNAL M3 (INA) M4 (MW) MS (MW) Mi (OF)
TiT2 T3 TIT2T3 TiT2T3 TiT2
CLOCK
INTR
INTA
oMS1,S0 X K1, 1, 1 0, 0, 1 0, 0, 1X 0, 1, 1
A8-A15 PCH (B3)
PCL (SP-1) H (SP-2) H
OUT
OUT oUT OUT oUT OUT
ADO-AD7
ALE
RD
WR
Figure 3.10b 8085A Interrupt Acknowledge Machine Cycles (Contd.)
(Source: Intel Corporation)
If it is a CALL routine, then it is necessary to fetch the two bytes of the CALL address
the
through two INA machine cycles (M2 and M3 in the diagram). It is also necessary to save
address of the main program the CPU was handling when the interrupt appeared. This is done
bus
by storing the contents of the PC onto the Stack, executed by placing first SP-1 on the address
and storing the high-order byte of the PC (PCH), then placing SP-2 on the address bus and
storing the low-order byte of the PC. (PCL). In the next machine cycle (which would be OF) the
address of the CALL subroutine is placed on the address bus (B3 the high-order byte on A8-
A15, and B2- the low-order byte on ADO-AD7), which would result in the CALL subroutine to
be executed.
The CPU inhibits incrementing of the PC during the INA cycles so that the correct PC can
be stored onto the Stack during M4 and M5.
3.3.5 Bus Idle (BI) and Halt State
There could a few situations when the machine cycles are neither READ nor WRITE, such as
(i) To execute the DAD instruction (this instruction adds the contents of a specified register pair
to the contents of H and L) ten T-states are needed. Rather then having M1 of ten clock
cycles, it generates the extra machine cycles which do not involve either memory or 1/0.
31
 INTRODUCTION TO MICROPROCESSORS
IDLE eycles
these BUS
case of DAD,
machine cycles. In the ALE is not
These are called BUS IDLE (B) low ever and
does not go
difference is that RD
are identical to MR cycle. The M3 cycles of DAD.
during M2 and
generated. Further, READY is ignored or TRAP
internal opcode generation
for the RST
also appears during trigger at the
The rising edge
(ii) BUS DLE cycle illustrated for RST 7.5
in Fig. 3.11. of the last but
one
interrupts; the cycles are on the falling edge
that is sampled but without
sets an internal latch (identical to OF
KST 7.5 input then enters a BUS
IDLE machine cycle
RESTART instruction,
putting
clock period. The CPU is own
generates Program
causing the RD to go low)
during which it address of RST
7.5) on to the
003CH (vector executed. During
the
PC onto the Stack and placing 7.5 can be
the (ISR) of RST
routine
so that the interrupt service
Counter
BI cycle the READY line is ignored.
MI (B)
M2 (MW)
SIGNALS
MI(OF)
Ti T2
T3 T4 TS T6 TIT2
T3 T4
CLOCK
RST 7.5
1O/M
S1, So
SP H
A8-A15 CPC-1H PCH
OUT
IN
N
(SP-13LPCH
ADO-AD7 L
ALE
ÎNTA
RD
WR
RBADY
Figure 3.11 Bus läle Machine Cycle For RST 7.5
(Source: Intel Corporation)
The BUS DLE state entered during a HALT state with the RST 7.5 triggered is shown in
Fig. 3.12. In M2, the CPU is in THLT the dashed lines indicate the floating signals. Appearence
ofa valid interrupt can cause the processor to exit the TuT State. The CPU resets the INTE FF,
this disables permanently further interrupts and moves to the T1 state
(T1.M1) of the next
instruction. (The HOLD input makes the CPU exit THALT
beyond which it returns to THALT).
temporarily for the duration of the THOLD
32
 THE 8085A CPU
Mi (OF) M2 (HALT)
SIGNALS
T3 T4 Mi( M2 (MW)
T1THAr THALT T1T2T3 T4 TS T6 TI
CLOCK
RST 7.5
oM
S1,
A&-A1S
(ciH CH PCH (SP1
N OUT IN
OUT OUT
ADO-AD7 HALT PO
ALE
INTA
RD
RRADY
Figure 3.12 Halt and Bus Idle cycles with RST 7.5 terminating THALT State
Source: Intel Corporation)
In Fig. 3.12 the rising edge of RST 7.5 trigger sets an internal latch that is sampled during CLK
1 of every TrALT State (besides during a high clock occurring two clock cycles before any M1.T1).
Thelatched interrupt high (due to INTE FF = 1 or RST 7.5 mask 0) forces the CPU to exit
THALT State at the end of the following clock period and to enter Mi.T1.
3.3.6 Hold and Halt States
When the CPU is in THOLD State, it relinquishes the bus; in this situation external devices can gain
control of the bus and the bus can be used for DMA, for example.
As regards THOLD and THALT states, three situations can occur:
) The CPU is in TaAr state:
During CLK = 1 of every TrALT state the processor internally latches, (a) The state of the
HOLD line, and (b) Any unmasked interrupts. If the HOLD is high, then on the following
CLK 1, the CPU exits THALT and enters THoLD This takes place even if a valid interrupt
appears simultaneously with the HOLD signal.
33
 INTRODUCTION TO MICROPROCESSORS

(i) The CPU is in THOLD 5tate:

the atate of the
=
internally latches: (a) =
CLK 1 of every TuOLn State, the processor then following CLK
During If the HOLD is low,
HOLD line, and (b) any unmasked interrupts. entered THoLD from THALT, Or
it had originally
TsoLy and (a) enters THALT if due to a high HOLD
1, the CPU exits at the time it entered THoLD
the program it was executing
(6) returns to
input. thereafter all
enabled interrupt;
the CPU accepts only the first unmasked
As regards interrupts, When it emerges from the
are ignored regardless
of their intrinisic priorities.
other interrupts
HOLD state, the CPU services the interrupt.

(ii) The CPU is neither in TuALT nor in THoLD

or TwAT) or the
last state before T5
= 1 of the last state before T3 (T2
Then during CLK the HOLD line.
(T4 of a six T-state M1) the CPU latches internally
CPU enters
in the following CLK, the
the next CLK 1, the HOLD is high, then
Ifduring
THOLD
latches the
state before each M1.T1, internally
The CPU, during the clock of the last but one
state of any unmasked interrupt.

3.3.7 Power ON and Reset IN

Due to its internal constraints, on POWER ON, when the Vcc terminal of 8085A reaches 4.75V
level, the device takes at least another 10 ms to perform satisfactorily. To circumvent any problem
due to this eonstraint, it is suggested that the RESET IN pin be kept low during this period. A
simple cireuit which achieves this satisfactorily is given below:

Vcc
MANUAL RESET

RESET IN

Circuit to generate Power-On Reset-In

(Source Intel Corporation)

In every elock cycle, whenever the CLK

goes high, the 8085A latches the
signal on the RESET IN
34
 THE 8085A CPU

input. The CPU recognises, only during the CLK 1 of the next T state, presence of
RESET IN signal. f RESET IN is found low, the CPU then outputs RESET OUT any and1atcned
=

enters
TRESET during the next T state. It is recommended that the RESET ÎN be kept low for a minimum
of three clock periods for necessary synchronisation after which the RESETN could be allowed
to go high.Then the CPU enters M1.TI during the next T1 state, and with PC 0000H, it starts
executing instruction_, with the interrupt system masked, from 0000HA

3.3.8 SID and SOD Signals

The timing relationship between SID sigmal, and execution of RIM (which loads SID signal to bit
D7 of the Accumulator) is shown in Fig. 3.13. During T3.CLK = 0 of the RIM instruction, the
status of the SID is internally latched. The figure also shows the relationship of SIM (which loads
bit D7 of the Accumulator signal to SOD, provided bit 6 is 1) with the SOD signal. The transfer
takes place during Mi.T2. CLK = 0 of the instruction that follows SIM or RIM.

SIGNAL M1 (OF Mi(OF) M1(OP

Ti T2 T3 T4 T1 T2 T3 T4
T3 T4 T1 12
CLOCK

SOD

SID

ACCUMULATOR
(BT 7)

A8-A1S

OUT N OUT |IN IN

ADO-AD7 RIM SIM |RDM

ALB

RD

Figure 3.13 8085A RIM and SIM instructions timing

(Source: Intel Corporation)

35
 CHAPTER 4

The 8085A Instruction Set

two, and
1. The 8085A Instruction Set consists of one-,
is always the
three-byte instructions. The first byte
the second byte is
opcode; in two-byte instructions
instructions the last two
usually data; in three-byte
address.
bytes represent some

into five
2. The Instruction Set can be categorised
of functions the
different groups based on the nature
Transfer group (i)
instructions carry out; (i) Data
Arithmetic group, ( ) Branch group, (iv) Logic group,
Machine Control
and (v) Stack, Input/Output, and
group.
data
3. The Data Transfer group instructions load given
into registers, move data between registers, and move
data between registers and memory locations. The
Arithmetic group instructions add, subtract, increment
or decrement data in registers or in memory.
In
addition, there is one instruction in which eight-bit
data is adjusted to form BCD digits. The Branch group
instructions include calling of subroutines, conditional
and unconditional jumps, returns, and restarts. The
Logic group instructions perform logie operations such
as AND, OR, and XOR, compare data between
registers, or between register and memory, rotate or
complement data in registers. The Stack, Input/Output
Machine Control group instructions transfer data
and
between registers and the Stack, exchange contents of
SP and HL with Stack Top, move data to and from
specific Input/Output ports, enable or disable
Interrupts, and handle Interrupt masking.

This Chapter presents the 8085A Instruction Set. The

instructions are presented in five
G) the Data Transfer group (Move, Load, Store, ete groups:
instructions), (i) the Arithmetic group
Increment, Decrement, Add, Subtract, etc instructions), (ii) the Branch
Return, Restart, ete instructions), (iv) the Logic group group (Jump, Call,
(AND, OR, Compare, Rotate, etc
instructions), and (v) the Stack, Input/Output, the Machine control
EI, DI, ete instructions). In this Chapter, individual group (PUSH, POP, IN, OUT,
mnemonics are followed by a
description of
36
 THE 8086A
INSTRUCTION SET
what the execution of the
instruction achieves. The
and the mnemonics for all the Operational Codes (opcodes, in hexadecmalis
along with a Table in which theinstructions are given in Table 4.1. For convenience, Table 4.
order, are reproduced in opcodes for various mnemonics are
Appendix D. presented alphabetical
in

Table 4.1 8085A CPU

INSTRUCTIONS (MNEMONICS) IN OPERATION
CODE SEQUENCE
2

NOP LXI B STAX B INX B INR B

LXI D DCR B MVI B RLC
STAX D INX D INR D
RIM DCR D MVI D RAL
LXI SHLD INX1 INR
SIM LXI SP DCR H MVI H DAA
STA INX SP
tov B,B MOV B.C MOV B,D
INRM DCR M MVI M STC
MOV B,E MOV B,H MOV BL MOV B,M MOV BA
MOV D,B MOV D,C MOV D,D MOV D,E MOV D,H MOV DL MOV D,M MOV DA
MOV HB MOV HC MOV HD MOV HE MOV HH
MOV MB MOV HL MOV H,M MOV HA
MOV M,C MOV MD MOV ME MOV M,H MOV ML HLT MOV MA

ADD B ADD C ADD D ADD E ADD H

9 SUB B SUB C SUB D SUB E
ADD L ADD M ADD A

A ANA B ANA C SUB H SUB L SUB M SUB A

B ORA B ORA C
ANA D ANA E ANA H ANA L ANA M ANA A
ORA D ORA E
RNZ POP B JNZ
ORA ORA L ORA M ORA A
JMP CNZ PUSH B ADI RST 0
D RNC POP D JNC OUT CNC PUSH D SUI RST 2
RPO POP H JPO XTHL CPO PUSH H ANI RST 4
RP POP PSWN JP D1 CP PUSH PSW ORI RST 6

B C D E

DAD B LDAX B DCX B INRRC DCR C MVI C RRC

1 DAD D LDAX D DCX D INR E DCR E MVI E RAR
DAD H LHLD DCX H INR L DCR L L CMA
MVI
DAD SP LDA DCX SP INR A DCR A MVIA CMC
MOV CB MOV C,C MOV CD MOV C.E MOV CH MOV CL MOV C,M MOV CA
MOV E,BB MOV E,C MOV ED MOV E,E MOV E,H MOV EL MOV EM MOV EA
MOV LB MOV LC MOV LD MOV LE MOV LH MOV LL MOV LM MOV LA
MOV A,B MOV A,C MOV A,D MOV A,E MOV A,H MOV A,L MOV A,M MOV AA

ADC B ADC C ADC D ADC ADC H ADC L ADC M ADC A

9 SBB B SBB C SBB D SBB SBB H SBB L SBB M SBB A
A XRA B XRA C XRA D XRA E XRA H XRA L XRA M XRA A
B CMP B CMP C CMP D CMP E CMP H CMP L CMP M CMP A
RZ RET JZ CZ CALL ACI RST 1
RC JC IN CC SBI RST 3
RPE PCHL JPE XCHG CPE XRI RST 5
F RM SPHL JM EI CM CPI RST 7
Mnemonics Copyright: Intel Corporation.

Exampie: 1CH is the Opcode for INR E. CIH is the Opcode for POPB.

37
 INTRODUCTION TO MICROPROCESSORS

The 8085A instructions are presented below in terms of their functional grouping:

4.1 DATA TRANSFER GROUP"

This group consists of the following set ofinstructions

MVI r,data
MVI M,data
MOV r1,12
MOV M,r
MOV r,M
LXI rp,data
STA addr
LDA addr
SHLD addr
LHLD addr
LDAX rp
STAX rp
XCHG

MVI r,data (Move data immediate to register r)

This instruction directly loads a single register with a single byte of data that follows the opcode.

MVI M,data (Move data immediate to memory whose address is in H and L)

This instruction directly stores the data that follows the opcode in the memory location specifñed
by the contents of the H and L registers.

MOV r1,2 (Move data from register to register; r2 to r1)

This instruction transfers the contents of one register to another register.

MOV Mr (Move data from register r to memory whose address is in H and L)

This instruction transfers data from the source register to an address which is pointed to by H
and L registers.

In the description of instructions, r represents a register, rp a register pair, and addr an address.

38
 THE 8085A INSTRUCTiON SET

MOV r,M (Move data from location specified by H and L registers to register r)

This instruction transfers data from a location whose address is in H and L registers to the
destination register r.

LXI p,data (Load immediate register pair with double byte data)

This instruction loads immediately the double byte 16-bit data into a register pair or into the SP
register. The register pair may be BC, DE or HL

STA addr (Store data from A direct at the address that follows)

This stores in the memory the contents of the Aceumulator in the address that is specifid.

LDA addr (Load data into A direct from the address that follows)

This instruction copies the contents of the memory location given by the address onto the

Accumulator.

SHLD addr (Store H and L direct)

The contents of the register L is stored in the memory location corresponding to the address given,
and the contents of the register H at the next address location.

LHLD addr (Load H and L direct)

This instruction copies the contents of the memory location given by the address onto the register
the register H.
L and the contents of the next address location onto

LDAX p (Load A with the contents of the memory location whose address is in rp)

Accumulator the contents of the memory location whose address

This instruction copies onto the
(BC or DE only).
is given by the contents of register pair

STAX rp (Store contents of A in memory whose address is in register pair BC or DE)

of the Accumulator at the memory location whose address is

This instruction stores the contents
given by register pair (BC or DE only).

39
 INTRODUCTION TO MICROPROCESSORS

XCHG (Exchange contents of register H with D and L with E)

of L with that of E.
s nstruction exchanges the contents of the register H with that of D, and

4.2 ARITHMETIC GROUP

4.2.1 Increment and Decrement

This group consists of the following set of instructions:

INR r
INR M
INX rp
DCR r
DCR M
DCX rp

INR r (lncrement register)

incremented by one. All flags except Carry are affected.
The contents of the specified register are

INR M (Increment data in memory)

HL incremented by one. Al flags

of the memory location whose address is in
are
The contents

except Carry are affected.

INXrp Increment register pair)

The contents of the specifed register pair are incremented by one. No flags are affected.

DCR r Decrement register)

The contents of the specified register are decremented by one. All flags except Carry are affected.

DCR M (Decrement data in memory)

The contents of the memory location whose address is in HL decremented by All

are one. flags
except Carry are affected.

40

3325
 THE 8085A
INSTRUCTION SET
DCX p (Decrement register pair)

The contents of the specified register pair are

decremented by one. No flags are affected.

4.2.2 Add

This group consists of the following set of instructions:

ADD r
ADD M
ADI data
ADC r
ADC M
ACI data
DAD p

ADD r (Add registerr to A)

The contents of the specified register are added to the contents of the Accumulator. The result is
stored in the Accumulator. All flags are affected.

ADD M (Add data in memory to A)

The contents of the memory location whose address is in HL are added to the Accumulator. All
flags are affected.

ADI data (Add data Immediate to A)

The data given is added to the contents of the Accumulator. The result is stored in the
Accumulator. All flags are affected.

ADC r (Add register r with carry to A)

If the Carry flag is set by some previous operation, it adds 1 and the contents of
register r to A,
else it adds the contents of r only. The result remains in the Accumulator. All
fagsare affected.
ADC M (Add data in memory to A with Car1y)

If the Carry flag is set by some previous operation, it adds 1 and the contents of
the memory
location whose address is in HL to A, else it adds the memory contents
only. The result remains
in the Accumulator. All flags are affected.

41
 I N T R O D U C T I O N T O M I C R O P R O C E S s O R S

with carry)
ACI data (Add immediate data to A dat.
adds only the given ata.
data to A, else it
1 and the given
flag is set, then it adds aifected.
All flags are
in A.
h e Carryremains
The result

H and L)
DAD p (Add register pair rp to
the specified register pair
is added
contents of
could be BC, DE, HL or SP. The affected.
The register pair is
the Carry flag
remains in HL. Only
to H and L The result

4.2.3 Subtract

set of instructions:
This group consists of the following

SUBr
SUB M
SUI data
SBBr
SBB M
SBI data

SUB r (Subtract register r from A)

The contents of the specified register are subtracted from A. IfA is less than r, the Carry (Borrow)
lag is set. The result remains in A. All flags are affected.

SUB M (Subtract data in memory from A)

The contents of the memory location whose address is in HL are

subtracted from A. If A is less
than the memory data, the Carry (Borrow) flag is set. The
result remains in A. All lags are
affected.

SUI data (Subtract Immediate from A)

The given data is subtracted from A. If A is less than the
remains in A. All flags are affected. data, the Carry flag is set. The result

SBB r (Subtract register r from A with

borrow)
The contents of the
is set by some specifñed register are subtracted
the
previous from A along with
contents of r are operation, then 1 borrow. If the Carry
subtracted. "The resultplus the contents of r are
remains in the subtracted frpm A, else iag
ony
Accumulator. All flags are affectea.
42
 THE 80854A
INSTRUCTION SET
SBB M (Subtract memory data from A
with borrow)
The contents of the
memory location whose address is
borrow. F the Carry lag
is set by some in HL are subtracted from A along wiu
previous operation,
subtracted from A, else only the memory contents are then 1 plus the memory contents ard
flags are affected. subtracted. The result remains in A. Au

SBI data (Subtract Immediate data from A with borrow

The given data is subtracted from A with borrow. If the Carry flag is set by some
operation, then 1 plus the data are subtracted from A, else only the given data is subtracted
previrom
A, The result remains in A. All are
flags affected.

4.2.4 Decimal Adjust Accumulator

DAA Decimal adjust A)

This adjusts A to packed BCD (Binary Coded Decimal) after addition of two BCDs. It functions
in two steps:

1. f the lower 4-bits of A are greater than 9 or the Auxiliary Carry flag is set, then it adds 06H
to A

2. Subsequently, if the higher 4-bits of A are now greater than 9 or the Carry flag is set, it adds
60H to A. This affects all flags.

4.3 BRANCH GROUP

4.3.1 Jump

This group consists of the following set of instructions:

JMP addr
Jcond addr
PCHL

JMP addr (Jump unconditionaly to the address)

This loads the PC with the address given, and resumes the program execution from this location.
 INTRODUCTION TO MICROPROCESSORS
Jeond addr (Jump conditionally to the address given)
nis instruction causes a jump to the given address if a specified condition is satisfied. The
conditions could be
JC Jump on Carry C-1
JNC Jump on not Carry C-0
JP Jump on Positive S=0
JM Jump on Minus 1
JPE Jump on Parity even P-1
JPO Jump on Parity odd P-0
JZ Jump on Zero Z-1
JNZ Jump on not Zero Z-0

PCHL (H and L to Program Counter)

Counter. The program control is
This instruction copies the contents of HL into the Program
transferred to the location whose address is in HL.

4.3.2 Call

This group consists of the following set of instructions:

CALL addr
Ccond. addr

CALL addr (Call unconditionally a subroutine at the address given)

This pushes the current PC contents onto the Stack and loads the given address onto the PC;
thus, the CPU jumps to the given address. The Stack Pointer is decremented by two.

Ceond. addr (Call the subroutine at the given address conditionally)

This instruction Calls the subroutine at the given address if a specified condition is satisfied. The
Stack Pointer is decremented by two. The following conditional Calls can be made:

CC Call on Carry C 1
CNC Call on not Carry C-0
CP Call on Positive S-0
CM Call on Minus S-1
CPE Call on Parity even P-1

44
 THE 8085A
INSTRUCTION SET
CPO Call on Parity odd
CZ Call on Zero
P-0
Z-1
CNZ Call on not Zero
Z-0

4.3.3 Return

This group consists of the

following set of instructions:
RET
Rcond addr

RET (Return from the subroutine

unconditionally)
This instruction pops PC off the
Stack, and thus jumps next to the instruction from where it
CALLed. Note that when a CALL instruction is was
executed,
current PC address) is pushed onto the Stack.] The Stack
the address of the next instruction (the
Pointer is incremented by two.

Reond (Return from the subroutine

conditionaly)
This instruction returns the control to the main program (after execution of, for example, a CALL
instruction) if the specified condition is satisfied. The changes in contents of PC and SP are the
same as in an unconditional RET. The
following conditional return instructions are possible:
RC Return on Carry C-1
RNC Return on not Carry C= 0
RP Return on Positive S-0
RM Return on Minus S-1
RPE Return on Parity even P=1
RPO Return on Parity odd P=0
RZ Return on Zero Z 1
RNZ Return on not Zero Z-0

4.3.4 Restart

This group consists of Restart instructions.

RST n (Restart n:0 to 7)

This instruction transfers the control to the specific memory addresses as listed below. This
instruction is equivalent to a fixed address CALL instruction. All RST instructions save the
current Program Counter at the top of the Stack. The Stack Pointer is decremented by two. The
destination address is eight times n (in hexadecimal).

45
 INTRODUCTION TO MICROPROCESSORS

Mnemonic form Opcode Destination Address (H)

RST 0 C7 0000
RST 1 CF 0008
RST 2 D7 0010
RST 3 DF 0018
RST 4 E7 0020
RST 5 EF 0028
RST 6 F7 0030
RST 7 FF 0038

4.4 LOGIC GROUP

4.4.1 Logical Operations

following set of instructions:

This roup consists of the

ANAr
ANA M
ANI data
XRAr
XRA M
XRI data
ORA r
ORA M
ORI data
CMP r
CMP M
CPI data
STC
CMC
CMA

ANA r (AND register with A)

This instruction logically ANDs the contents of the specified register with those of the
A.ceumulator bit by bit and places the result in the Accumulator. The Carry flag is cleared and the
Auxiliary Carry flag is set. All flags are affected.

ANA M (AND memory contents with A)

This instructuion logically ANDs the contents of the memory location whose address is in HL with
by result Aceumulator. The Carry flag is
those of the Aceumulator bit bit and places the
cleared and the Auxiliary Carry flag is set. All flags are affected.
in the

46
 THE 8085A
INSTRUCTIiON SET
ANI data (AND Immediate with A)

This instruction ANDs bit by bit the

os the results in the Accumulator. contents
stores The
of the
Accumulator with the 8-bit given data and
All flags are affected. Carry flag is cleared and the
Auxiliary Carry lag is set.

XRAr (Exclusive OR register with A)

This instruction performs Exclusive OR operation bit

an

specifñed register and places the result by

bit between the contents
Accumulator and the o the
in A. All flags are affected. Both the
Carry and Auxilíary Carry flags are cleared.

XRA M (Exclusive OR memory contents with A)

This instruction performs an Exclusive OR
operation bit by bit between the contents ot the
memory location wh0se address is in HL and the Accumulator and places the result in A. AI 1ags
are affected. Both the Carry and Auxiliary Carry flags are cleared.

XRI data ( Exclusive OR Immediate with A)

This instruction performs an Exclusive OR operation bit by bit between the contents of the
Accumulator and the 8-bit data that is given. The result is stored in the Accumulator. All fags
are affected. Both the Carry and Auxiliary Carry flags are cleared.

ORA r (OR register r with A)

between the contents of the specified register r

This instruction performs a bit by bit OR operation
result is stored in A. All lags are affected. Both the
with the contents of the Accumulator. The
cleared.
Carry and Auxiliary Carry flags are

ORA M (OR memory contents

with A)

of the memory location

bit by bit OR operation between the contents
This instruction performs a
Accumulator. The result is stored in A. A flags
contents of the
whose address is in HL with the cleared.
areaffected. Both the Carry and
Auxiliary Carry flags are

with A)
ORI data (OR Immediate data
between the contents of the Accumulator
and
This instruction performs a bit by bit OR operation affected. Both
in the Accumulator. All flags are
The result is stored
the 8-bit data that is given.
are cleared.
the Carry and Auxiliary Carry flags

47
 MICROPROCESSORS

RAL
CY MSB LSB

BIT MOVEMENT PATTERN

Figure 4.3 Effect of RAL instruction

RAR

CY
LSB
MSB

BIT MOVEMENT PATTERN

Figure 4.4 Effect of RAR instruction

RLC, RRC are equivalent to 8-bit rotate, and RAL, RAR are equivalent to 9-bit rotate instructions.

4.5 STACK OPERATIONS, I/0, AND MACHINE CONTROL INSTRUCTIONS

4.5.1 Stack Operations

This group consists of the following set of instructions:

PUSH rpP
PUSH PSW
POP rp
POP PSWW
XTHL
SPHL

PUSH p (Push register pair rp onto Stack)

The register pair could be BC, DE, or HL. As a result of the PUSH operation, SP is decremented
and the high-order byte of rp is copied onto the location pointed to by SP; SP is again decremented
the low-order byte of rp is copied onto the location pointed to by SP. None of the lags are
affected

50
 THE 8085A INSTRUCTION SET
PUSH PSW (Push Processor Status Word onto Stack)

PSW is the Program Status Word; it consists of the Accumulator and Flag registers with
Accumulator as the high-order byte. As a result of the PUSH operation, SP is decremented and
the high-orderbyte (A) is copied onto the location pointed to by SP; SP is again decremented and
the low-order byte (Flag register) is copied onto the locatio to by SP. None of the flags
are affected.
pointe

POP rp Pop register pair off the Stack)

to by SP
The register pair could be BC, DE, or HL. It copies the contents of the location pointed
of rp, increments SP, and copies the contents of the location pointed t
onto the low-order byte
by SP onto the high-order byte of rp. None of the flags are affected.

POP PSw (Pop Processor Status Word off the Stack)

low-order byte of the PSW (Flag

Itcopies the contents of the location pointed to by SP onto the SP onto the high
register), increments SP, and copies the contents of the location pointed by
to

order byte of the PSW (A). All the flags are affected.

XTHL (Exchange top of Stack with H and L)

and
of the Stack location pointed to by the SP,
The contents of L are exchanged with the contents contents
at the next Stack location (SP+1). The
the contents of H are exchanged with the contents
of the flags are affected.
of Stack Pointer register are not altered. None

SPHL (H and L to Stack Pointer)

contents of HL onto the Stack Pointer register. H provides the high-

This instruction copies the the address.
the low-order byte of
order byte of the address while L provides

4.5.2 Input/Output

following set of instructions:

This group consists of the

IN addr
OUT addr

51
 INTRODUCTION TO MICROPROCESSORS

IN addr lnput)

contents of the port whose address

is specified by
This instruction puts into the Accumulator the
the one byte address. No flags are affected.

oUT addr (Output)

byte address
This instruction transfers the contents of the Accumulator
onto the port whose one

is specified. No flags are affected.

4.5.3 Machine Control

This group consists of the following set of instructions:

EI
DI
NOP
HLT
SIM
RIM

EI (Enable interrupts)

This instruction sets the interrupt enable flip-flop. The interrupts are enabled following the
execution of the next instruction.

DI (Disable interrupts)

This instruction resets the interrupt enable flip-lop. The interrupts are disabled immediately
following the execution of this instruction. An interrupt occurring during the execution of this
instruction is not recogmised.

NOP (No operation)

This instruction does nothing at al.

HLT (Hat the processor)

This instruction. halts the processor. It can be restarted by a valid interrupt or by applying a
RESET.

This is a one byte Port address.

52
 THE 8086A INSTRUCTION SET

SIM (Set interrupt mask)

Masks the interrupt(s) as desired. It also sends out serial data through the SOD pin. For this, a
command byte needs to be first loaded in A. The pattern for the command byte is:

D D DD DD2 Do

D7: (SOD): Serial data output.

D6: (SOE): Serial output enable. This should be 1 to enable SoD.
D5: (X): Don't care. It can be either 1 or 0.
D4: (RST 7.5): Reset RST 7.5 flip-flop.
D3: (MSE): Mask set enable. It should be 1 to make D0-D2 effective.
D2: (M 7.5): Mask RST 7.5. Masks if 1 and unmasks if 0
D1: (M 6.5): Mask RST 6.5. Masks if 1 and unmasks if 0.
D0: (M 5.5): Mask RST 5.5. Masks if 1 and unmasks if 0.

RIM (Read interrupt mask)

also be used to read serial data through
This copies the status of the interrupts into A. This
can

the SID pin. The pattern of the status byte is:

D D DsD.D D D Do

Serial input data.

D7: (SID):
Set if RST 7.5 is pending.
D6: (17.5) Set if RST 6.5 is pending.
D5: (T6.5):
Set if RST 5.5 is pending.
D4: 15.5): is set.
(TE): Set if interrupt enable flag
D3: masked.
D2: CM7.5): Set if RST 7.5 is
RST 6.5 is masked.
Set if
D1: (M6.5): 5.5 is masked.
(M5.5): Set if RST
DO:

53
 INTRODUCTION TO MICROPROCESSORS

Table 4.1 Summary of Flags Set in Instruction Execution

Logic Group Stack, 1/0,

Data Transfer Arithmetic Branch Machine Control Group
Group Group Group
NO FLAGS
NO FLAGS ALL FLAGS
NO FLAGS ALL FLAGS (cxceptions as
(Cxceptions as
(cxccptions as indicated)
indicated)
indicated)

ANA r IN port
MOV 1,2 ADD r JMP addr Out Port
JMP Cond addr ANA M
MOV Mr ADD M XTHL
CALL addr ANI data
MOV r,M ADI data SPHL
CALL Cond addr ORA r
MVI r,data ADC r
ORA M
MVI M,data ADC M RET
RET Cond ORI data
ACI data
XRA r
LXI rp,data DAA PCHL PUSH Ip (NSP)
XRA M
SUB RST n PUSH PSw
XRI data
STA addr SUB M POP p (NSP)
LDA addr SUI data POP PSW (AFL)
CMP r
SBBr
CMP M
STAX p SBB M
CPI data
LDAX rp SBI data NOP
HLT
LHLD addr INR r (NCY)
SHLD addr INR M (NCY) CMA (NFL)
EI
DCR r (NCY)
RLC (CY) DI
XCHG DCR M (NCY)
RRC (CY RIM
RAL (CY) SIM
INX rp (NFL)
DCX rp (NFL) RAR (CY
STC (CY)
DAD rp (CY) CMC (CY)D

Source: AJ
=
= BC, DE
=
A , B, C, D, E, H, L; rp BC, DE, HL, SP;Allrp'but
Borrow; NCY = Carry; NFL No Flags
Auxiliary Carry # Auxiliary =
=
CY Only Carry; NSP Except SP; AFL All Flags